UefiCpuPkg/Include/Register/LocalApic.h

   1 /** @file
   2   IA32 Local APIC Definitions.
   3
   4   Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef __LOCAL_APIC_H__
  16 #define __LOCAL_APIC_H__
  17
  18 //
  19 // Definitions for IA32 architectural MSRs
  20 //
  21 #define MSR_IA32_APIC_BASE_ADDRESS              0x1B
  22
  23 //
  24 // Definition for Local APIC registers and related values
  25 //
  26 #define XAPIC_ID_OFFSET                         0x20
  27 #define XAPIC_VERSION_OFFSET                    0x30
  28 #define XAPIC_EOI_OFFSET                        0x0b0
  29 #define XAPIC_ICR_DFR_OFFSET                    0x0e0
  30 #define XAPIC_SPURIOUS_VECTOR_OFFSET            0x0f0
  31 #define XAPIC_ICR_LOW_OFFSET                    0x300
  32 #define XAPIC_ICR_HIGH_OFFSET                   0x310
  33 #define XAPIC_LVT_TIMER_OFFSET                  0x320
  34 #define XAPIC_LVT_LINT0_OFFSET                  0x350
  35 #define XAPIC_LVT_LINT1_OFFSET                  0x360
  36 #define XAPIC_TIMER_INIT_COUNT_OFFSET           0x380
  37 #define XAPIC_TIMER_CURRENT_COUNT_OFFSET        0x390
  38 #define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0
  39
  40 #define X2APIC_MSR_BASE_ADDRESS                 0x800
  41 #define X2APIC_MSR_ICR_ADDRESS                  0x830
  42
  43 #define LOCAL_APIC_DELIVERY_MODE_FIXED           0
  44 #define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1
  45 #define LOCAL_APIC_DELIVERY_MODE_SMI             2
  46 #define LOCAL_APIC_DELIVERY_MODE_NMI             4
  47 #define LOCAL_APIC_DELIVERY_MODE_INIT            5
  48 #define LOCAL_APIC_DELIVERY_MODE_STARTUP         6
  49 #define LOCAL_APIC_DELIVERY_MODE_EXTINT          7
  50
  51 #define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND       0
  52 #define LOCAL_APIC_DESTINATION_SHORTHAND_SELF               1
  53 #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2
  54 #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3
  55
  56 typedef union {
  57   struct {
  58     UINT32  Reserved0:8;     ///< Reserved.
  59     UINT32  Bsp:1;           ///< Processor is BSP.
  60     UINT32  Reserved1:1;     ///< Reserved.
  61     UINT32  Extd:1;          ///< Enable x2APIC mode.
  62     UINT32  En:1;            ///< xAPIC global enable/disable.
  63     UINT32  ApicBaseLow:20;  ///< APIC Base physical address. The actual field width depends on physical address width.
  64     UINT32  ApicBaseHigh:32;
  65   } Bits;
  66   UINT64    Uint64;
  67 } MSR_IA32_APIC_BASE;
  68
  69 //
  70 // Local APIC Version Register.
  71 //
  72 typedef union {
  73   struct {
  74     UINT32  Version:8;                  ///< The version numbers of the local APIC.
  75     UINT32  Reserved0:8;                ///< Reserved.
  76     UINT32  MaxLvtEntry:8;              ///< Number of LVT entries minus 1.
  77     UINT32  EoiBroadcastSuppression:1;  ///< 1 if EOI-broadcast suppression supported.
  78     UINT32  Reserved1:7;                ///< Reserved.
  79   } Bits;
  80   UINT32    Uint32;
  81 } LOCAL_APIC_VERSION;
  82
  83 //
  84 // Low half of Interrupt Command Register (ICR).
  85 //
  86 typedef union {
  87   struct {
  88     UINT32  Vector:8;                ///< The vector number of the interrupt being sent.
  89     UINT32  DeliveryMode:3;          ///< Specifies the type of IPI to be sent.
  90     UINT32  DestinationMode:1;       ///< 0: physical destination mode, 1: logical destination mode.
  91     UINT32  DeliveryStatus:1;        ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.
  92     UINT32  Reserved0:1;             ///< Reserved.
  93     UINT32  Level:1;                 ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.
  94     UINT32  TriggerMode:1;           ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.
  95     UINT32  Reserved1:2;             ///< Reserved.
  96     UINT32  DestinationShorthand:2;  ///< A shorthand notation to specify the destination of the interrupt.
  97     UINT32  Reserved2:12;            ///< Reserved.
  98   } Bits;
  99   UINT32    Uint32;
 100 } LOCAL_APIC_ICR_LOW;
 101
 102 //
 103 // High half of Interrupt Command Register (ICR)
 104 //
 105 typedef union {
 106   struct {
 107     UINT32  Reserved0:24;   ///< Reserved.
 108     UINT32  Destination:8;  ///< Specifies the target processor or processors in xAPIC mode.
 109   } Bits;
 110   UINT32    Uint32;         ///< Destination field expanded to 32-bit in x2APIC mode.
 111 } LOCAL_APIC_ICR_HIGH;
 112
 113 //
 114 // Spurious-Interrupt Vector Register (SVR)
 115 //
 116 typedef union {
 117   struct {
 118     UINT32  SpuriousVector:8;           ///< Spurious Vector.
 119     UINT32  SoftwareEnable:1;           ///< APIC Software Enable/Disable.
 120     UINT32  FocusProcessorChecking:1;   ///< Focus Processor Checking.
 121     UINT32  Reserved0:2;                ///< Reserved.
 122     UINT32  EoiBroadcastSuppression:1;  ///< EOI-Broadcast Suppression.
 123     UINT32  Reserved1:19;               ///< Reserved.
 124   } Bits;
 125   UINT32    Uint32;
 126 } LOCAL_APIC_SVR;
 127
 128 //
 129 // Divide Configuration Register (DCR)
 130 //
 131 typedef union {
 132   struct {
 133     UINT32  DivideValue1:2;  ///< Low 2 bits of the divide value.
 134     UINT32  Reserved0:1;     ///< Always 0.
 135     UINT32  DivideValue2:1;  ///< Highest 1 bit of the divide value.
 136     UINT32  Reserved1:28;    ///< Reserved.
 137   } Bits;
 138   UINT32    Uint32;
 139 } LOCAL_APIC_DCR;
 140
 141 //
 142 // LVT Timer Register
 143 //
 144 typedef union {
 145   struct {
 146     UINT32  Vector:8;          ///< The vector number of the interrupt being sent.
 147     UINT32  Reserved0:4;       ///< Reserved.
 148     UINT32  DeliveryStatus:1;  ///< 0: Idle, 1: send pending.
 149     UINT32  Reserved1:3;       ///< Reserved.
 150     UINT32  Mask:1;            ///< 0: Not masked, 1: Masked.
 151     UINT32  TimerMode:1;       ///< 0: One-shot, 1: Periodic.
 152     UINT32  Reserved2:14;      ///< Reserved.
 153   } Bits;
 154   UINT32    Uint32;
 155 } LOCAL_APIC_LVT_TIMER;
 156
 157 //
 158 // LVT LINT0/LINT1 Register
 159 //
 160 typedef union {
 161   struct {
 162     UINT32  Vector:8;            ///< The vector number of the interrupt being sent.
 163     UINT32  DeliveryMode:3;      ///< Specifies the type of interrupt to be sent.
 164     UINT32  Reserved0:1;         ///< Reserved.
 165     UINT32  DeliveryStatus:1;    ///< 0: Idle, 1: send pending.
 166     UINT32  InputPinPolarity:1;  ///< Interrupt Input Pin Polarity.
 167     UINT32  RemoteIrr:1;         ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.
 168     UINT32  TriggerMode:1;       ///< 0:edge, 1:level.
 169     UINT32  Mask:1;              ///< 0: Not masked, 1: Masked.
 170     UINT32  Reserved1:15;        ///< Reserved.
 171   } Bits;
 172   UINT32    Uint32;
 173 } LOCAL_APIC_LVT_LINT;
 174
 175 //
 176 // MSI Address Register
 177 //
 178 typedef union {
 179   struct {
 180     UINT32  Reserved0:2;         ///< Reserved
 181     UINT32  DestinationMode:1;   ///< Specifies the Destination Mode.
 182     UINT32  RedirectionHint:1;   ///< Specifies the Redirection Hint.
 183     UINT32  Reserved1:8;         ///< Reserved.
 184     UINT32  DestinationId:8;     ///< Specifies the Destination ID.
 185     UINT32  BaseAddress:12;      ///< Must be 0FEEH
 186   } Bits;
 187   UINT32    Uint32;
 188 } LOCAL_APIC_MSI_ADDRESS;
 189
 190 //
 191 // MSI Address Register
 192 //
 193 typedef union {
 194   struct {
 195     UINT32  Vector:8;            ///< Interrupt vector in range 010h..0FEH
 196     UINT32  DeliveryMode:3;      ///< Specifies the type of interrupt to be sent.
 197     UINT32  Reserved0:3;         ///< Reserved.
 198     UINT32  Level:1;             ///< 0:Deassert, 1:Assert.  Ignored for Edge triggered interrupts.
 199     UINT32  TriggerMode:1;       ///< 0:Edge,     1:Level.
 200     UINT32  Reserved1:16;        ///< Reserved.
 201     UINT32  Reserved2:32;        ///< Reserved.
 202   } Bits;
 203   UINT64    Uint64;
 204 } LOCAL_APIC_MSI_DATA;
 205
 206 #endif
 207