7535ef50e95ef0777b55ddcf0e7bd35be8d11bde
[mirror_edk2.git] / UefiCpuPkg / Include / Register / LocalApic.h
1 /** @file
2 IA32 Local APIC Definitions.
3
4 Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #ifndef __LOCAL_APIC_H__
16 #define __LOCAL_APIC_H__
17
18 //
19 // Definitions for IA32 architectural MSRs
20 //
21 #define MSR_IA32_APIC_BASE_ADDRESS 0x1B
22
23 //
24 // Definitions for CPUID instruction
25 //
26 #define CPUID_VERSION_INFO 0x1
27 #define CPUID_EXTENDED_FUNCTION 0x80000000
28 #define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
29
30 //
31 // Definition for Local APIC registers and related values
32 //
33 #define XAPIC_ID_OFFSET 0x0
34 #define XAPIC_EOI_OFFSET 0x0b0
35 #define XAPIC_ICR_DFR_OFFSET 0x0e0
36 #define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0
37 #define XAPIC_ICR_LOW_OFFSET 0x300
38 #define XAPIC_ICR_HIGH_OFFSET 0x310
39 #define XAPIC_LVT_TIMER_OFFSET 0x320
40 #define XAPIC_LINT0_VECTOR_OFFSET 0x350
41 #define XAPIC_LINT1_VECTOR_OFFSET 0x360
42 #define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380
43 #define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390
44 #define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0
45
46 #define X2APIC_MSR_BASE_ADDRESS 0x800
47 #define X2APIC_MSR_ICR_ADDRESS 0x830
48
49 #define LOCAL_APIC_DELIVERY_MODE_FIXED 0
50 #define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1
51 #define LOCAL_APIC_DELIVERY_MODE_SMI 2
52 #define LOCAL_APIC_DELIVERY_MODE_NMI 4
53 #define LOCAL_APIC_DELIVERY_MODE_INIT 5
54 #define LOCAL_APIC_DELIVERY_MODE_STARTUP 6
55 #define LOCAL_APIC_DELIVERY_MODE_EXTINT 7
56
57 #define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0
58 #define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1
59 #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2
60 #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3
61
62 typedef union {
63 struct {
64 UINT64 Reserved0:8; ///< Reserved.
65 UINT64 Bsp:1; ///< Processor is BSP.
66 UINT64 Reserved1:1; ///< Reserved.
67 UINT64 Extd:1; ///< Enable x2APIC mode.
68 UINT64 En:1; ///< xAPIC global enable/disable.
69 UINT64 ApicBase:52; ///< APIC Base physical address. The actual field width depends on physical address width.
70 } Bits;
71 UINT64 Uint64;
72 } MSR_IA32_APIC_BASE;
73
74 //
75 // Low half of Interrupt Command Register (ICR).
76 //
77 typedef union {
78 struct {
79 UINT32 Vector:8; ///< The vector number of the interrupt being sent.
80 UINT32 DeliveryMode:3; ///< Specifies the type of IPI to be sent.
81 UINT32 DestinationMode:1; ///< 0: physical destination mode, 1: logical destination mode.
82 UINT32 DeliveryStatus:1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.
83 UINT32 Reserved0:1; ///< Reserved.
84 UINT32 Level:1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.
85 UINT32 TriggerMode:1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.
86 UINT32 Reserved1:2; ///< Reserved.
87 UINT32 DestinationShorthand:2; ///< A shorthand notation to specify the destination of the interrupt.
88 UINT32 Reserved2:12; ///< Reserved.
89 } Bits;
90 UINT32 Uint32;
91 } LOCAL_APIC_ICR_LOW;
92
93 //
94 // High half of Interrupt Command Register (ICR)
95 //
96 typedef union {
97 struct {
98 UINT32 Reserved0:24; ///< Reserved.
99 UINT32 Destination:8; ///< Specifies the target processor or processors in xAPIC mode.
100 } Bits;
101 UINT32 Uint32; ///< Destination field expanded to 32-bit in x2APIC mode.
102 } LOCAL_APIC_ICR_HIGH;
103
104 //
105 // Spurious-Interrupt Vector Register (SVR)
106 //
107 typedef union {
108 struct {
109 UINT32 SpuriousVector:8; ///< Spurious Vector.
110 UINT32 SoftwareEnable:1; ///< APIC Software Enable/Disable.
111 UINT32 FocusProcessorChecking:1; ///< Focus Processor Checking.
112 UINT32 Reserved0:2; ///< Reserved.
113 UINT32 EoiBroadcastSuppression:1; ///< EOI-Broadcast Suppression.
114 UINT32 Reserved1:19; ///< Reserved.
115 } Bits;
116 UINT32 Uint32;
117 } LOCAL_APIC_SVR;
118
119 //
120 // Divide Configuration Register (DCR)
121 //
122 typedef union {
123 struct {
124 UINT32 DivideValue1:2; ///< Low 2 bits of the divide value.
125 UINT32 Reserved0:1; ///< Always 0.
126 UINT32 DivideValue2:1; ///< Highest 1 bit of the divide value.
127 UINT32 Reserved1:28; ///< Reserved.
128 } Bits;
129 UINT32 Uint32;
130 } LOCAL_APIC_DCR;
131
132 //
133 // LVT Timer Register
134 //
135 typedef union {
136 struct {
137 UINT32 Vector:8; ///< The vector number of the interrupt being sent.
138 UINT32 Reserved0:4; ///< Reserved.
139 UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.
140 UINT32 Reserved1:3; ///< Reserved.
141 UINT32 Mask:1; ///< 0: Not masked, 1: Masked.
142 UINT32 TimerMode:1; ///< 0: One-shot, 1: Periodic.
143 UINT32 Reserved2:14; ///< Reserved.
144 } Bits;
145 UINT32 Uint32;
146 } LOCAL_APIC_LVT_TIMER;
147
148 //
149 // LVT LINT0/LINT1 Register
150 //
151 typedef union {
152 struct {
153 UINT32 Vector:8; ///< The vector number of the interrupt being sent.
154 UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.
155 UINT32 Reserved0:1; ///< Reserved.
156 UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.
157 UINT32 InputPinPolarity:1; ///< Interrupt Input Pin Polarity.
158 UINT32 RemoteIrr:1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.
159 UINT32 TriggerMode:1; ///< 0:edge, 1:level.
160 UINT32 Mask:1; ///< 0: Not masked, 1: Masked.
161 UINT32 Reserved1:15; ///< Reserved.
162 } Bits;
163 UINT32 Uint32;
164 } LOCAL_APIC_LVT_LINT;
165
166 #endif
167