2 IA32 Local APIC Definitions.
4 Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #ifndef __LOCAL_APIC_H__
16 #define __LOCAL_APIC_H__
19 // Definitions for IA32 architectural MSRs
21 #define MSR_IA32_APIC_BASE_ADDRESS 0x1B
24 // Definitions for CPUID instruction
26 #define CPUID_SIGNATURE 0x0
27 #define CPUID_VERSION_INFO 0x1
28 #define CPUID_CACHE_PARAMS 0x4
29 #define CPUID_EXTENDED_TOPOLOGY 0xB
30 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x0
31 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x1
32 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x2
33 #define CPUID_EXTENDED_FUNCTION 0x80000000
34 #define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
37 // Definition for Local APIC registers and related values
39 #define XAPIC_ID_OFFSET 0x20
40 #define XAPIC_VERSION_OFFSET 0x30
41 #define XAPIC_EOI_OFFSET 0x0b0
42 #define XAPIC_ICR_DFR_OFFSET 0x0e0
43 #define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0
44 #define XAPIC_ICR_LOW_OFFSET 0x300
45 #define XAPIC_ICR_HIGH_OFFSET 0x310
46 #define XAPIC_LVT_TIMER_OFFSET 0x320
47 #define XAPIC_LVT_LINT0_OFFSET 0x350
48 #define XAPIC_LVT_LINT1_OFFSET 0x360
49 #define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380
50 #define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390
51 #define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0
53 #define X2APIC_MSR_BASE_ADDRESS 0x800
54 #define X2APIC_MSR_ICR_ADDRESS 0x830
56 #define LOCAL_APIC_DELIVERY_MODE_FIXED 0
57 #define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1
58 #define LOCAL_APIC_DELIVERY_MODE_SMI 2
59 #define LOCAL_APIC_DELIVERY_MODE_NMI 4
60 #define LOCAL_APIC_DELIVERY_MODE_INIT 5
61 #define LOCAL_APIC_DELIVERY_MODE_STARTUP 6
62 #define LOCAL_APIC_DELIVERY_MODE_EXTINT 7
64 #define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0
65 #define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1
66 #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2
67 #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3
71 UINT32 Reserved0
:8; ///< Reserved.
72 UINT32 Bsp
:1; ///< Processor is BSP.
73 UINT32 Reserved1
:1; ///< Reserved.
74 UINT32 Extd
:1; ///< Enable x2APIC mode.
75 UINT32 En
:1; ///< xAPIC global enable/disable.
76 UINT32 ApicBaseLow
:20; ///< APIC Base physical address. The actual field width depends on physical address width.
77 UINT32 ApicBaseHigh
:32;
83 // Local APIC Version Register.
87 UINT32 Version
:8; ///< The version numbers of the local APIC.
88 UINT32 Reserved0
:8; ///< Reserved.
89 UINT32 MaxLvtEntry
:8; ///< Number of LVT entries minus 1.
90 UINT32 EoiBroadcastSuppression
:1; ///< 1 if EOI-broadcast suppression supported.
91 UINT32 Reserved1
:7; ///< Reserved.
97 // Low half of Interrupt Command Register (ICR).
101 UINT32 Vector
:8; ///< The vector number of the interrupt being sent.
102 UINT32 DeliveryMode
:3; ///< Specifies the type of IPI to be sent.
103 UINT32 DestinationMode
:1; ///< 0: physical destination mode, 1: logical destination mode.
104 UINT32 DeliveryStatus
:1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.
105 UINT32 Reserved0
:1; ///< Reserved.
106 UINT32 Level
:1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.
107 UINT32 TriggerMode
:1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.
108 UINT32 Reserved1
:2; ///< Reserved.
109 UINT32 DestinationShorthand
:2; ///< A shorthand notation to specify the destination of the interrupt.
110 UINT32 Reserved2
:12; ///< Reserved.
113 } LOCAL_APIC_ICR_LOW
;
116 // High half of Interrupt Command Register (ICR)
120 UINT32 Reserved0
:24; ///< Reserved.
121 UINT32 Destination
:8; ///< Specifies the target processor or processors in xAPIC mode.
123 UINT32 Uint32
; ///< Destination field expanded to 32-bit in x2APIC mode.
124 } LOCAL_APIC_ICR_HIGH
;
127 // Spurious-Interrupt Vector Register (SVR)
131 UINT32 SpuriousVector
:8; ///< Spurious Vector.
132 UINT32 SoftwareEnable
:1; ///< APIC Software Enable/Disable.
133 UINT32 FocusProcessorChecking
:1; ///< Focus Processor Checking.
134 UINT32 Reserved0
:2; ///< Reserved.
135 UINT32 EoiBroadcastSuppression
:1; ///< EOI-Broadcast Suppression.
136 UINT32 Reserved1
:19; ///< Reserved.
142 // Divide Configuration Register (DCR)
146 UINT32 DivideValue1
:2; ///< Low 2 bits of the divide value.
147 UINT32 Reserved0
:1; ///< Always 0.
148 UINT32 DivideValue2
:1; ///< Highest 1 bit of the divide value.
149 UINT32 Reserved1
:28; ///< Reserved.
155 // LVT Timer Register
159 UINT32 Vector
:8; ///< The vector number of the interrupt being sent.
160 UINT32 Reserved0
:4; ///< Reserved.
161 UINT32 DeliveryStatus
:1; ///< 0: Idle, 1: send pending.
162 UINT32 Reserved1
:3; ///< Reserved.
163 UINT32 Mask
:1; ///< 0: Not masked, 1: Masked.
164 UINT32 TimerMode
:1; ///< 0: One-shot, 1: Periodic.
165 UINT32 Reserved2
:14; ///< Reserved.
168 } LOCAL_APIC_LVT_TIMER
;
171 // LVT LINT0/LINT1 Register
175 UINT32 Vector
:8; ///< The vector number of the interrupt being sent.
176 UINT32 DeliveryMode
:3; ///< Specifies the type of interrupt to be sent.
177 UINT32 Reserved0
:1; ///< Reserved.
178 UINT32 DeliveryStatus
:1; ///< 0: Idle, 1: send pending.
179 UINT32 InputPinPolarity
:1; ///< Interrupt Input Pin Polarity.
180 UINT32 RemoteIrr
:1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.
181 UINT32 TriggerMode
:1; ///< 0:edge, 1:level.
182 UINT32 Mask
:1; ///< 0: Not masked, 1: Masked.
183 UINT32 Reserved1
:15; ///< Reserved.
186 } LOCAL_APIC_LVT_LINT
;
189 // MSI Address Register
193 UINT32 Reserved0
:2; ///< Reserved
194 UINT32 DestinationMode
:1; ///< Specifies the Destination Mode.
195 UINT32 RedirectionHint
:1; ///< Specifies the Redirection Hint.
196 UINT32 Reserved1
:8; ///< Reserved.
197 UINT32 DestinationId
:8; ///< Specifies the Destination ID.
198 UINT32 BaseAddress
:12; ///< Must be 0FEEH
201 } LOCAL_APIC_MSI_ADDRESS
;
204 // MSI Address Register
208 UINT32 Vector
:8; ///< Interrupt vector in range 010h..0FEH
209 UINT32 DeliveryMode
:3; ///< Specifies the type of interrupt to be sent.
210 UINT32 Reserved0
:3; ///< Reserved.
211 UINT32 Level
:1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts.
212 UINT32 TriggerMode
:1; ///< 0:Edge, 1:Level.
213 UINT32 Reserved1
:16; ///< Reserved.
214 UINT32 Reserved2
:32; ///< Reserved.
217 } LOCAL_APIC_MSI_DATA
;