UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h

   1 /** @file
   2   MSR Definitions for Intel processors based on the Broadwell microarchitecture.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
  10   This program and the accompanying materials
  11   are licensed and made available under the terms and conditions of the BSD License
  12   which accompanies this distribution.  The full text of the license may be found at
  13   http://opensource.org/licenses/bsd-license.php
  14
  15   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17
  18   @par Specification Reference:
  19   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
  20   December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-12.
  21
  22 **/
  23
  24 #ifndef __BROADWELL_MSR_H__
  25 #define __BROADWELL_MSR_H__
  26
  27 #include <Register/ArchitecturalMsr.h>
  28
  29 /**
  30   Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control
  31   Facilities.".
  32
  33   @param  ECX  MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS (0x0000038E)
  34   @param  EAX  Lower 32-bits of MSR value.
  35                Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER.
  36   @param  EDX  Upper 32-bits of MSR value.
  37                Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER.
  38
  39   <b>Example usage</b>
  40   @code
  41   MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER  Msr;
  42
  43   Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS);
  44   AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);
  45   @endcode
  46 **/
  47 #define MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS     0x0000038E
  48
  49 /**
  50   MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS
  51 **/
  52 typedef union {
  53   ///
  54   /// Individual bit fields
  55   ///
  56   struct {
  57     ///
  58     /// [Bit 0] Ovf_PMC0.
  59     ///
  60     UINT32  Ovf_PMC0:1;
  61     ///
  62     /// [Bit 1] Ovf_PMC1.
  63     ///
  64     UINT32  Ovf_PMC1:1;
  65     ///
  66     /// [Bit 2] Ovf_PMC2.
  67     ///
  68     UINT32  Ovf_PMC2:1;
  69     ///
  70     /// [Bit 3] Ovf_PMC3.
  71     ///
  72     UINT32  Ovf_PMC3:1;
  73     UINT32  Reserved1:28;
  74     ///
  75     /// [Bit 32] Ovf_FixedCtr0.
  76     ///
  77     UINT32  Ovf_FixedCtr0:1;
  78     ///
  79     /// [Bit 33] Ovf_FixedCtr1.
  80     ///
  81     UINT32  Ovf_FixedCtr1:1;
  82     ///
  83     /// [Bit 34] Ovf_FixedCtr2.
  84     ///
  85     UINT32  Ovf_FixedCtr2:1;
  86     UINT32  Reserved2:20;
  87     ///
  88     /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.4.2, "Table of Physical
  89     /// Addresses (ToPA).".
  90     ///
  91     UINT32  Trace_ToPA_PMI:1;
  92     UINT32  Reserved3:5;
  93     ///
  94     /// [Bit 61] Ovf_Uncore.
  95     ///
  96     UINT32  Ovf_Uncore:1;
  97     ///
  98     /// [Bit 62] Ovf_BufDSSAVE.
  99     ///
 100     UINT32  OvfBuf:1;
 101     ///
 102     /// [Bit 63] CondChgd.
 103     ///
 104     UINT32  CondChgd:1;
 105   } Bits;
 106   ///
 107   /// All bit fields as a 64-bit value
 108   ///
 109   UINT64  Uint64;
 110 } MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER;
 111
 112
 113 /**
 114   Core. C-State Configuration Control (R/W) Note: C-state values are processor
 115   specific C-state code names, unrelated to MWAIT extension C-state parameters
 116   or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
 117
 118   @param  ECX  MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)
 119   @param  EAX  Lower 32-bits of MSR value.
 120                Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
 121   @param  EDX  Upper 32-bits of MSR value.
 122                Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
 123
 124   <b>Example usage</b>
 125   @code
 126   MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
 127
 128   Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);
 129   AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
 130   @endcode
 131 **/
 132 #define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL     0x000000E2
 133
 134 /**
 135   MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL
 136 **/
 137 typedef union {
 138   ///
 139   /// Individual bit fields
 140   ///
 141   struct {
 142     ///
 143     /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest
 144     /// processor-specific C-state code name (consuming the least power) for
 145     /// the package. The default is set as factory-configured package C-state
 146     /// limit. The following C-state code name encodings are supported: 0000b:
 147     /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6
 148     /// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.
 149     ///
 150     UINT32  Limit:4;
 151     UINT32  Reserved1:6;
 152     ///
 153     /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
 154     ///
 155     UINT32  IO_MWAIT:1;
 156     UINT32  Reserved2:4;
 157     ///
 158     /// [Bit 15] CFG Lock (R/WO).
 159     ///
 160     UINT32  CFGLock:1;
 161     UINT32  Reserved3:9;
 162     ///
 163     /// [Bit 25] C3 State Auto Demotion Enable (R/W).
 164     ///
 165     UINT32  C3AutoDemotion:1;
 166     ///
 167     /// [Bit 26] C1 State Auto Demotion Enable (R/W).
 168     ///
 169     UINT32  C1AutoDemotion:1;
 170     ///
 171     /// [Bit 27] Enable C3 Undemotion (R/W).
 172     ///
 173     UINT32  C3Undemotion:1;
 174     ///
 175     /// [Bit 28] Enable C1 Undemotion (R/W).
 176     ///
 177     UINT32  C1Undemotion:1;
 178     ///
 179     /// [Bit 29] Enable Package C-State Auto-demotion (R/W).
 180     ///
 181     UINT32  CStateAutoDemotion:1;
 182     ///
 183     /// [Bit 30] Enable Package C-State Undemotion (R/W).
 184     ///
 185     UINT32  CStateUndemotion:1;
 186     UINT32  Reserved4:1;
 187     UINT32  Reserved5:32;
 188   } Bits;
 189   ///
 190   /// All bit fields as a 32-bit value
 191   ///
 192   UINT32  Uint32;
 193   ///
 194   /// All bit fields as a 64-bit value
 195   ///
 196   UINT64  Uint64;
 197 } MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;
 198
 199
 200 /**
 201   Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
 202   RW if MSR_PLATFORM_INFO.[28] = 1.
 203
 204   @param  ECX  MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)
 205   @param  EAX  Lower 32-bits of MSR value.
 206                Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
 207   @param  EDX  Upper 32-bits of MSR value.
 208                Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
 209
 210   <b>Example usage</b>
 211   @code
 212   MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER  Msr;
 213
 214   Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);
 215   @endcode
 216 **/
 217 #define MSR_BROADWELL_TURBO_RATIO_LIMIT          0x000001AD
 218
 219 /**
 220   MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT
 221 **/
 222 typedef union {
 223   ///
 224   /// Individual bit fields
 225   ///
 226   struct {
 227     ///
 228     /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
 229     /// limit of 1 core active.
 230     ///
 231     UINT32  Maximum1C:8;
 232     ///
 233     /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
 234     /// limit of 2 core active.
 235     ///
 236     UINT32  Maximum2C:8;
 237     ///
 238     /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
 239     /// limit of 3 core active.
 240     ///
 241     UINT32  Maximum3C:8;
 242     ///
 243     /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
 244     /// limit of 4 core active.
 245     ///
 246     UINT32  Maximum4C:8;
 247     ///
 248     /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
 249     /// limit of 5core active.
 250     ///
 251     UINT32  Maximum5C:8;
 252     ///
 253     /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
 254     /// limit of 6core active.
 255     ///
 256     UINT32  Maximum6C:8;
 257     UINT32  Reserved:16;
 258   } Bits;
 259   ///
 260   /// All bit fields as a 64-bit value
 261   ///
 262   UINT64  Uint64;
 263 } MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;
 264
 265 #endif