UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h

   1 /** @file
   2   MSR Definitions for Intel processors based on the Broadwell microarchitecture.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
  10   SPDX-License-Identifier: BSD-2-Clause-Patent
  11
  12   @par Specification Reference:
  13   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
  14   May 2018, Volume 4: Model-Specific-Registers (MSR)
  15
  16 **/
  17
  18 #ifndef __BROADWELL_MSR_H__
  19 #define __BROADWELL_MSR_H__
  20
  21 #include <Register/ArchitecturalMsr.h>
  22
  23 /**
  24   Is Intel processors based on the Broadwell microarchitecture?
  25
  26   @param   DisplayFamily  Display Family ID
  27   @param   DisplayModel   Display Model ID
  28
  29   @retval  TRUE   Yes, it is.
  30   @retval  FALSE  No, it isn't.
  31 **/
  32 #define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \
  33   (DisplayFamily == 0x06 && \
  34    (                        \
  35     DisplayModel == 0x3D || \
  36     DisplayModel == 0x47 || \
  37     DisplayModel == 0x4F || \
  38     DisplayModel == 0x56    \
  39     )                       \
  40    )
  41
  42 /**
  43   Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control
  44   Facilities.".
  45
  46   @param  ECX  MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)
  47   @param  EAX  Lower 32-bits of MSR value.
  48                Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.
  49   @param  EDX  Upper 32-bits of MSR value.
  50                Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.
  51
  52   <b>Example usage</b>
  53   @code
  54   MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER  Msr;
  55
  56   Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS);
  57   AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);
  58   @endcode
  59   @note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
  60 **/
  61 #define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS    0x0000038E
  62
  63 /**
  64   MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS
  65 **/
  66 typedef union {
  67   ///
  68   /// Individual bit fields
  69   ///
  70   struct {
  71     ///
  72     /// [Bit 0] Ovf_PMC0.
  73     ///
  74     UINT32  Ovf_PMC0:1;
  75     ///
  76     /// [Bit 1] Ovf_PMC1.
  77     ///
  78     UINT32  Ovf_PMC1:1;
  79     ///
  80     /// [Bit 2] Ovf_PMC2.
  81     ///
  82     UINT32  Ovf_PMC2:1;
  83     ///
  84     /// [Bit 3] Ovf_PMC3.
  85     ///
  86     UINT32  Ovf_PMC3:1;
  87     UINT32  Reserved1:28;
  88     ///
  89     /// [Bit 32] Ovf_FixedCtr0.
  90     ///
  91     UINT32  Ovf_FixedCtr0:1;
  92     ///
  93     /// [Bit 33] Ovf_FixedCtr1.
  94     ///
  95     UINT32  Ovf_FixedCtr1:1;
  96     ///
  97     /// [Bit 34] Ovf_FixedCtr2.
  98     ///
  99     UINT32  Ovf_FixedCtr2:1;
 100     UINT32  Reserved2:20;
 101     ///
 102     /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical
 103     /// Addresses (ToPA).".
 104     ///
 105     UINT32  Trace_ToPA_PMI:1;
 106     UINT32  Reserved3:5;
 107     ///
 108     /// [Bit 61] Ovf_Uncore.
 109     ///
 110     UINT32  Ovf_Uncore:1;
 111     ///
 112     /// [Bit 62] Ovf_BufDSSAVE.
 113     ///
 114     UINT32  OvfBuf:1;
 115     ///
 116     /// [Bit 63] CondChgd.
 117     ///
 118     UINT32  CondChgd:1;
 119   } Bits;
 120   ///
 121   /// All bit fields as a 64-bit value
 122   ///
 123   UINT64  Uint64;
 124 } MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER;
 125
 126
 127 /**
 128   Core. C-State Configuration Control (R/W) Note: C-state values are processor
 129   specific C-state code names, unrelated to MWAIT extension C-state parameters
 130   or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
 131
 132   @param  ECX  MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)
 133   @param  EAX  Lower 32-bits of MSR value.
 134                Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
 135   @param  EDX  Upper 32-bits of MSR value.
 136                Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
 137
 138   <b>Example usage</b>
 139   @code
 140   MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
 141
 142   Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);
 143   AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
 144   @endcode
 145   @note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
 146 **/
 147 #define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL     0x000000E2
 148
 149 /**
 150   MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL
 151 **/
 152 typedef union {
 153   ///
 154   /// Individual bit fields
 155   ///
 156   struct {
 157     ///
 158     /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest
 159     /// processor-specific C-state code name (consuming the least power) for
 160     /// the package. The default is set as factory-configured package C-state
 161     /// limit. The following C-state code name encodings are supported: 0000b:
 162     /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6
 163     /// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.
 164     ///
 165     UINT32  Limit:4;
 166     UINT32  Reserved1:6;
 167     ///
 168     /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
 169     ///
 170     UINT32  IO_MWAIT:1;
 171     UINT32  Reserved2:4;
 172     ///
 173     /// [Bit 15] CFG Lock (R/WO).
 174     ///
 175     UINT32  CFGLock:1;
 176     UINT32  Reserved3:9;
 177     ///
 178     /// [Bit 25] C3 State Auto Demotion Enable (R/W).
 179     ///
 180     UINT32  C3AutoDemotion:1;
 181     ///
 182     /// [Bit 26] C1 State Auto Demotion Enable (R/W).
 183     ///
 184     UINT32  C1AutoDemotion:1;
 185     ///
 186     /// [Bit 27] Enable C3 Undemotion (R/W).
 187     ///
 188     UINT32  C3Undemotion:1;
 189     ///
 190     /// [Bit 28] Enable C1 Undemotion (R/W).
 191     ///
 192     UINT32  C1Undemotion:1;
 193     ///
 194     /// [Bit 29] Enable Package C-State Auto-demotion (R/W).
 195     ///
 196     UINT32  CStateAutoDemotion:1;
 197     ///
 198     /// [Bit 30] Enable Package C-State Undemotion (R/W).
 199     ///
 200     UINT32  CStateUndemotion:1;
 201     UINT32  Reserved4:1;
 202     UINT32  Reserved5:32;
 203   } Bits;
 204   ///
 205   /// All bit fields as a 32-bit value
 206   ///
 207   UINT32  Uint32;
 208   ///
 209   /// All bit fields as a 64-bit value
 210   ///
 211   UINT64  Uint64;
 212 } MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;
 213
 214
 215 /**
 216   Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
 217   RW if MSR_PLATFORM_INFO.[28] = 1.
 218
 219   @param  ECX  MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)
 220   @param  EAX  Lower 32-bits of MSR value.
 221                Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
 222   @param  EDX  Upper 32-bits of MSR value.
 223                Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
 224
 225   <b>Example usage</b>
 226   @code
 227   MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER  Msr;
 228
 229   Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);
 230   @endcode
 231   @note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 232 **/
 233 #define MSR_BROADWELL_TURBO_RATIO_LIMIT          0x000001AD
 234
 235 /**
 236   MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT
 237 **/
 238 typedef union {
 239   ///
 240   /// Individual bit fields
 241   ///
 242   struct {
 243     ///
 244     /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
 245     /// limit of 1 core active.
 246     ///
 247     UINT32  Maximum1C:8;
 248     ///
 249     /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
 250     /// limit of 2 core active.
 251     ///
 252     UINT32  Maximum2C:8;
 253     ///
 254     /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
 255     /// limit of 3 core active.
 256     ///
 257     UINT32  Maximum3C:8;
 258     ///
 259     /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
 260     /// limit of 4 core active.
 261     ///
 262     UINT32  Maximum4C:8;
 263     ///
 264     /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
 265     /// limit of 5core active.
 266     ///
 267     UINT32  Maximum5C:8;
 268     ///
 269     /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
 270     /// limit of 6core active.
 271     ///
 272     UINT32  Maximum6C:8;
 273     UINT32  Reserved:16;
 274   } Bits;
 275   ///
 276   /// All bit fields as a 64-bit value
 277   ///
 278   UINT64  Uint64;
 279 } MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;
 280
 281
 282 /**
 283   Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
 284   fields represent the widest possible range of uncore frequencies. Writing to
 285   these fields allows software to control the minimum and the maximum
 286   frequency that hardware will select.
 287
 288   @param  ECX  MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT (0x00000620)
 289   @param  EAX  Lower 32-bits of MSR value.
 290                Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
 291   @param  EDX  Upper 32-bits of MSR value.
 292                Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
 293
 294   <b>Example usage</b>
 295   @code
 296   MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER  Msr;
 297
 298   Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT);
 299   AsmWriteMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
 300   @endcode
 301 **/
 302 #define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT      0x00000620
 303
 304 /**
 305   MSR information returned for MSR index #MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT
 306 **/
 307 typedef union {
 308   ///
 309   /// Individual bit fields
 310   ///
 311   struct {
 312     ///
 313     /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
 314     /// LLC/Ring.
 315     ///
 316     UINT32  MAX_RATIO:7;
 317     UINT32  Reserved2:1;
 318     ///
 319     /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
 320     /// possible ratio of the LLC/Ring.
 321     ///
 322     UINT32  MIN_RATIO:7;
 323     UINT32  Reserved3:17;
 324     UINT32  Reserved4:32;
 325   } Bits;
 326   ///
 327   /// All bit fields as a 32-bit value
 328   ///
 329   UINT32  Uint32;
 330   ///
 331   /// All bit fields as a 64-bit value
 332   ///
 333   UINT64  Uint64;
 334 } MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER;
 335
 336 /**
 337   Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
 338   Domains.".
 339
 340   @param  ECX  MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)
 341   @param  EAX  Lower 32-bits of MSR value.
 342   @param  EDX  Upper 32-bits of MSR value.
 343
 344   <b>Example usage</b>
 345   @code
 346   UINT64  Msr;
 347
 348   Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS);
 349   @endcode
 350   @note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
 351 **/
 352 #define MSR_BROADWELL_PP0_ENERGY_STATUS          0x00000639
 353
 354 #endif