2 MSR Definitions for Intel processors based on the Broadwell microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
18 #ifndef __BROADWELL_MSR_H__
19 #define __BROADWELL_MSR_H__
21 #include <Register/ArchitecturalMsr.h>
24 Is Intel processors based on the Broadwell microarchitecture?
26 @param DisplayFamily Display Family ID
27 @param DisplayModel Display Model ID
29 @retval TRUE Yes, it is.
30 @retval FALSE No, it isn't.
32 #define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
35 DisplayModel == 0x3D || \
36 DisplayModel == 0x47 || \
37 DisplayModel == 0x4F || \
38 DisplayModel == 0x56 \
43 Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control
46 @param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)
47 @param EAX Lower 32-bits of MSR value.
48 Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.
49 @param EDX Upper 32-bits of MSR value.
50 Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.
54 MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
56 Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS);
57 AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);
59 @note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
61 #define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS 0x0000038E
64 MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS
68 /// Individual bit fields
89 /// [Bit 32] Ovf_FixedCtr0.
91 UINT32 Ovf_FixedCtr0
:1;
93 /// [Bit 33] Ovf_FixedCtr1.
95 UINT32 Ovf_FixedCtr1
:1;
97 /// [Bit 34] Ovf_FixedCtr2.
99 UINT32 Ovf_FixedCtr2
:1;
102 /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical
103 /// Addresses (ToPA).".
105 UINT32 Trace_ToPA_PMI
:1;
108 /// [Bit 61] Ovf_Uncore.
112 /// [Bit 62] Ovf_BufDSSAVE.
116 /// [Bit 63] CondChgd.
121 /// All bit fields as a 64-bit value
124 } MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER
;
128 Core. C-State Configuration Control (R/W) Note: C-state values are processor
129 specific C-state code names, unrelated to MWAIT extension C-state parameters
130 or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
132 @param ECX MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)
133 @param EAX Lower 32-bits of MSR value.
134 Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
135 @param EDX Upper 32-bits of MSR value.
136 Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
140 MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
142 Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);
143 AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
145 @note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
147 #define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL 0x000000E2
150 MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL
154 /// Individual bit fields
158 /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest
159 /// processor-specific C-state code name (consuming the least power) for
160 /// the package. The default is set as factory-configured package C-state
161 /// limit. The following C-state code name encodings are supported: 0000b:
162 /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6
163 /// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.
168 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
173 /// [Bit 15] CFG Lock (R/WO).
178 /// [Bit 25] C3 State Auto Demotion Enable (R/W).
180 UINT32 C3AutoDemotion
:1;
182 /// [Bit 26] C1 State Auto Demotion Enable (R/W).
184 UINT32 C1AutoDemotion
:1;
186 /// [Bit 27] Enable C3 Undemotion (R/W).
188 UINT32 C3Undemotion
:1;
190 /// [Bit 28] Enable C1 Undemotion (R/W).
192 UINT32 C1Undemotion
:1;
194 /// [Bit 29] Enable Package C-State Auto-demotion (R/W).
196 UINT32 CStateAutoDemotion
:1;
198 /// [Bit 30] Enable Package C-State Undemotion (R/W).
200 UINT32 CStateUndemotion
:1;
205 /// All bit fields as a 32-bit value
209 /// All bit fields as a 64-bit value
212 } MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER
;
216 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
217 RW if MSR_PLATFORM_INFO.[28] = 1.
219 @param ECX MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)
220 @param EAX Lower 32-bits of MSR value.
221 Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
222 @param EDX Upper 32-bits of MSR value.
223 Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
227 MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER Msr;
229 Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);
231 @note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
233 #define MSR_BROADWELL_TURBO_RATIO_LIMIT 0x000001AD
236 MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT
240 /// Individual bit fields
244 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
245 /// limit of 1 core active.
249 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
250 /// limit of 2 core active.
254 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
255 /// limit of 3 core active.
259 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
260 /// limit of 4 core active.
264 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
265 /// limit of 5core active.
269 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
270 /// limit of 6core active.
276 /// All bit fields as a 64-bit value
279 } MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER
;
283 Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
284 fields represent the widest possible range of uncore frequencies. Writing to
285 these fields allows software to control the minimum and the maximum
286 frequency that hardware will select.
288 @param ECX MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT (0x00000620)
289 @param EAX Lower 32-bits of MSR value.
290 Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
291 @param EDX Upper 32-bits of MSR value.
292 Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
296 MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
298 Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT);
299 AsmWriteMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
302 #define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT 0x00000620
305 MSR information returned for MSR index #MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT
309 /// Individual bit fields
313 /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
319 /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
320 /// possible ratio of the LLC/Ring.
327 /// All bit fields as a 32-bit value
331 /// All bit fields as a 64-bit value
334 } MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER
;
337 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
340 @param ECX MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)
341 @param EAX Lower 32-bits of MSR value.
342 @param EDX Upper 32-bits of MSR value.
348 Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS);
350 @note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
352 #define MSR_BROADWELL_PP0_ENERGY_STATUS 0x00000639