UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h

   1 /** @file
   2   MSR Definitions for Intel processors based on the Broadwell microarchitecture.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
  10   This program and the accompanying materials
  11   are licensed and made available under the terms and conditions of the BSD License
  12   which accompanies this distribution.  The full text of the license may be found at
  13   http://opensource.org/licenses/bsd-license.php
  14
  15   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17
  18   @par Specification Reference:
  19   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
  20   December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-12.
  21
  22 **/
  23
  24 #ifndef __BROADWELL_MSR_H__
  25 #define __BROADWELL_MSR_H__
  26
  27 #include <Register/ArchitecturalMsr.h>
  28
  29 /**
  30   Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control
  31   Facilities.".
  32
  33   @param  ECX  MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS (0x0000038E)
  34   @param  EAX  Lower 32-bits of MSR value.
  35                Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER.
  36   @param  EDX  Upper 32-bits of MSR value.
  37                Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER.
  38
  39   <b>Example usage</b>
  40   @code
  41   MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER  Msr;
  42
  43   Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS);
  44   AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);
  45   @endcode
  46   @note MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
  47 **/
  48 #define MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS     0x0000038E
  49
  50 /**
  51   MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS
  52 **/
  53 typedef union {
  54   ///
  55   /// Individual bit fields
  56   ///
  57   struct {
  58     ///
  59     /// [Bit 0] Ovf_PMC0.
  60     ///
  61     UINT32  Ovf_PMC0:1;
  62     ///
  63     /// [Bit 1] Ovf_PMC1.
  64     ///
  65     UINT32  Ovf_PMC1:1;
  66     ///
  67     /// [Bit 2] Ovf_PMC2.
  68     ///
  69     UINT32  Ovf_PMC2:1;
  70     ///
  71     /// [Bit 3] Ovf_PMC3.
  72     ///
  73     UINT32  Ovf_PMC3:1;
  74     UINT32  Reserved1:28;
  75     ///
  76     /// [Bit 32] Ovf_FixedCtr0.
  77     ///
  78     UINT32  Ovf_FixedCtr0:1;
  79     ///
  80     /// [Bit 33] Ovf_FixedCtr1.
  81     ///
  82     UINT32  Ovf_FixedCtr1:1;
  83     ///
  84     /// [Bit 34] Ovf_FixedCtr2.
  85     ///
  86     UINT32  Ovf_FixedCtr2:1;
  87     UINT32  Reserved2:20;
  88     ///
  89     /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.4.2, "Table of Physical
  90     /// Addresses (ToPA).".
  91     ///
  92     UINT32  Trace_ToPA_PMI:1;
  93     UINT32  Reserved3:5;
  94     ///
  95     /// [Bit 61] Ovf_Uncore.
  96     ///
  97     UINT32  Ovf_Uncore:1;
  98     ///
  99     /// [Bit 62] Ovf_BufDSSAVE.
 100     ///
 101     UINT32  OvfBuf:1;
 102     ///
 103     /// [Bit 63] CondChgd.
 104     ///
 105     UINT32  CondChgd:1;
 106   } Bits;
 107   ///
 108   /// All bit fields as a 64-bit value
 109   ///
 110   UINT64  Uint64;
 111 } MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER;
 112
 113
 114 /**
 115   Core. C-State Configuration Control (R/W) Note: C-state values are processor
 116   specific C-state code names, unrelated to MWAIT extension C-state parameters
 117   or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
 118
 119   @param  ECX  MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)
 120   @param  EAX  Lower 32-bits of MSR value.
 121                Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
 122   @param  EDX  Upper 32-bits of MSR value.
 123                Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
 124
 125   <b>Example usage</b>
 126   @code
 127   MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
 128
 129   Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);
 130   AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
 131   @endcode
 132   @note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
 133 **/
 134 #define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL     0x000000E2
 135
 136 /**
 137   MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL
 138 **/
 139 typedef union {
 140   ///
 141   /// Individual bit fields
 142   ///
 143   struct {
 144     ///
 145     /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest
 146     /// processor-specific C-state code name (consuming the least power) for
 147     /// the package. The default is set as factory-configured package C-state
 148     /// limit. The following C-state code name encodings are supported: 0000b:
 149     /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6
 150     /// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.
 151     ///
 152     UINT32  Limit:4;
 153     UINT32  Reserved1:6;
 154     ///
 155     /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
 156     ///
 157     UINT32  IO_MWAIT:1;
 158     UINT32  Reserved2:4;
 159     ///
 160     /// [Bit 15] CFG Lock (R/WO).
 161     ///
 162     UINT32  CFGLock:1;
 163     UINT32  Reserved3:9;
 164     ///
 165     /// [Bit 25] C3 State Auto Demotion Enable (R/W).
 166     ///
 167     UINT32  C3AutoDemotion:1;
 168     ///
 169     /// [Bit 26] C1 State Auto Demotion Enable (R/W).
 170     ///
 171     UINT32  C1AutoDemotion:1;
 172     ///
 173     /// [Bit 27] Enable C3 Undemotion (R/W).
 174     ///
 175     UINT32  C3Undemotion:1;
 176     ///
 177     /// [Bit 28] Enable C1 Undemotion (R/W).
 178     ///
 179     UINT32  C1Undemotion:1;
 180     ///
 181     /// [Bit 29] Enable Package C-State Auto-demotion (R/W).
 182     ///
 183     UINT32  CStateAutoDemotion:1;
 184     ///
 185     /// [Bit 30] Enable Package C-State Undemotion (R/W).
 186     ///
 187     UINT32  CStateUndemotion:1;
 188     UINT32  Reserved4:1;
 189     UINT32  Reserved5:32;
 190   } Bits;
 191   ///
 192   /// All bit fields as a 32-bit value
 193   ///
 194   UINT32  Uint32;
 195   ///
 196   /// All bit fields as a 64-bit value
 197   ///
 198   UINT64  Uint64;
 199 } MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;
 200
 201
 202 /**
 203   Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
 204   RW if MSR_PLATFORM_INFO.[28] = 1.
 205
 206   @param  ECX  MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)
 207   @param  EAX  Lower 32-bits of MSR value.
 208                Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
 209   @param  EDX  Upper 32-bits of MSR value.
 210                Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
 211
 212   <b>Example usage</b>
 213   @code
 214   MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER  Msr;
 215
 216   Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);
 217   @endcode
 218   @note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 219 **/
 220 #define MSR_BROADWELL_TURBO_RATIO_LIMIT          0x000001AD
 221
 222 /**
 223   MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT
 224 **/
 225 typedef union {
 226   ///
 227   /// Individual bit fields
 228   ///
 229   struct {
 230     ///
 231     /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
 232     /// limit of 1 core active.
 233     ///
 234     UINT32  Maximum1C:8;
 235     ///
 236     /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
 237     /// limit of 2 core active.
 238     ///
 239     UINT32  Maximum2C:8;
 240     ///
 241     /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
 242     /// limit of 3 core active.
 243     ///
 244     UINT32  Maximum3C:8;
 245     ///
 246     /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
 247     /// limit of 4 core active.
 248     ///
 249     UINT32  Maximum4C:8;
 250     ///
 251     /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
 252     /// limit of 5core active.
 253     ///
 254     UINT32  Maximum5C:8;
 255     ///
 256     /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
 257     /// limit of 6core active.
 258     ///
 259     UINT32  Maximum6C:8;
 260     UINT32  Reserved:16;
 261   } Bits;
 262   ///
 263   /// All bit fields as a 64-bit value
 264   ///
 265   UINT64  Uint64;
 266 } MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;
 267
 268 #endif