2 MSR Definitions for the Intel(R) Core(TM) 2 Processor Family.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-2.
24 #ifndef __CORE2_MSR_H__
25 #define __CORE2_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Shared. Model Specific Platform ID (R).
32 @param ECX MSR_CORE2_PLATFORM_ID (0x00000017)
33 @param EAX Lower 32-bits of MSR value.
34 Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.
35 @param EDX Upper 32-bits of MSR value.
36 Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.
40 MSR_CORE2_PLATFORM_ID_REGISTER Msr;
42 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PLATFORM_ID);
45 #define MSR_CORE2_PLATFORM_ID 0x00000017
48 MSR information returned for MSR index #MSR_CORE2_PLATFORM_ID
52 /// Individual bit fields
57 /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.
59 UINT32 MaximumQualifiedRatio
:5;
63 /// [Bits 52:50] See Table 35-2.
69 /// All bit fields as a 64-bit value
72 } MSR_CORE2_PLATFORM_ID_REGISTER
;
76 Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
77 processor features; (R) indicates current processor configuration.
79 @param ECX MSR_CORE2_EBL_CR_POWERON (0x0000002A)
80 @param EAX Lower 32-bits of MSR value.
81 Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.
82 @param EDX Upper 32-bits of MSR value.
83 Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.
87 MSR_CORE2_EBL_CR_POWERON_REGISTER Msr;
89 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_EBL_CR_POWERON);
90 AsmWriteMsr64 (MSR_CORE2_EBL_CR_POWERON, Msr.Uint64);
93 #define MSR_CORE2_EBL_CR_POWERON 0x0000002A
96 MSR information returned for MSR index #MSR_CORE2_EBL_CR_POWERON
100 /// Individual bit fields
105 /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
106 /// Note: Not all processor implements R/W.
108 UINT32 DataErrorCheckingEnable
:1;
110 /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
111 /// Note: Not all processor implements R/W.
113 UINT32 ResponseErrorCheckingEnable
:1;
115 /// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
116 /// all processor implements R/W.
118 UINT32 MCERR_DriveEnable
:1;
120 /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:
121 /// Not all processor implements R/W.
123 UINT32 AddressParityEnable
:1;
127 /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
128 /// all processor implements R/W.
130 UINT32 BINIT_DriverEnable
:1;
132 /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
134 UINT32 OutputTriStateEnable
:1;
136 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
138 UINT32 ExecuteBIST
:1;
140 /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
142 UINT32 MCERR_ObservationEnabled
:1;
144 /// [Bit 11] Intel TXT Capable Chipset. (R/O) 1 = Present; 0 = Not Present.
146 UINT32 IntelTXTCapableChipset
:1;
148 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
150 UINT32 BINIT_ObservationEnabled
:1;
153 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
155 UINT32 ResetVector
:1;
158 /// [Bits 17:16] APIC Cluster ID (R/O).
160 UINT32 APICClusterID
:2;
162 /// [Bit 18] N/2 Non-Integer Bus Ratio (R/O) 0 = Integer ratio; 1 =
163 /// Non-integer ratio.
165 UINT32 NonIntegerBusRatio
:1;
168 /// [Bits 21:20] Symmetric Arbitration ID (R/O).
170 UINT32 SymmetricArbitrationID
:2;
172 /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
174 UINT32 IntegerBusFrequencyRatio
:5;
179 /// All bit fields as a 32-bit value
183 /// All bit fields as a 64-bit value
186 } MSR_CORE2_EBL_CR_POWERON_REGISTER
;
190 Unique. Control Features in Intel 64Processor (R/W) See Table 35-2.
192 @param ECX MSR_CORE2_FEATURE_CONTROL (0x0000003A)
193 @param EAX Lower 32-bits of MSR value.
194 Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.
195 @param EDX Upper 32-bits of MSR value.
196 Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.
200 MSR_CORE2_FEATURE_CONTROL_REGISTER Msr;
202 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FEATURE_CONTROL);
203 AsmWriteMsr64 (MSR_CORE2_FEATURE_CONTROL, Msr.Uint64);
206 #define MSR_CORE2_FEATURE_CONTROL 0x0000003A
209 MSR information returned for MSR index #MSR_CORE2_FEATURE_CONTROL
213 /// Individual bit fields
218 /// [Bit 3] Unique. SMRR Enable (R/WL) When this bit is set and the lock
219 /// bit is set makes the SMRR_PHYS_BASE and SMRR_PHYS_MASK registers read
220 /// visible and writeable while in SMM.
227 /// All bit fields as a 32-bit value
231 /// All bit fields as a 64-bit value
234 } MSR_CORE2_FEATURE_CONTROL_REGISTER
;
238 Unique. Last Branch Record n From IP (R/W) One of four pairs of last branch
239 record registers on the last branch record stack. This part of the stack
240 contains pointers to the source instruction for one of the last four
241 branches, exceptions, or interrupts taken by the processor. See also: -
242 Last Branch Record Stack TOS at 1C9H - Section 17.12, "Last Branch,
243 Interrupt, and Exception Recording (Pentium M Processors).".
245 @param ECX MSR_CORE2_LASTBRANCH_n_FROM_IP
246 @param EAX Lower 32-bits of MSR value.
247 @param EDX Upper 32-bits of MSR value.
253 Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP);
254 AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP, Msr);
258 #define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x00000040
259 #define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x00000041
260 #define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x00000042
261 #define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x00000043
266 Unique. Last Branch Record n To IP (R/W) One of four pairs of last branch
267 record registers on the last branch record stack. This part of the stack
268 contains pointers to the destination instruction for one of the last four
269 branches, exceptions, or interrupts taken by the processor.
271 @param ECX MSR_CORE2_LASTBRANCH_n_TO_IP
272 @param EAX Lower 32-bits of MSR value.
273 @param EDX Upper 32-bits of MSR value.
279 Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP);
280 AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP, Msr);
284 #define MSR_CORE2_LASTBRANCH_0_TO_IP 0x00000060
285 #define MSR_CORE2_LASTBRANCH_1_TO_IP 0x00000061
286 #define MSR_CORE2_LASTBRANCH_2_TO_IP 0x00000062
287 #define MSR_CORE2_LASTBRANCH_3_TO_IP 0x00000063
292 Unique. System Management Mode Base Address register (WO in SMM)
293 Model-specific implementation of SMRR-like interface, read visible and write
296 @param ECX MSR_CORE2_SMRR_PHYSBASE (0x000000A0)
297 @param EAX Lower 32-bits of MSR value.
298 Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.
299 @param EDX Upper 32-bits of MSR value.
300 Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.
304 MSR_CORE2_SMRR_PHYSBASE_REGISTER Msr;
307 AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSBASE, Msr.Uint64);
310 #define MSR_CORE2_SMRR_PHYSBASE 0x000000A0
313 MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSBASE
317 /// Individual bit fields
322 /// [Bits 31:12] PhysBase. SMRR physical Base Address.
328 /// All bit fields as a 32-bit value
332 /// All bit fields as a 64-bit value
335 } MSR_CORE2_SMRR_PHYSBASE_REGISTER
;
339 Unique. System Management Mode Physical Address Mask register (WO in SMM)
340 Model-specific implementation of SMRR-like interface, read visible and write
343 @param ECX MSR_CORE2_SMRR_PHYSMASK (0x000000A1)
344 @param EAX Lower 32-bits of MSR value.
345 Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.
346 @param EDX Upper 32-bits of MSR value.
347 Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.
351 MSR_CORE2_SMRR_PHYSMASK_REGISTER Msr;
354 AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSMASK, Msr.Uint64);
357 #define MSR_CORE2_SMRR_PHYSMASK 0x000000A1
360 MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSMASK
364 /// Individual bit fields
369 /// [Bit 11] Valid. Physical address base and range mask are valid.
373 /// [Bits 31:12] PhysMask. SMRR physical address range mask.
379 /// All bit fields as a 32-bit value
383 /// All bit fields as a 64-bit value
386 } MSR_CORE2_SMRR_PHYSMASK_REGISTER
;
390 Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
391 bus clock speed for processors based on Intel Core microarchitecture:.
393 @param ECX MSR_CORE2_FSB_FREQ (0x000000CD)
394 @param EAX Lower 32-bits of MSR value.
395 Described by the type MSR_CORE2_FSB_FREQ_REGISTER.
396 @param EDX Upper 32-bits of MSR value.
397 Described by the type MSR_CORE2_FSB_FREQ_REGISTER.
401 MSR_CORE2_FSB_FREQ_REGISTER Msr;
403 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FSB_FREQ);
406 #define MSR_CORE2_FSB_FREQ 0x000000CD
409 MSR information returned for MSR index #MSR_CORE2_FSB_FREQ
413 /// Individual bit fields
417 /// [Bits 2:0] - Scalable Bus Speed
418 /// 101B: 100 MHz (FSB 400)
419 /// 001B: 133 MHz (FSB 533)
420 /// 011B: 167 MHz (FSB 667)
421 /// 010B: 200 MHz (FSB 800)
422 /// 000B: 267 MHz (FSB 1067)
423 /// 100B: 333 MHz (FSB 1333)
425 /// 133.33 MHz should be utilized if performing calculation with System
426 /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if
427 /// performing calculation with System Bus Speed when encoding is 011B.
428 /// 266.67 MHz should be utilized if performing calculation with System
429 /// Bus Speed when encoding is 000B. 333.33 MHz should be utilized if
430 /// performing calculation with System Bus Speed when encoding is 100B.
432 UINT32 ScalableBusSpeed
:3;
437 /// All bit fields as a 32-bit value
441 /// All bit fields as a 64-bit value
444 } MSR_CORE2_FSB_FREQ_REGISTER
;
450 @param ECX MSR_CORE2_BBL_CR_CTL3 (0x0000011E)
451 @param EAX Lower 32-bits of MSR value.
452 Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER.
453 @param EDX Upper 32-bits of MSR value.
454 Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER.
458 MSR_CORE2_BBL_CR_CTL3_REGISTER Msr;
460 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_BBL_CR_CTL3);
461 AsmWriteMsr64 (MSR_CORE2_BBL_CR_CTL3, Msr.Uint64);
464 #define MSR_CORE2_BBL_CR_CTL3 0x0000011E
467 MSR information returned for MSR index #MSR_CORE2_BBL_CR_CTL3
471 /// Individual bit fields
475 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
476 /// Indicates if the L2 is hardware-disabled.
478 UINT32 L2HardwareEnabled
:1;
481 /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
482 /// Disabled (default) Until this bit is set the processor will not
483 /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
488 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
490 UINT32 L2NotPresent
:1;
495 /// All bit fields as a 32-bit value
499 /// All bit fields as a 64-bit value
502 } MSR_CORE2_BBL_CR_CTL3_REGISTER
;
508 @param ECX MSR_CORE2_PERF_STATUS (0x00000198)
509 @param EAX Lower 32-bits of MSR value.
510 Described by the type MSR_CORE2_PERF_STATUS_REGISTER.
511 @param EDX Upper 32-bits of MSR value.
512 Described by the type MSR_CORE2_PERF_STATUS_REGISTER.
516 MSR_CORE2_PERF_STATUS_REGISTER Msr;
518 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_STATUS);
519 AsmWriteMsr64 (MSR_CORE2_PERF_STATUS, Msr.Uint64);
522 #define MSR_CORE2_PERF_STATUS 0x00000198
525 MSR information returned for MSR index #MSR_CORE2_PERF_STATUS
529 /// Individual bit fields
533 /// [Bits 15:0] Current Performance State Value.
535 UINT32 CurrentPerformanceStateValue
:16;
538 /// [Bit 31] XE Operation (R/O). If set, XE operation is enabled. Default
541 UINT32 XEOperation
:1;
544 /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio
545 /// configured for the processor.
547 UINT32 MaximumBusRatio
:5;
550 /// [Bit 46] Non-Integer Bus Ratio (R/O) Indicates non-integer bus ratio
551 /// is enabled. Applies processors based on Enhanced Intel Core
552 /// microarchitecture.
554 UINT32 NonIntegerBusRatio
:1;
558 /// All bit fields as a 64-bit value
561 } MSR_CORE2_PERF_STATUS_REGISTER
;
567 @param ECX MSR_CORE2_THERM2_CTL (0x0000019D)
568 @param EAX Lower 32-bits of MSR value.
569 Described by the type MSR_CORE2_THERM2_CTL_REGISTER.
570 @param EDX Upper 32-bits of MSR value.
571 Described by the type MSR_CORE2_THERM2_CTL_REGISTER.
575 MSR_CORE2_THERM2_CTL_REGISTER Msr;
577 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_THERM2_CTL);
578 AsmWriteMsr64 (MSR_CORE2_THERM2_CTL, Msr.Uint64);
581 #define MSR_CORE2_THERM2_CTL 0x0000019D
584 MSR information returned for MSR index #MSR_CORE2_THERM2_CTL
588 /// Individual bit fields
593 /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
594 /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
595 /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
596 /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
597 /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.
604 /// All bit fields as a 32-bit value
608 /// All bit fields as a 64-bit value
611 } MSR_CORE2_THERM2_CTL_REGISTER
;
615 Enable Misc. Processor Features (R/W) Allows a variety of processor
616 functions to be enabled and disabled.
618 @param ECX MSR_CORE2_IA32_MISC_ENABLE (0x000001A0)
619 @param EAX Lower 32-bits of MSR value.
620 Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.
621 @param EDX Upper 32-bits of MSR value.
622 Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.
626 MSR_CORE2_IA32_MISC_ENABLE_REGISTER Msr;
628 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_IA32_MISC_ENABLE);
629 AsmWriteMsr64 (MSR_CORE2_IA32_MISC_ENABLE, Msr.Uint64);
632 #define MSR_CORE2_IA32_MISC_ENABLE 0x000001A0
635 MSR information returned for MSR index #MSR_CORE2_IA32_MISC_ENABLE
639 /// Individual bit fields
643 /// [Bit 0] Fast-Strings Enable See Table 35-2.
645 UINT32 FastStrings
:1;
648 /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
651 UINT32 AutomaticThermalControlCircuit
:1;
654 /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.
656 UINT32 PerformanceMonitoring
:1;
659 /// [Bit 9] Hardware Prefetcher Disable (R/W) When set, disables the
660 /// hardware prefetcher operation on streams of data. When clear
661 /// (default), enables the prefetch queue. Disabling of the hardware
662 /// prefetcher may impact processor performance.
664 UINT32 HardwarePrefetcherDisable
:1;
666 /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
667 /// the processor to indicate a pending break event within the processor 0
668 /// = Indicates compatible FERR# signaling behavior This bit must be set
669 /// to 1 to support XAPIC interrupt model usage.
673 /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.
677 /// [Bit 12] Shared. Precise Event Based Sampling Unavailable (RO) See
682 /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
683 /// thermal sensor indicates that the die temperature is at the
684 /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
685 /// TM2 will reduce the bus to core ratio and voltage according to the
686 /// value last written to MSR_THERM2_CTL bits 15:0.
687 /// When this bit is clear (0, default), the processor does not change
688 /// the VID signals or the bus to core ratio when the processor enters a
689 /// thermally managed state. The BIOS must enable this feature if the
690 /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is
691 /// not set, this feature is not supported and BIOS must not alter the
692 /// contents of the TM2 bit location. The processor is operating out of
693 /// specification if both this bit and the TM1 bit are set to 0.
698 /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
704 /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.
708 /// [Bit 19] Shared. Adjacent Cache Line Prefetch Disable (R/W) When set
709 /// to 1, the processor fetches the cache line that contains data
710 /// currently required by the processor. When set to 0, the processor
711 /// fetches cache lines that comprise a cache line pair (128 bytes).
712 /// Single processor platforms should not set this bit. Server platforms
713 /// should set or clear this bit based on platform performance observed in
714 /// validation and testing. BIOS may contain a setup option that controls
715 /// the setting of this bit.
717 UINT32 AdjacentCacheLinePrefetchDisable
:1;
719 /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock
720 /// (R/WO) When set, this bit causes the following bits to become
721 /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this
722 /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must
723 /// be set before an Enhanced Intel SpeedStep Technology transition is
724 /// requested. This bit is cleared on reset.
729 /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 35-2.
731 UINT32 LimitCpuidMaxval
:1;
733 /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.
735 UINT32 xTPR_Message_Disable
:1;
739 /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.
744 /// [Bit 37] Unique. DCU Prefetcher Disable (R/W) When set to 1, The DCU
745 /// L1 data cache prefetcher is disabled. The default value after reset is
746 /// 0. BIOS may write '1' to disable this feature. The DCU prefetcher is
747 /// an L1 data cache prefetcher. When the DCU prefetcher detects multiple
748 /// loads from the same line done within a time limit, the DCU prefetcher
749 /// assumes the next line will be required. The next line is prefetched in
750 /// to the L1 data cache from memory or L2.
752 UINT32 DCUPrefetcherDisable
:1;
754 /// [Bit 38] Shared. IDA Disable (R/W) When set to 1 on processors that
755 /// support IDA, the Intel Dynamic Acceleration feature (IDA) is disabled
756 /// and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0).
757 /// When set to a 0 on processors that support IDA, CPUID.06H: EAX[1]
758 /// reports the processor's support of IDA is enabled. Note: the power-on
759 /// default value is used by BIOS to detect hardware support of IDA. If
760 /// power-on default value is 1, IDA is available in the processor. If
761 /// power-on default value is 0, IDA is not available.
765 /// [Bit 39] Unique. IP Prefetcher Disable (R/W) When set to 1, The IP
766 /// prefetcher is disabled. The default value after reset is 0. BIOS may
767 /// write '1' to disable this feature. The IP prefetcher is an L1 data
768 /// cache prefetcher. The IP prefetcher looks for sequential load history
769 /// to determine whether to prefetch the next expected data into the L1
770 /// cache from memory or L2.
772 UINT32 IPPrefetcherDisable
:1;
773 UINT32 Reserved10
:24;
776 /// All bit fields as a 64-bit value
779 } MSR_CORE2_IA32_MISC_ENABLE_REGISTER
;
783 Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
784 that points to the MSR containing the most recent branch record. See
785 MSR_LASTBRANCH_0_FROM_IP (at 40H).
787 @param ECX MSR_CORE2_LASTBRANCH_TOS (0x000001C9)
788 @param EAX Lower 32-bits of MSR value.
789 @param EDX Upper 32-bits of MSR value.
795 Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_TOS);
796 AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_TOS, Msr);
799 #define MSR_CORE2_LASTBRANCH_TOS 0x000001C9
803 Unique. Last Exception Record From Linear IP (R) Contains a pointer to the
804 last branch instruction that the processor executed prior to the last
805 exception that was generated or the last interrupt that was handled.
807 @param ECX MSR_CORE2_LER_FROM_LIP (0x000001DD)
808 @param EAX Lower 32-bits of MSR value.
809 @param EDX Upper 32-bits of MSR value.
815 Msr = AsmReadMsr64 (MSR_CORE2_LER_FROM_LIP);
818 #define MSR_CORE2_LER_FROM_LIP 0x000001DD
822 Unique. Last Exception Record To Linear IP (R) This area contains a pointer
823 to the target of the last branch instruction that the processor executed
824 prior to the last exception that was generated or the last interrupt that
827 @param ECX MSR_CORE2_LER_TO_LIP (0x000001DE)
828 @param EAX Lower 32-bits of MSR value.
829 @param EDX Upper 32-bits of MSR value.
835 Msr = AsmReadMsr64 (MSR_CORE2_LER_TO_LIP);
838 #define MSR_CORE2_LER_TO_LIP 0x000001DE
842 Unique. Fixed-Function Performance Counter Register n (R/W).
844 @param ECX MSR_CORE2_PERF_FIXED_CTRn
845 @param EAX Lower 32-bits of MSR value.
846 @param EDX Upper 32-bits of MSR value.
852 Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR0);
853 AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR0, Msr);
857 #define MSR_CORE2_PERF_FIXED_CTR0 0x00000309
858 #define MSR_CORE2_PERF_FIXED_CTR1 0x0000030A
859 #define MSR_CORE2_PERF_FIXED_CTR2 0x0000030B
864 Unique. RO. This applies to processors that do not support architectural
867 @param ECX MSR_CORE2_PERF_CAPABILITIES (0x00000345)
868 @param EAX Lower 32-bits of MSR value.
869 Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.
870 @param EDX Upper 32-bits of MSR value.
871 Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.
875 MSR_CORE2_PERF_CAPABILITIES_REGISTER Msr;
877 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_CAPABILITIES);
878 AsmWriteMsr64 (MSR_CORE2_PERF_CAPABILITIES, Msr.Uint64);
881 #define MSR_CORE2_PERF_CAPABILITIES 0x00000345
884 MSR information returned for MSR index #MSR_CORE2_PERF_CAPABILITIES
888 /// Individual bit fields
892 /// [Bits 5:0] LBR Format. See Table 35-2.
896 /// [Bit 6] PEBS Record Format.
900 /// [Bit 7] PEBSSaveArchRegs. See Table 35-2.
902 UINT32 PEBS_ARCH_REG
:1;
907 /// All bit fields as a 32-bit value
911 /// All bit fields as a 64-bit value
914 } MSR_CORE2_PERF_CAPABILITIES_REGISTER
;
918 Unique. Fixed-Function-Counter Control Register (R/W).
920 @param ECX MSR_CORE2_PERF_FIXED_CTR_CTRL (0x0000038D)
921 @param EAX Lower 32-bits of MSR value.
922 @param EDX Upper 32-bits of MSR value.
928 Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL);
929 AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL, Msr);
932 #define MSR_CORE2_PERF_FIXED_CTR_CTRL 0x0000038D
936 Unique. See Table 35-2. See Section 18.4.2, "Global Counter Control
939 @param ECX MSR_CORE2_IA32_PERF_GLOBAL_STAUS (0x0000038E)
940 @param EAX Lower 32-bits of MSR value.
941 @param EDX Upper 32-bits of MSR value.
947 Msr = AsmReadMsr64 (MSR_CORE2_IA32_PERF_GLOBAL_STAUS);
948 AsmWriteMsr64 (MSR_CORE2_IA32_PERF_GLOBAL_STAUS, Msr);
951 #define MSR_CORE2_IA32_PERF_GLOBAL_STAUS 0x0000038E
955 Unique. See Section 18.4.2, "Global Counter Control Facilities.".
957 @param ECX MSR_CORE2_PERF_GLOBAL_STAUS (0x0000038E)
958 @param EAX Lower 32-bits of MSR value.
959 @param EDX Upper 32-bits of MSR value.
965 Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STAUS);
966 AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STAUS, Msr);
969 #define MSR_CORE2_PERF_GLOBAL_STAUS 0x0000038E
973 Unique. See Section 18.4.2, "Global Counter Control Facilities.".
975 @param ECX MSR_CORE2_PERF_GLOBAL_CTRL (0x0000038F)
976 @param EAX Lower 32-bits of MSR value.
977 @param EDX Upper 32-bits of MSR value.
983 Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL);
984 AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL, Msr);
987 #define MSR_CORE2_PERF_GLOBAL_CTRL 0x0000038F
991 Unique. See Section 18.4.2, "Global Counter Control Facilities.".
993 @param ECX MSR_CORE2_PERF_GLOBAL_OVF_CTRL (0x00000390)
994 @param EAX Lower 32-bits of MSR value.
995 @param EDX Upper 32-bits of MSR value.
1001 Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL);
1002 AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL, Msr);
1005 #define MSR_CORE2_PERF_GLOBAL_OVF_CTRL 0x00000390
1009 Unique. See Table 35-2. See Section 18.4.4, "Precise Event Based Sampling
1012 @param ECX MSR_CORE2_PEBS_ENABLE (0x000003F1)
1013 @param EAX Lower 32-bits of MSR value.
1014 Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.
1015 @param EDX Upper 32-bits of MSR value.
1016 Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.
1018 <b>Example usage</b>
1020 MSR_CORE2_PEBS_ENABLE_REGISTER Msr;
1022 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PEBS_ENABLE);
1023 AsmWriteMsr64 (MSR_CORE2_PEBS_ENABLE, Msr.Uint64);
1026 #define MSR_CORE2_PEBS_ENABLE 0x000003F1
1029 MSR information returned for MSR index #MSR_CORE2_PEBS_ENABLE
1033 /// Individual bit fields
1037 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
1040 UINT32 Reserved1
:31;
1041 UINT32 Reserved2
:32;
1044 /// All bit fields as a 32-bit value
1048 /// All bit fields as a 64-bit value
1051 } MSR_CORE2_PEBS_ENABLE_REGISTER
;
1055 Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
1057 @param ECX MSR_CORE2_MC4_CTL (0x0000040C)
1058 @param EAX Lower 32-bits of MSR value.
1059 @param EDX Upper 32-bits of MSR value.
1061 <b>Example usage</b>
1065 Msr = AsmReadMsr64 (MSR_CORE2_MC4_CTL);
1066 AsmWriteMsr64 (MSR_CORE2_MC4_CTL, Msr);
1069 #define MSR_CORE2_MC4_CTL 0x0000040C
1073 Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
1075 @param ECX MSR_CORE2_MC4_STATUS (0x0000040D)
1076 @param EAX Lower 32-bits of MSR value.
1077 @param EDX Upper 32-bits of MSR value.
1079 <b>Example usage</b>
1083 Msr = AsmReadMsr64 (MSR_CORE2_MC4_STATUS);
1084 AsmWriteMsr64 (MSR_CORE2_MC4_STATUS, Msr);
1087 #define MSR_CORE2_MC4_STATUS 0x0000040D
1091 Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR
1092 register is either not implemented or contains no address if the ADDRV flag
1093 in the MSR_MC4_STATUS register is clear. When not implemented in the
1094 processor, all reads and writes to this MSR will cause a general-protection
1097 @param ECX MSR_CORE2_MC4_ADDR (0x0000040E)
1098 @param EAX Lower 32-bits of MSR value.
1099 @param EDX Upper 32-bits of MSR value.
1101 <b>Example usage</b>
1105 Msr = AsmReadMsr64 (MSR_CORE2_MC4_ADDR);
1106 AsmWriteMsr64 (MSR_CORE2_MC4_ADDR, Msr);
1109 #define MSR_CORE2_MC4_ADDR 0x0000040E
1113 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
1115 @param ECX MSR_CORE2_MC3_CTL (0x00000410)
1116 @param EAX Lower 32-bits of MSR value.
1117 @param EDX Upper 32-bits of MSR value.
1119 <b>Example usage</b>
1123 Msr = AsmReadMsr64 (MSR_CORE2_MC3_CTL);
1124 AsmWriteMsr64 (MSR_CORE2_MC3_CTL, Msr);
1127 #define MSR_CORE2_MC3_CTL 0x00000410
1131 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
1133 @param ECX MSR_CORE2_MC3_STATUS (0x00000411)
1134 @param EAX Lower 32-bits of MSR value.
1135 @param EDX Upper 32-bits of MSR value.
1137 <b>Example usage</b>
1141 Msr = AsmReadMsr64 (MSR_CORE2_MC3_STATUS);
1142 AsmWriteMsr64 (MSR_CORE2_MC3_STATUS, Msr);
1145 #define MSR_CORE2_MC3_STATUS 0x00000411
1149 Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR
1150 register is either not implemented or contains no address if the ADDRV flag
1151 in the MSR_MC3_STATUS register is clear. When not implemented in the
1152 processor, all reads and writes to this MSR will cause a general-protection
1155 @param ECX MSR_CORE2_MC3_ADDR (0x00000412)
1156 @param EAX Lower 32-bits of MSR value.
1157 @param EDX Upper 32-bits of MSR value.
1159 <b>Example usage</b>
1163 Msr = AsmReadMsr64 (MSR_CORE2_MC3_ADDR);
1164 AsmWriteMsr64 (MSR_CORE2_MC3_ADDR, Msr);
1167 #define MSR_CORE2_MC3_ADDR 0x00000412
1173 @param ECX MSR_CORE2_MC3_MISC (0x00000413)
1174 @param EAX Lower 32-bits of MSR value.
1175 @param EDX Upper 32-bits of MSR value.
1177 <b>Example usage</b>
1181 Msr = AsmReadMsr64 (MSR_CORE2_MC3_MISC);
1182 AsmWriteMsr64 (MSR_CORE2_MC3_MISC, Msr);
1185 #define MSR_CORE2_MC3_MISC 0x00000413
1191 @param ECX MSR_CORE2_MC5_CTL (0x00000414)
1192 @param EAX Lower 32-bits of MSR value.
1193 @param EDX Upper 32-bits of MSR value.
1195 <b>Example usage</b>
1199 Msr = AsmReadMsr64 (MSR_CORE2_MC5_CTL);
1200 AsmWriteMsr64 (MSR_CORE2_MC5_CTL, Msr);
1203 #define MSR_CORE2_MC5_CTL 0x00000414
1209 @param ECX MSR_CORE2_MC5_STATUS (0x00000415)
1210 @param EAX Lower 32-bits of MSR value.
1211 @param EDX Upper 32-bits of MSR value.
1213 <b>Example usage</b>
1217 Msr = AsmReadMsr64 (MSR_CORE2_MC5_STATUS);
1218 AsmWriteMsr64 (MSR_CORE2_MC5_STATUS, Msr);
1221 #define MSR_CORE2_MC5_STATUS 0x00000415
1227 @param ECX MSR_CORE2_MC5_ADDR (0x00000416)
1228 @param EAX Lower 32-bits of MSR value.
1229 @param EDX Upper 32-bits of MSR value.
1231 <b>Example usage</b>
1235 Msr = AsmReadMsr64 (MSR_CORE2_MC5_ADDR);
1236 AsmWriteMsr64 (MSR_CORE2_MC5_ADDR, Msr);
1239 #define MSR_CORE2_MC5_ADDR 0x00000416
1245 @param ECX MSR_CORE2_MC5_MISC (0x00000417)
1246 @param EAX Lower 32-bits of MSR value.
1247 @param EDX Upper 32-bits of MSR value.
1249 <b>Example usage</b>
1253 Msr = AsmReadMsr64 (MSR_CORE2_MC5_MISC);
1254 AsmWriteMsr64 (MSR_CORE2_MC5_MISC, Msr);
1257 #define MSR_CORE2_MC5_MISC 0x00000417
1261 Unique. Apply to Intel Xeon processor 7400 series (processor signature
1262 06_1D) only. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS." and Chapter 23.
1264 @param ECX MSR_CORE2_MC6_STATUS (0x00000419)
1265 @param EAX Lower 32-bits of MSR value.
1266 @param EDX Upper 32-bits of MSR value.
1268 <b>Example usage</b>
1272 Msr = AsmReadMsr64 (MSR_CORE2_MC6_STATUS);
1273 AsmWriteMsr64 (MSR_CORE2_MC6_STATUS, Msr);
1276 #define MSR_CORE2_MC6_STATUS 0x00000419
1280 Unique. GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon
1281 processor 7400 series (processor signature 06_1D) only. See Section 17.2.2.
1283 @param ECX MSR_CORE2_EMON_L3_CTR_CTLn
1284 @param EAX Lower 32-bits of MSR value.
1285 @param EDX Upper 32-bits of MSR value.
1287 <b>Example usage</b>
1291 Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0);
1292 AsmWriteMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0, Msr);
1296 #define MSR_CORE2_EMON_L3_CTR_CTL0 0x000107CC
1297 #define MSR_CORE2_EMON_L3_CTR_CTL1 0x000107CD
1298 #define MSR_CORE2_EMON_L3_CTR_CTL2 0x000107CE
1299 #define MSR_CORE2_EMON_L3_CTR_CTL3 0x000107CF
1300 #define MSR_CORE2_EMON_L3_CTR_CTL4 0x000107D0
1301 #define MSR_CORE2_EMON_L3_CTR_CTL5 0x000107D1
1302 #define MSR_CORE2_EMON_L3_CTR_CTL6 0x000107D2
1303 #define MSR_CORE2_EMON_L3_CTR_CTL7 0x000107D3
1308 Unique. L3/FSB Common Control Register (R/W) Apply to Intel Xeon processor
1309 7400 series (processor signature 06_1D) only. See Section 17.2.2.
1311 @param ECX MSR_CORE2_EMON_L3_GL_CTL (0x000107D8)
1312 @param EAX Lower 32-bits of MSR value.
1313 @param EDX Upper 32-bits of MSR value.
1315 <b>Example usage</b>
1319 Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_GL_CTL);
1320 AsmWriteMsr64 (MSR_CORE2_EMON_L3_GL_CTL, Msr);
1323 #define MSR_CORE2_EMON_L3_GL_CTL 0x000107D8