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1 /** @file
2 MSR Definitions for the Intel(R) Core(TM) 2 Processor Family.
3
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
7 provided for that MSR.
8
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
14
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-2.
21
22 **/
23
24 #ifndef __CORE2_MSR_H__
25 #define __CORE2_MSR_H__
26
27 #include <Register/ArchitecturalMsr.h>
28
29 /**
30 Shared. Model Specific Platform ID (R).
31
32 @param ECX MSR_CORE2_PLATFORM_ID (0x00000017)
33 @param EAX Lower 32-bits of MSR value.
34 Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.
35 @param EDX Upper 32-bits of MSR value.
36 Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.
37
38 <b>Example usage</b>
39 @code
40 MSR_CORE2_PLATFORM_ID_REGISTER Msr;
41
42 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PLATFORM_ID);
43 @endcode
44 @note MSR_CORE2_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
45 **/
46 #define MSR_CORE2_PLATFORM_ID 0x00000017
47
48 /**
49 MSR information returned for MSR index #MSR_CORE2_PLATFORM_ID
50 **/
51 typedef union {
52 ///
53 /// Individual bit fields
54 ///
55 struct {
56 UINT32 Reserved1:8;
57 ///
58 /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.
59 ///
60 UINT32 MaximumQualifiedRatio:5;
61 UINT32 Reserved2:19;
62 UINT32 Reserved3:18;
63 ///
64 /// [Bits 52:50] See Table 35-2.
65 ///
66 UINT32 PlatformId:3;
67 UINT32 Reserved4:11;
68 } Bits;
69 ///
70 /// All bit fields as a 64-bit value
71 ///
72 UINT64 Uint64;
73 } MSR_CORE2_PLATFORM_ID_REGISTER;
74
75
76 /**
77 Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
78 processor features; (R) indicates current processor configuration.
79
80 @param ECX MSR_CORE2_EBL_CR_POWERON (0x0000002A)
81 @param EAX Lower 32-bits of MSR value.
82 Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.
83 @param EDX Upper 32-bits of MSR value.
84 Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.
85
86 <b>Example usage</b>
87 @code
88 MSR_CORE2_EBL_CR_POWERON_REGISTER Msr;
89
90 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_EBL_CR_POWERON);
91 AsmWriteMsr64 (MSR_CORE2_EBL_CR_POWERON, Msr.Uint64);
92 @endcode
93 @note MSR_CORE2_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
94 **/
95 #define MSR_CORE2_EBL_CR_POWERON 0x0000002A
96
97 /**
98 MSR information returned for MSR index #MSR_CORE2_EBL_CR_POWERON
99 **/
100 typedef union {
101 ///
102 /// Individual bit fields
103 ///
104 struct {
105 UINT32 Reserved1:1;
106 ///
107 /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
108 /// Note: Not all processor implements R/W.
109 ///
110 UINT32 DataErrorCheckingEnable:1;
111 ///
112 /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
113 /// Note: Not all processor implements R/W.
114 ///
115 UINT32 ResponseErrorCheckingEnable:1;
116 ///
117 /// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
118 /// all processor implements R/W.
119 ///
120 UINT32 MCERR_DriveEnable:1;
121 ///
122 /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:
123 /// Not all processor implements R/W.
124 ///
125 UINT32 AddressParityEnable:1;
126 UINT32 Reserved2:1;
127 UINT32 Reserved3:1;
128 ///
129 /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
130 /// all processor implements R/W.
131 ///
132 UINT32 BINIT_DriverEnable:1;
133 ///
134 /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
135 ///
136 UINT32 OutputTriStateEnable:1;
137 ///
138 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
139 ///
140 UINT32 ExecuteBIST:1;
141 ///
142 /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
143 ///
144 UINT32 MCERR_ObservationEnabled:1;
145 ///
146 /// [Bit 11] Intel TXT Capable Chipset. (R/O) 1 = Present; 0 = Not Present.
147 ///
148 UINT32 IntelTXTCapableChipset:1;
149 ///
150 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
151 ///
152 UINT32 BINIT_ObservationEnabled:1;
153 UINT32 Reserved4:1;
154 ///
155 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
156 ///
157 UINT32 ResetVector:1;
158 UINT32 Reserved5:1;
159 ///
160 /// [Bits 17:16] APIC Cluster ID (R/O).
161 ///
162 UINT32 APICClusterID:2;
163 ///
164 /// [Bit 18] N/2 Non-Integer Bus Ratio (R/O) 0 = Integer ratio; 1 =
165 /// Non-integer ratio.
166 ///
167 UINT32 NonIntegerBusRatio:1;
168 UINT32 Reserved6:1;
169 ///
170 /// [Bits 21:20] Symmetric Arbitration ID (R/O).
171 ///
172 UINT32 SymmetricArbitrationID:2;
173 ///
174 /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
175 ///
176 UINT32 IntegerBusFrequencyRatio:5;
177 UINT32 Reserved7:5;
178 UINT32 Reserved8:32;
179 } Bits;
180 ///
181 /// All bit fields as a 32-bit value
182 ///
183 UINT32 Uint32;
184 ///
185 /// All bit fields as a 64-bit value
186 ///
187 UINT64 Uint64;
188 } MSR_CORE2_EBL_CR_POWERON_REGISTER;
189
190
191 /**
192 Unique. Control Features in Intel 64Processor (R/W) See Table 35-2.
193
194 @param ECX MSR_CORE2_FEATURE_CONTROL (0x0000003A)
195 @param EAX Lower 32-bits of MSR value.
196 Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.
197 @param EDX Upper 32-bits of MSR value.
198 Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.
199
200 <b>Example usage</b>
201 @code
202 MSR_CORE2_FEATURE_CONTROL_REGISTER Msr;
203
204 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FEATURE_CONTROL);
205 AsmWriteMsr64 (MSR_CORE2_FEATURE_CONTROL, Msr.Uint64);
206 @endcode
207 @note MSR_CORE2_FEATURE_CONTROL is defined as MSR_FEATURE_CONTROL in SDM.
208 **/
209 #define MSR_CORE2_FEATURE_CONTROL 0x0000003A
210
211 /**
212 MSR information returned for MSR index #MSR_CORE2_FEATURE_CONTROL
213 **/
214 typedef union {
215 ///
216 /// Individual bit fields
217 ///
218 struct {
219 UINT32 Reserved1:3;
220 ///
221 /// [Bit 3] Unique. SMRR Enable (R/WL) When this bit is set and the lock
222 /// bit is set makes the SMRR_PHYS_BASE and SMRR_PHYS_MASK registers read
223 /// visible and writeable while in SMM.
224 ///
225 UINT32 SMRREnable:1;
226 UINT32 Reserved2:28;
227 UINT32 Reserved3:32;
228 } Bits;
229 ///
230 /// All bit fields as a 32-bit value
231 ///
232 UINT32 Uint32;
233 ///
234 /// All bit fields as a 64-bit value
235 ///
236 UINT64 Uint64;
237 } MSR_CORE2_FEATURE_CONTROL_REGISTER;
238
239
240 /**
241 Unique. Last Branch Record n From IP (R/W) One of four pairs of last branch
242 record registers on the last branch record stack. This part of the stack
243 contains pointers to the source instruction for one of the last four
244 branches, exceptions, or interrupts taken by the processor. See also: -
245 Last Branch Record Stack TOS at 1C9H - Section 17.12, "Last Branch,
246 Interrupt, and Exception Recording (Pentium M Processors).".
247
248 @param ECX MSR_CORE2_LASTBRANCH_n_FROM_IP
249 @param EAX Lower 32-bits of MSR value.
250 @param EDX Upper 32-bits of MSR value.
251
252 <b>Example usage</b>
253 @code
254 UINT64 Msr;
255
256 Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP);
257 AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP, Msr);
258 @endcode
259 @note MSR_CORE2_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
260 MSR_CORE2_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
261 MSR_CORE2_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
262 MSR_CORE2_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
263 @{
264 **/
265 #define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x00000040
266 #define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x00000041
267 #define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x00000042
268 #define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x00000043
269 /// @}
270
271
272 /**
273 Unique. Last Branch Record n To IP (R/W) One of four pairs of last branch
274 record registers on the last branch record stack. This part of the stack
275 contains pointers to the destination instruction for one of the last four
276 branches, exceptions, or interrupts taken by the processor.
277
278 @param ECX MSR_CORE2_LASTBRANCH_n_TO_IP
279 @param EAX Lower 32-bits of MSR value.
280 @param EDX Upper 32-bits of MSR value.
281
282 <b>Example usage</b>
283 @code
284 UINT64 Msr;
285
286 Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP);
287 AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP, Msr);
288 @endcode
289 @note MSR_CORE2_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
290 MSR_CORE2_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
291 MSR_CORE2_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
292 MSR_CORE2_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
293 @{
294 **/
295 #define MSR_CORE2_LASTBRANCH_0_TO_IP 0x00000060
296 #define MSR_CORE2_LASTBRANCH_1_TO_IP 0x00000061
297 #define MSR_CORE2_LASTBRANCH_2_TO_IP 0x00000062
298 #define MSR_CORE2_LASTBRANCH_3_TO_IP 0x00000063
299 /// @}
300
301
302 /**
303 Unique. System Management Mode Base Address register (WO in SMM)
304 Model-specific implementation of SMRR-like interface, read visible and write
305 only in SMM.
306
307 @param ECX MSR_CORE2_SMRR_PHYSBASE (0x000000A0)
308 @param EAX Lower 32-bits of MSR value.
309 Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.
310 @param EDX Upper 32-bits of MSR value.
311 Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.
312
313 <b>Example usage</b>
314 @code
315 MSR_CORE2_SMRR_PHYSBASE_REGISTER Msr;
316
317 Msr.Uint64 = 0;
318 AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSBASE, Msr.Uint64);
319 @endcode
320 @note MSR_CORE2_SMRR_PHYSBASE is defined as MSR_SMRR_PHYSBASE in SDM.
321 **/
322 #define MSR_CORE2_SMRR_PHYSBASE 0x000000A0
323
324 /**
325 MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSBASE
326 **/
327 typedef union {
328 ///
329 /// Individual bit fields
330 ///
331 struct {
332 UINT32 Reserved1:12;
333 ///
334 /// [Bits 31:12] PhysBase. SMRR physical Base Address.
335 ///
336 UINT32 PhysBase:20;
337 UINT32 Reserved2:32;
338 } Bits;
339 ///
340 /// All bit fields as a 32-bit value
341 ///
342 UINT32 Uint32;
343 ///
344 /// All bit fields as a 64-bit value
345 ///
346 UINT64 Uint64;
347 } MSR_CORE2_SMRR_PHYSBASE_REGISTER;
348
349
350 /**
351 Unique. System Management Mode Physical Address Mask register (WO in SMM)
352 Model-specific implementation of SMRR-like interface, read visible and write
353 only in SMM.
354
355 @param ECX MSR_CORE2_SMRR_PHYSMASK (0x000000A1)
356 @param EAX Lower 32-bits of MSR value.
357 Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.
358 @param EDX Upper 32-bits of MSR value.
359 Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.
360
361 <b>Example usage</b>
362 @code
363 MSR_CORE2_SMRR_PHYSMASK_REGISTER Msr;
364
365 Msr.Uint64 = 0;
366 AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSMASK, Msr.Uint64);
367 @endcode
368 @note MSR_CORE2_SMRR_PHYSMASK is defined as MSR_SMRR_PHYSMASK in SDM.
369 **/
370 #define MSR_CORE2_SMRR_PHYSMASK 0x000000A1
371
372 /**
373 MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSMASK
374 **/
375 typedef union {
376 ///
377 /// Individual bit fields
378 ///
379 struct {
380 UINT32 Reserved1:11;
381 ///
382 /// [Bit 11] Valid. Physical address base and range mask are valid.
383 ///
384 UINT32 Valid:1;
385 ///
386 /// [Bits 31:12] PhysMask. SMRR physical address range mask.
387 ///
388 UINT32 PhysMask:20;
389 UINT32 Reserved2:32;
390 } Bits;
391 ///
392 /// All bit fields as a 32-bit value
393 ///
394 UINT32 Uint32;
395 ///
396 /// All bit fields as a 64-bit value
397 ///
398 UINT64 Uint64;
399 } MSR_CORE2_SMRR_PHYSMASK_REGISTER;
400
401
402 /**
403 Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
404 bus clock speed for processors based on Intel Core microarchitecture:.
405
406 @param ECX MSR_CORE2_FSB_FREQ (0x000000CD)
407 @param EAX Lower 32-bits of MSR value.
408 Described by the type MSR_CORE2_FSB_FREQ_REGISTER.
409 @param EDX Upper 32-bits of MSR value.
410 Described by the type MSR_CORE2_FSB_FREQ_REGISTER.
411
412 <b>Example usage</b>
413 @code
414 MSR_CORE2_FSB_FREQ_REGISTER Msr;
415
416 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FSB_FREQ);
417 @endcode
418 @note MSR_CORE2_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
419 **/
420 #define MSR_CORE2_FSB_FREQ 0x000000CD
421
422 /**
423 MSR information returned for MSR index #MSR_CORE2_FSB_FREQ
424 **/
425 typedef union {
426 ///
427 /// Individual bit fields
428 ///
429 struct {
430 ///
431 /// [Bits 2:0] - Scalable Bus Speed
432 /// 101B: 100 MHz (FSB 400)
433 /// 001B: 133 MHz (FSB 533)
434 /// 011B: 167 MHz (FSB 667)
435 /// 010B: 200 MHz (FSB 800)
436 /// 000B: 267 MHz (FSB 1067)
437 /// 100B: 333 MHz (FSB 1333)
438 ///
439 /// 133.33 MHz should be utilized if performing calculation with System
440 /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if
441 /// performing calculation with System Bus Speed when encoding is 011B.
442 /// 266.67 MHz should be utilized if performing calculation with System
443 /// Bus Speed when encoding is 000B. 333.33 MHz should be utilized if
444 /// performing calculation with System Bus Speed when encoding is 100B.
445 ///
446 UINT32 ScalableBusSpeed:3;
447 UINT32 Reserved1:29;
448 UINT32 Reserved2:32;
449 } Bits;
450 ///
451 /// All bit fields as a 32-bit value
452 ///
453 UINT32 Uint32;
454 ///
455 /// All bit fields as a 64-bit value
456 ///
457 UINT64 Uint64;
458 } MSR_CORE2_FSB_FREQ_REGISTER;
459
460
461 /**
462 Shared.
463
464 @param ECX MSR_CORE2_BBL_CR_CTL3 (0x0000011E)
465 @param EAX Lower 32-bits of MSR value.
466 Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER.
467 @param EDX Upper 32-bits of MSR value.
468 Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER.
469
470 <b>Example usage</b>
471 @code
472 MSR_CORE2_BBL_CR_CTL3_REGISTER Msr;
473
474 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_BBL_CR_CTL3);
475 AsmWriteMsr64 (MSR_CORE2_BBL_CR_CTL3, Msr.Uint64);
476 @endcode
477 @note MSR_CORE2_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
478 **/
479 #define MSR_CORE2_BBL_CR_CTL3 0x0000011E
480
481 /**
482 MSR information returned for MSR index #MSR_CORE2_BBL_CR_CTL3
483 **/
484 typedef union {
485 ///
486 /// Individual bit fields
487 ///
488 struct {
489 ///
490 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
491 /// Indicates if the L2 is hardware-disabled.
492 ///
493 UINT32 L2HardwareEnabled:1;
494 UINT32 Reserved1:7;
495 ///
496 /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
497 /// Disabled (default) Until this bit is set the processor will not
498 /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
499 ///
500 UINT32 L2Enabled:1;
501 UINT32 Reserved2:14;
502 ///
503 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
504 ///
505 UINT32 L2NotPresent:1;
506 UINT32 Reserved3:8;
507 UINT32 Reserved4:32;
508 } Bits;
509 ///
510 /// All bit fields as a 32-bit value
511 ///
512 UINT32 Uint32;
513 ///
514 /// All bit fields as a 64-bit value
515 ///
516 UINT64 Uint64;
517 } MSR_CORE2_BBL_CR_CTL3_REGISTER;
518
519
520 /**
521 Shared.
522
523 @param ECX MSR_CORE2_PERF_STATUS (0x00000198)
524 @param EAX Lower 32-bits of MSR value.
525 Described by the type MSR_CORE2_PERF_STATUS_REGISTER.
526 @param EDX Upper 32-bits of MSR value.
527 Described by the type MSR_CORE2_PERF_STATUS_REGISTER.
528
529 <b>Example usage</b>
530 @code
531 MSR_CORE2_PERF_STATUS_REGISTER Msr;
532
533 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_STATUS);
534 AsmWriteMsr64 (MSR_CORE2_PERF_STATUS, Msr.Uint64);
535 @endcode
536 @note MSR_CORE2_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
537 **/
538 #define MSR_CORE2_PERF_STATUS 0x00000198
539
540 /**
541 MSR information returned for MSR index #MSR_CORE2_PERF_STATUS
542 **/
543 typedef union {
544 ///
545 /// Individual bit fields
546 ///
547 struct {
548 ///
549 /// [Bits 15:0] Current Performance State Value.
550 ///
551 UINT32 CurrentPerformanceStateValue:16;
552 UINT32 Reserved1:15;
553 ///
554 /// [Bit 31] XE Operation (R/O). If set, XE operation is enabled. Default
555 /// is cleared.
556 ///
557 UINT32 XEOperation:1;
558 UINT32 Reserved2:8;
559 ///
560 /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio
561 /// configured for the processor.
562 ///
563 UINT32 MaximumBusRatio:5;
564 UINT32 Reserved3:1;
565 ///
566 /// [Bit 46] Non-Integer Bus Ratio (R/O) Indicates non-integer bus ratio
567 /// is enabled. Applies processors based on Enhanced Intel Core
568 /// microarchitecture.
569 ///
570 UINT32 NonIntegerBusRatio:1;
571 UINT32 Reserved4:17;
572 } Bits;
573 ///
574 /// All bit fields as a 64-bit value
575 ///
576 UINT64 Uint64;
577 } MSR_CORE2_PERF_STATUS_REGISTER;
578
579
580 /**
581 Unique.
582
583 @param ECX MSR_CORE2_THERM2_CTL (0x0000019D)
584 @param EAX Lower 32-bits of MSR value.
585 Described by the type MSR_CORE2_THERM2_CTL_REGISTER.
586 @param EDX Upper 32-bits of MSR value.
587 Described by the type MSR_CORE2_THERM2_CTL_REGISTER.
588
589 <b>Example usage</b>
590 @code
591 MSR_CORE2_THERM2_CTL_REGISTER Msr;
592
593 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_THERM2_CTL);
594 AsmWriteMsr64 (MSR_CORE2_THERM2_CTL, Msr.Uint64);
595 @endcode
596 @note MSR_CORE2_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
597 **/
598 #define MSR_CORE2_THERM2_CTL 0x0000019D
599
600 /**
601 MSR information returned for MSR index #MSR_CORE2_THERM2_CTL
602 **/
603 typedef union {
604 ///
605 /// Individual bit fields
606 ///
607 struct {
608 UINT32 Reserved1:16;
609 ///
610 /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
611 /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
612 /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
613 /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
614 /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.
615 ///
616 UINT32 TM_SELECT:1;
617 UINT32 Reserved2:15;
618 UINT32 Reserved3:32;
619 } Bits;
620 ///
621 /// All bit fields as a 32-bit value
622 ///
623 UINT32 Uint32;
624 ///
625 /// All bit fields as a 64-bit value
626 ///
627 UINT64 Uint64;
628 } MSR_CORE2_THERM2_CTL_REGISTER;
629
630
631 /**
632 Enable Misc. Processor Features (R/W) Allows a variety of processor
633 functions to be enabled and disabled.
634
635 @param ECX MSR_CORE2_IA32_MISC_ENABLE (0x000001A0)
636 @param EAX Lower 32-bits of MSR value.
637 Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.
638 @param EDX Upper 32-bits of MSR value.
639 Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.
640
641 <b>Example usage</b>
642 @code
643 MSR_CORE2_IA32_MISC_ENABLE_REGISTER Msr;
644
645 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_IA32_MISC_ENABLE);
646 AsmWriteMsr64 (MSR_CORE2_IA32_MISC_ENABLE, Msr.Uint64);
647 @endcode
648 @note MSR_CORE2_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
649 **/
650 #define MSR_CORE2_IA32_MISC_ENABLE 0x000001A0
651
652 /**
653 MSR information returned for MSR index #MSR_CORE2_IA32_MISC_ENABLE
654 **/
655 typedef union {
656 ///
657 /// Individual bit fields
658 ///
659 struct {
660 ///
661 /// [Bit 0] Fast-Strings Enable See Table 35-2.
662 ///
663 UINT32 FastStrings:1;
664 UINT32 Reserved1:2;
665 ///
666 /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
667 /// Table 35-2.
668 ///
669 UINT32 AutomaticThermalControlCircuit:1;
670 UINT32 Reserved2:3;
671 ///
672 /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.
673 ///
674 UINT32 PerformanceMonitoring:1;
675 UINT32 Reserved3:1;
676 ///
677 /// [Bit 9] Hardware Prefetcher Disable (R/W) When set, disables the
678 /// hardware prefetcher operation on streams of data. When clear
679 /// (default), enables the prefetch queue. Disabling of the hardware
680 /// prefetcher may impact processor performance.
681 ///
682 UINT32 HardwarePrefetcherDisable:1;
683 ///
684 /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
685 /// the processor to indicate a pending break event within the processor 0
686 /// = Indicates compatible FERR# signaling behavior This bit must be set
687 /// to 1 to support XAPIC interrupt model usage.
688 ///
689 UINT32 FERR:1;
690 ///
691 /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.
692 ///
693 UINT32 BTS:1;
694 ///
695 /// [Bit 12] Shared. Precise Event Based Sampling Unavailable (RO) See
696 /// Table 35-2.
697 ///
698 UINT32 PEBS:1;
699 ///
700 /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
701 /// thermal sensor indicates that the die temperature is at the
702 /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
703 /// TM2 will reduce the bus to core ratio and voltage according to the
704 /// value last written to MSR_THERM2_CTL bits 15:0.
705 /// When this bit is clear (0, default), the processor does not change
706 /// the VID signals or the bus to core ratio when the processor enters a
707 /// thermally managed state. The BIOS must enable this feature if the
708 /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is
709 /// not set, this feature is not supported and BIOS must not alter the
710 /// contents of the TM2 bit location. The processor is operating out of
711 /// specification if both this bit and the TM1 bit are set to 0.
712 ///
713 UINT32 TM2:1;
714 UINT32 Reserved4:2;
715 ///
716 /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
717 /// Table 35-2.
718 ///
719 UINT32 EIST:1;
720 UINT32 Reserved5:1;
721 ///
722 /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.
723 ///
724 UINT32 MONITOR:1;
725 ///
726 /// [Bit 19] Shared. Adjacent Cache Line Prefetch Disable (R/W) When set
727 /// to 1, the processor fetches the cache line that contains data
728 /// currently required by the processor. When set to 0, the processor
729 /// fetches cache lines that comprise a cache line pair (128 bytes).
730 /// Single processor platforms should not set this bit. Server platforms
731 /// should set or clear this bit based on platform performance observed in
732 /// validation and testing. BIOS may contain a setup option that controls
733 /// the setting of this bit.
734 ///
735 UINT32 AdjacentCacheLinePrefetchDisable:1;
736 ///
737 /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock
738 /// (R/WO) When set, this bit causes the following bits to become
739 /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this
740 /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must
741 /// be set before an Enhanced Intel SpeedStep Technology transition is
742 /// requested. This bit is cleared on reset.
743 ///
744 UINT32 EISTLock:1;
745 UINT32 Reserved6:1;
746 ///
747 /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 35-2.
748 ///
749 UINT32 LimitCpuidMaxval:1;
750 ///
751 /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.
752 ///
753 UINT32 xTPR_Message_Disable:1;
754 UINT32 Reserved7:8;
755 UINT32 Reserved8:2;
756 ///
757 /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.
758 ///
759 UINT32 XD:1;
760 UINT32 Reserved9:2;
761 ///
762 /// [Bit 37] Unique. DCU Prefetcher Disable (R/W) When set to 1, The DCU
763 /// L1 data cache prefetcher is disabled. The default value after reset is
764 /// 0. BIOS may write '1' to disable this feature. The DCU prefetcher is
765 /// an L1 data cache prefetcher. When the DCU prefetcher detects multiple
766 /// loads from the same line done within a time limit, the DCU prefetcher
767 /// assumes the next line will be required. The next line is prefetched in
768 /// to the L1 data cache from memory or L2.
769 ///
770 UINT32 DCUPrefetcherDisable:1;
771 ///
772 /// [Bit 38] Shared. IDA Disable (R/W) When set to 1 on processors that
773 /// support IDA, the Intel Dynamic Acceleration feature (IDA) is disabled
774 /// and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0).
775 /// When set to a 0 on processors that support IDA, CPUID.06H: EAX[1]
776 /// reports the processor's support of IDA is enabled. Note: the power-on
777 /// default value is used by BIOS to detect hardware support of IDA. If
778 /// power-on default value is 1, IDA is available in the processor. If
779 /// power-on default value is 0, IDA is not available.
780 ///
781 UINT32 IDADisable:1;
782 ///
783 /// [Bit 39] Unique. IP Prefetcher Disable (R/W) When set to 1, The IP
784 /// prefetcher is disabled. The default value after reset is 0. BIOS may
785 /// write '1' to disable this feature. The IP prefetcher is an L1 data
786 /// cache prefetcher. The IP prefetcher looks for sequential load history
787 /// to determine whether to prefetch the next expected data into the L1
788 /// cache from memory or L2.
789 ///
790 UINT32 IPPrefetcherDisable:1;
791 UINT32 Reserved10:24;
792 } Bits;
793 ///
794 /// All bit fields as a 64-bit value
795 ///
796 UINT64 Uint64;
797 } MSR_CORE2_IA32_MISC_ENABLE_REGISTER;
798
799
800 /**
801 Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
802 that points to the MSR containing the most recent branch record. See
803 MSR_LASTBRANCH_0_FROM_IP (at 40H).
804
805 @param ECX MSR_CORE2_LASTBRANCH_TOS (0x000001C9)
806 @param EAX Lower 32-bits of MSR value.
807 @param EDX Upper 32-bits of MSR value.
808
809 <b>Example usage</b>
810 @code
811 UINT64 Msr;
812
813 Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_TOS);
814 AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_TOS, Msr);
815 @endcode
816 @note MSR_CORE2_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
817 **/
818 #define MSR_CORE2_LASTBRANCH_TOS 0x000001C9
819
820
821 /**
822 Unique. Last Exception Record From Linear IP (R) Contains a pointer to the
823 last branch instruction that the processor executed prior to the last
824 exception that was generated or the last interrupt that was handled.
825
826 @param ECX MSR_CORE2_LER_FROM_LIP (0x000001DD)
827 @param EAX Lower 32-bits of MSR value.
828 @param EDX Upper 32-bits of MSR value.
829
830 <b>Example usage</b>
831 @code
832 UINT64 Msr;
833
834 Msr = AsmReadMsr64 (MSR_CORE2_LER_FROM_LIP);
835 @endcode
836 @note MSR_CORE2_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
837 **/
838 #define MSR_CORE2_LER_FROM_LIP 0x000001DD
839
840
841 /**
842 Unique. Last Exception Record To Linear IP (R) This area contains a pointer
843 to the target of the last branch instruction that the processor executed
844 prior to the last exception that was generated or the last interrupt that
845 was handled.
846
847 @param ECX MSR_CORE2_LER_TO_LIP (0x000001DE)
848 @param EAX Lower 32-bits of MSR value.
849 @param EDX Upper 32-bits of MSR value.
850
851 <b>Example usage</b>
852 @code
853 UINT64 Msr;
854
855 Msr = AsmReadMsr64 (MSR_CORE2_LER_TO_LIP);
856 @endcode
857 @note MSR_CORE2_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
858 **/
859 #define MSR_CORE2_LER_TO_LIP 0x000001DE
860
861
862 /**
863 Unique. Fixed-Function Performance Counter Register n (R/W).
864
865 @param ECX MSR_CORE2_PERF_FIXED_CTRn
866 @param EAX Lower 32-bits of MSR value.
867 @param EDX Upper 32-bits of MSR value.
868
869 <b>Example usage</b>
870 @code
871 UINT64 Msr;
872
873 Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR0);
874 AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR0, Msr);
875 @endcode
876 @note MSR_CORE2_PERF_FIXED_CTR0 is defined as MSR_PERF_FIXED_CTR0 in SDM.
877 MSR_CORE2_PERF_FIXED_CTR1 is defined as MSR_PERF_FIXED_CTR1 in SDM.
878 MSR_CORE2_PERF_FIXED_CTR2 is defined as MSR_PERF_FIXED_CTR2 in SDM.
879 @{
880 **/
881 #define MSR_CORE2_PERF_FIXED_CTR0 0x00000309
882 #define MSR_CORE2_PERF_FIXED_CTR1 0x0000030A
883 #define MSR_CORE2_PERF_FIXED_CTR2 0x0000030B
884 /// @}
885
886
887 /**
888 Unique. RO. This applies to processors that do not support architectural
889 perfmon version 2.
890
891 @param ECX MSR_CORE2_PERF_CAPABILITIES (0x00000345)
892 @param EAX Lower 32-bits of MSR value.
893 Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.
894 @param EDX Upper 32-bits of MSR value.
895 Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.
896
897 <b>Example usage</b>
898 @code
899 MSR_CORE2_PERF_CAPABILITIES_REGISTER Msr;
900
901 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_CAPABILITIES);
902 AsmWriteMsr64 (MSR_CORE2_PERF_CAPABILITIES, Msr.Uint64);
903 @endcode
904 @note MSR_CORE2_PERF_CAPABILITIES is defined as MSR_PERF_CAPABILITIES in SDM.
905 **/
906 #define MSR_CORE2_PERF_CAPABILITIES 0x00000345
907
908 /**
909 MSR information returned for MSR index #MSR_CORE2_PERF_CAPABILITIES
910 **/
911 typedef union {
912 ///
913 /// Individual bit fields
914 ///
915 struct {
916 ///
917 /// [Bits 5:0] LBR Format. See Table 35-2.
918 ///
919 UINT32 LBR_FMT:6;
920 ///
921 /// [Bit 6] PEBS Record Format.
922 ///
923 UINT32 PEBS_FMT:1;
924 ///
925 /// [Bit 7] PEBSSaveArchRegs. See Table 35-2.
926 ///
927 UINT32 PEBS_ARCH_REG:1;
928 UINT32 Reserved1:24;
929 UINT32 Reserved2:32;
930 } Bits;
931 ///
932 /// All bit fields as a 32-bit value
933 ///
934 UINT32 Uint32;
935 ///
936 /// All bit fields as a 64-bit value
937 ///
938 UINT64 Uint64;
939 } MSR_CORE2_PERF_CAPABILITIES_REGISTER;
940
941
942 /**
943 Unique. Fixed-Function-Counter Control Register (R/W).
944
945 @param ECX MSR_CORE2_PERF_FIXED_CTR_CTRL (0x0000038D)
946 @param EAX Lower 32-bits of MSR value.
947 @param EDX Upper 32-bits of MSR value.
948
949 <b>Example usage</b>
950 @code
951 UINT64 Msr;
952
953 Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL);
954 AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL, Msr);
955 @endcode
956 @note MSR_CORE2_PERF_FIXED_CTR_CTRL is defined as MSR_PERF_FIXED_CTR_CTRL in SDM.
957 **/
958 #define MSR_CORE2_PERF_FIXED_CTR_CTRL 0x0000038D
959
960
961 /**
962 Unique. See Table 35-2. See Section 18.4.2, "Global Counter Control
963 Facilities.".
964
965 @param ECX MSR_CORE2_IA32_PERF_GLOBAL_STAUS (0x0000038E)
966 @param EAX Lower 32-bits of MSR value.
967 @param EDX Upper 32-bits of MSR value.
968
969 <b>Example usage</b>
970 @code
971 UINT64 Msr;
972
973 Msr = AsmReadMsr64 (MSR_CORE2_IA32_PERF_GLOBAL_STAUS);
974 AsmWriteMsr64 (MSR_CORE2_IA32_PERF_GLOBAL_STAUS, Msr);
975 @endcode
976 @note MSR_CORE2_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
977 **/
978 #define MSR_CORE2_IA32_PERF_GLOBAL_STAUS 0x0000038E
979
980
981 /**
982 Unique. See Section 18.4.2, "Global Counter Control Facilities.".
983
984 @param ECX MSR_CORE2_PERF_GLOBAL_STAUS (0x0000038E)
985 @param EAX Lower 32-bits of MSR value.
986 @param EDX Upper 32-bits of MSR value.
987
988 <b>Example usage</b>
989 @code
990 UINT64 Msr;
991
992 Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STAUS);
993 AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STAUS, Msr);
994 @endcode
995 @note MSR_CORE2_PERF_GLOBAL_STAUS is defined as MSR_PERF_GLOBAL_STAUS in SDM.
996 **/
997 #define MSR_CORE2_PERF_GLOBAL_STAUS 0x0000038E
998
999
1000 /**
1001 Unique. See Section 18.4.2, "Global Counter Control Facilities.".
1002
1003 @param ECX MSR_CORE2_PERF_GLOBAL_CTRL (0x0000038F)
1004 @param EAX Lower 32-bits of MSR value.
1005 @param EDX Upper 32-bits of MSR value.
1006
1007 <b>Example usage</b>
1008 @code
1009 UINT64 Msr;
1010
1011 Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL);
1012 AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL, Msr);
1013 @endcode
1014 @note MSR_CORE2_PERF_GLOBAL_CTRL is defined as MSR_PERF_GLOBAL_CTRL in SDM.
1015 **/
1016 #define MSR_CORE2_PERF_GLOBAL_CTRL 0x0000038F
1017
1018
1019 /**
1020 Unique. See Section 18.4.2, "Global Counter Control Facilities.".
1021
1022 @param ECX MSR_CORE2_PERF_GLOBAL_OVF_CTRL (0x00000390)
1023 @param EAX Lower 32-bits of MSR value.
1024 @param EDX Upper 32-bits of MSR value.
1025
1026 <b>Example usage</b>
1027 @code
1028 UINT64 Msr;
1029
1030 Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL);
1031 AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL, Msr);
1032 @endcode
1033 @note MSR_CORE2_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.
1034 **/
1035 #define MSR_CORE2_PERF_GLOBAL_OVF_CTRL 0x00000390
1036
1037
1038 /**
1039 Unique. See Table 35-2. See Section 18.4.4, "Precise Event Based Sampling
1040 (PEBS).".
1041
1042 @param ECX MSR_CORE2_PEBS_ENABLE (0x000003F1)
1043 @param EAX Lower 32-bits of MSR value.
1044 Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.
1045 @param EDX Upper 32-bits of MSR value.
1046 Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.
1047
1048 <b>Example usage</b>
1049 @code
1050 MSR_CORE2_PEBS_ENABLE_REGISTER Msr;
1051
1052 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PEBS_ENABLE);
1053 AsmWriteMsr64 (MSR_CORE2_PEBS_ENABLE, Msr.Uint64);
1054 @endcode
1055 @note MSR_CORE2_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1056 **/
1057 #define MSR_CORE2_PEBS_ENABLE 0x000003F1
1058
1059 /**
1060 MSR information returned for MSR index #MSR_CORE2_PEBS_ENABLE
1061 **/
1062 typedef union {
1063 ///
1064 /// Individual bit fields
1065 ///
1066 struct {
1067 ///
1068 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
1069 ///
1070 UINT32 Enable:1;
1071 UINT32 Reserved1:31;
1072 UINT32 Reserved2:32;
1073 } Bits;
1074 ///
1075 /// All bit fields as a 32-bit value
1076 ///
1077 UINT32 Uint32;
1078 ///
1079 /// All bit fields as a 64-bit value
1080 ///
1081 UINT64 Uint64;
1082 } MSR_CORE2_PEBS_ENABLE_REGISTER;
1083
1084
1085 /**
1086 Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
1087
1088 @param ECX MSR_CORE2_MC4_CTL (0x0000040C)
1089 @param EAX Lower 32-bits of MSR value.
1090 @param EDX Upper 32-bits of MSR value.
1091
1092 <b>Example usage</b>
1093 @code
1094 UINT64 Msr;
1095
1096 Msr = AsmReadMsr64 (MSR_CORE2_MC4_CTL);
1097 AsmWriteMsr64 (MSR_CORE2_MC4_CTL, Msr);
1098 @endcode
1099 @note MSR_CORE2_MC4_CTL is defined as MSR_MC4_CTL in SDM.
1100 **/
1101 #define MSR_CORE2_MC4_CTL 0x0000040C
1102
1103
1104 /**
1105 Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
1106
1107 @param ECX MSR_CORE2_MC4_STATUS (0x0000040D)
1108 @param EAX Lower 32-bits of MSR value.
1109 @param EDX Upper 32-bits of MSR value.
1110
1111 <b>Example usage</b>
1112 @code
1113 UINT64 Msr;
1114
1115 Msr = AsmReadMsr64 (MSR_CORE2_MC4_STATUS);
1116 AsmWriteMsr64 (MSR_CORE2_MC4_STATUS, Msr);
1117 @endcode
1118 @note MSR_CORE2_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
1119 **/
1120 #define MSR_CORE2_MC4_STATUS 0x0000040D
1121
1122
1123 /**
1124 Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR
1125 register is either not implemented or contains no address if the ADDRV flag
1126 in the MSR_MC4_STATUS register is clear. When not implemented in the
1127 processor, all reads and writes to this MSR will cause a general-protection
1128 exception.
1129
1130 @param ECX MSR_CORE2_MC4_ADDR (0x0000040E)
1131 @param EAX Lower 32-bits of MSR value.
1132 @param EDX Upper 32-bits of MSR value.
1133
1134 <b>Example usage</b>
1135 @code
1136 UINT64 Msr;
1137
1138 Msr = AsmReadMsr64 (MSR_CORE2_MC4_ADDR);
1139 AsmWriteMsr64 (MSR_CORE2_MC4_ADDR, Msr);
1140 @endcode
1141 @note MSR_CORE2_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
1142 **/
1143 #define MSR_CORE2_MC4_ADDR 0x0000040E
1144
1145
1146 /**
1147 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
1148
1149 @param ECX MSR_CORE2_MC3_CTL (0x00000410)
1150 @param EAX Lower 32-bits of MSR value.
1151 @param EDX Upper 32-bits of MSR value.
1152
1153 <b>Example usage</b>
1154 @code
1155 UINT64 Msr;
1156
1157 Msr = AsmReadMsr64 (MSR_CORE2_MC3_CTL);
1158 AsmWriteMsr64 (MSR_CORE2_MC3_CTL, Msr);
1159 @endcode
1160 @note MSR_CORE2_MC3_CTL is defined as MSR_MC3_CTL in SDM.
1161 **/
1162 #define MSR_CORE2_MC3_CTL 0x00000410
1163
1164
1165 /**
1166 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
1167
1168 @param ECX MSR_CORE2_MC3_STATUS (0x00000411)
1169 @param EAX Lower 32-bits of MSR value.
1170 @param EDX Upper 32-bits of MSR value.
1171
1172 <b>Example usage</b>
1173 @code
1174 UINT64 Msr;
1175
1176 Msr = AsmReadMsr64 (MSR_CORE2_MC3_STATUS);
1177 AsmWriteMsr64 (MSR_CORE2_MC3_STATUS, Msr);
1178 @endcode
1179 @note MSR_CORE2_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
1180 **/
1181 #define MSR_CORE2_MC3_STATUS 0x00000411
1182
1183
1184 /**
1185 Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR
1186 register is either not implemented or contains no address if the ADDRV flag
1187 in the MSR_MC3_STATUS register is clear. When not implemented in the
1188 processor, all reads and writes to this MSR will cause a general-protection
1189 exception.
1190
1191 @param ECX MSR_CORE2_MC3_ADDR (0x00000412)
1192 @param EAX Lower 32-bits of MSR value.
1193 @param EDX Upper 32-bits of MSR value.
1194
1195 <b>Example usage</b>
1196 @code
1197 UINT64 Msr;
1198
1199 Msr = AsmReadMsr64 (MSR_CORE2_MC3_ADDR);
1200 AsmWriteMsr64 (MSR_CORE2_MC3_ADDR, Msr);
1201 @endcode
1202 @note MSR_CORE2_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
1203 **/
1204 #define MSR_CORE2_MC3_ADDR 0x00000412
1205
1206
1207 /**
1208 Unique.
1209
1210 @param ECX MSR_CORE2_MC3_MISC (0x00000413)
1211 @param EAX Lower 32-bits of MSR value.
1212 @param EDX Upper 32-bits of MSR value.
1213
1214 <b>Example usage</b>
1215 @code
1216 UINT64 Msr;
1217
1218 Msr = AsmReadMsr64 (MSR_CORE2_MC3_MISC);
1219 AsmWriteMsr64 (MSR_CORE2_MC3_MISC, Msr);
1220 @endcode
1221 @note MSR_CORE2_MC3_MISC is defined as MSR_MC3_MISC in SDM.
1222 **/
1223 #define MSR_CORE2_MC3_MISC 0x00000413
1224
1225
1226 /**
1227 Unique.
1228
1229 @param ECX MSR_CORE2_MC5_CTL (0x00000414)
1230 @param EAX Lower 32-bits of MSR value.
1231 @param EDX Upper 32-bits of MSR value.
1232
1233 <b>Example usage</b>
1234 @code
1235 UINT64 Msr;
1236
1237 Msr = AsmReadMsr64 (MSR_CORE2_MC5_CTL);
1238 AsmWriteMsr64 (MSR_CORE2_MC5_CTL, Msr);
1239 @endcode
1240 @note MSR_CORE2_MC5_CTL is defined as MSR_MC5_CTL in SDM.
1241 **/
1242 #define MSR_CORE2_MC5_CTL 0x00000414
1243
1244
1245 /**
1246 Unique.
1247
1248 @param ECX MSR_CORE2_MC5_STATUS (0x00000415)
1249 @param EAX Lower 32-bits of MSR value.
1250 @param EDX Upper 32-bits of MSR value.
1251
1252 <b>Example usage</b>
1253 @code
1254 UINT64 Msr;
1255
1256 Msr = AsmReadMsr64 (MSR_CORE2_MC5_STATUS);
1257 AsmWriteMsr64 (MSR_CORE2_MC5_STATUS, Msr);
1258 @endcode
1259 @note MSR_CORE2_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
1260 **/
1261 #define MSR_CORE2_MC5_STATUS 0x00000415
1262
1263
1264 /**
1265 Unique.
1266
1267 @param ECX MSR_CORE2_MC5_ADDR (0x00000416)
1268 @param EAX Lower 32-bits of MSR value.
1269 @param EDX Upper 32-bits of MSR value.
1270
1271 <b>Example usage</b>
1272 @code
1273 UINT64 Msr;
1274
1275 Msr = AsmReadMsr64 (MSR_CORE2_MC5_ADDR);
1276 AsmWriteMsr64 (MSR_CORE2_MC5_ADDR, Msr);
1277 @endcode
1278 @note MSR_CORE2_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
1279 **/
1280 #define MSR_CORE2_MC5_ADDR 0x00000416
1281
1282
1283 /**
1284 Unique.
1285
1286 @param ECX MSR_CORE2_MC5_MISC (0x00000417)
1287 @param EAX Lower 32-bits of MSR value.
1288 @param EDX Upper 32-bits of MSR value.
1289
1290 <b>Example usage</b>
1291 @code
1292 UINT64 Msr;
1293
1294 Msr = AsmReadMsr64 (MSR_CORE2_MC5_MISC);
1295 AsmWriteMsr64 (MSR_CORE2_MC5_MISC, Msr);
1296 @endcode
1297 @note MSR_CORE2_MC5_MISC is defined as MSR_MC5_MISC in SDM.
1298 **/
1299 #define MSR_CORE2_MC5_MISC 0x00000417
1300
1301
1302 /**
1303 Unique. Apply to Intel Xeon processor 7400 series (processor signature
1304 06_1D) only. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS." and Chapter 23.
1305
1306 @param ECX MSR_CORE2_MC6_STATUS (0x00000419)
1307 @param EAX Lower 32-bits of MSR value.
1308 @param EDX Upper 32-bits of MSR value.
1309
1310 <b>Example usage</b>
1311 @code
1312 UINT64 Msr;
1313
1314 Msr = AsmReadMsr64 (MSR_CORE2_MC6_STATUS);
1315 AsmWriteMsr64 (MSR_CORE2_MC6_STATUS, Msr);
1316 @endcode
1317 @note MSR_CORE2_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.
1318 **/
1319 #define MSR_CORE2_MC6_STATUS 0x00000419
1320
1321
1322 /**
1323 Unique. GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon
1324 processor 7400 series (processor signature 06_1D) only. See Section 17.2.2.
1325
1326 @param ECX MSR_CORE2_EMON_L3_CTR_CTLn
1327 @param EAX Lower 32-bits of MSR value.
1328 @param EDX Upper 32-bits of MSR value.
1329
1330 <b>Example usage</b>
1331 @code
1332 UINT64 Msr;
1333
1334 Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0);
1335 AsmWriteMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0, Msr);
1336 @endcode
1337 @note MSR_CORE2_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.
1338 MSR_CORE2_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.
1339 MSR_CORE2_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.
1340 MSR_CORE2_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.
1341 MSR_CORE2_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.
1342 MSR_CORE2_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.
1343 MSR_CORE2_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.
1344 MSR_CORE2_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.
1345 @{
1346 **/
1347 #define MSR_CORE2_EMON_L3_CTR_CTL0 0x000107CC
1348 #define MSR_CORE2_EMON_L3_CTR_CTL1 0x000107CD
1349 #define MSR_CORE2_EMON_L3_CTR_CTL2 0x000107CE
1350 #define MSR_CORE2_EMON_L3_CTR_CTL3 0x000107CF
1351 #define MSR_CORE2_EMON_L3_CTR_CTL4 0x000107D0
1352 #define MSR_CORE2_EMON_L3_CTR_CTL5 0x000107D1
1353 #define MSR_CORE2_EMON_L3_CTR_CTL6 0x000107D2
1354 #define MSR_CORE2_EMON_L3_CTR_CTL7 0x000107D3
1355 /// @}
1356
1357
1358 /**
1359 Unique. L3/FSB Common Control Register (R/W) Apply to Intel Xeon processor
1360 7400 series (processor signature 06_1D) only. See Section 17.2.2.
1361
1362 @param ECX MSR_CORE2_EMON_L3_GL_CTL (0x000107D8)
1363 @param EAX Lower 32-bits of MSR value.
1364 @param EDX Upper 32-bits of MSR value.
1365
1366 <b>Example usage</b>
1367 @code
1368 UINT64 Msr;
1369
1370 Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_GL_CTL);
1371 AsmWriteMsr64 (MSR_CORE2_EMON_L3_GL_CTL, Msr);
1372 @endcode
1373 @note MSR_CORE2_EMON_L3_GL_CTL is defined as MSR_EMON_L3_GL_CTL in SDM.
1374 **/
1375 #define MSR_CORE2_EMON_L3_GL_CTL 0x000107D8
1376
1377 #endif
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