2 MSR Definitions for Intel Core Solo and Intel Core Duo Processors.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.19.
24 #ifndef __CORE_MSR_H__
25 #define __CORE_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Unique. See Section 35.22, "MSRs in Pentium Processors," and see Table 35-2.
32 @param ECX MSR_CORE_P5_MC_ADDR (0x00000000)
33 @param EAX Lower 32-bits of MSR value.
34 @param EDX Upper 32-bits of MSR value.
40 Msr = AsmReadMsr64 (MSR_CORE_P5_MC_ADDR);
41 AsmWriteMsr64 (MSR_CORE_P5_MC_ADDR, Msr);
43 @note MSR_CORE_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
45 #define MSR_CORE_P5_MC_ADDR 0x00000000
49 Unique. See Section 35.22, "MSRs in Pentium Processors," and see Table 35-2.
51 @param ECX MSR_CORE_P5_MC_TYPE (0x00000001)
52 @param EAX Lower 32-bits of MSR value.
53 @param EDX Upper 32-bits of MSR value.
59 Msr = AsmReadMsr64 (MSR_CORE_P5_MC_TYPE);
60 AsmWriteMsr64 (MSR_CORE_P5_MC_TYPE, Msr);
62 @note MSR_CORE_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
64 #define MSR_CORE_P5_MC_TYPE 0x00000001
68 Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
69 processor features; (R) indicates current processor configuration.
71 @param ECX MSR_CORE_EBL_CR_POWERON (0x0000002A)
72 @param EAX Lower 32-bits of MSR value.
73 Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
74 @param EDX Upper 32-bits of MSR value.
75 Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
79 MSR_CORE_EBL_CR_POWERON_REGISTER Msr;
81 Msr.Uint64 = AsmReadMsr64 (MSR_CORE_EBL_CR_POWERON);
82 AsmWriteMsr64 (MSR_CORE_EBL_CR_POWERON, Msr.Uint64);
84 @note MSR_CORE_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
86 #define MSR_CORE_EBL_CR_POWERON 0x0000002A
89 MSR information returned for MSR index #MSR_CORE_EBL_CR_POWERON
93 /// Individual bit fields
98 /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
99 /// Note: Not all processor implements R/W.
101 UINT32 DataErrorCheckingEnable
:1;
103 /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
104 /// Note: Not all processor implements R/W.
106 UINT32 ResponseErrorCheckingEnable
:1;
108 /// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
109 /// all processor implements R/W.
111 UINT32 MCERR_DriveEnable
:1;
113 /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:
114 /// Not all processor implements R/W.
116 UINT32 AddressParityEnable
:1;
119 /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
120 /// all processor implements R/W.
122 UINT32 BINIT_DriverEnable
:1;
124 /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
126 UINT32 OutputTriStateEnable
:1;
128 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
130 UINT32 ExecuteBIST
:1;
132 /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
134 UINT32 MCERR_ObservationEnabled
:1;
137 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
139 UINT32 BINIT_ObservationEnabled
:1;
142 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
144 UINT32 ResetVector
:1;
147 /// [Bits 17:16] APIC Cluster ID (R/O).
149 UINT32 APICClusterID
:2;
151 /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved.
153 UINT32 SystemBusFrequency
:1;
156 /// [Bits 21:20] Symmetric Arbitration ID (R/O).
158 UINT32 SymmetricArbitrationID
:2;
160 /// [Bits 26:22] Clock Frequency Ratio (R/O).
162 UINT32 ClockFrequencyRatio
:5;
167 /// All bit fields as a 32-bit value
171 /// All bit fields as a 64-bit value
174 } MSR_CORE_EBL_CR_POWERON_REGISTER
;
178 Unique. Last Branch Record n (R/W) One of 8 last branch record registers on
179 the last branch record stack: bits 31-0 hold the 'from' address and bits
180 63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at
181 1C9H - Section 17.13, "Last Branch, Interrupt, and Exception Recording
182 (Pentium M Processors).".
184 @param ECX MSR_CORE_LASTBRANCH_n
185 @param EAX Lower 32-bits of MSR value.
186 @param EDX Upper 32-bits of MSR value.
192 Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);
193 AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);
195 @note MSR_CORE_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
196 MSR_CORE_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
197 MSR_CORE_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
198 MSR_CORE_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
199 MSR_CORE_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.
200 MSR_CORE_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.
201 MSR_CORE_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.
202 MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.
205 #define MSR_CORE_LASTBRANCH_0 0x00000040
206 #define MSR_CORE_LASTBRANCH_1 0x00000041
207 #define MSR_CORE_LASTBRANCH_2 0x00000042
208 #define MSR_CORE_LASTBRANCH_3 0x00000043
209 #define MSR_CORE_LASTBRANCH_4 0x00000044
210 #define MSR_CORE_LASTBRANCH_5 0x00000045
211 #define MSR_CORE_LASTBRANCH_6 0x00000046
212 #define MSR_CORE_LASTBRANCH_7 0x00000047
217 Shared. Scalable Bus Speed (RO) This field indicates the scalable bus
220 @param ECX MSR_CORE_FSB_FREQ (0x000000CD)
221 @param EAX Lower 32-bits of MSR value.
222 Described by the type MSR_CORE_FSB_FREQ_REGISTER.
223 @param EDX Upper 32-bits of MSR value.
224 Described by the type MSR_CORE_FSB_FREQ_REGISTER.
228 MSR_CORE_FSB_FREQ_REGISTER Msr;
230 Msr.Uint64 = AsmReadMsr64 (MSR_CORE_FSB_FREQ);
232 @note MSR_CORE_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
234 #define MSR_CORE_FSB_FREQ 0x000000CD
237 MSR information returned for MSR index #MSR_CORE_FSB_FREQ
241 /// Individual bit fields
245 /// [Bits 2:0] - Scalable Bus Speed
246 /// 101B: 100 MHz (FSB 400)
247 /// 001B: 133 MHz (FSB 533)
248 /// 011B: 167 MHz (FSB 667)
250 /// 133.33 MHz should be utilized if performing calculation with System Bus
251 /// Speed when encoding is 101B. 166.67 MHz should be utilized if
252 /// performing calculation with System Bus Speed when encoding is 001B.
254 UINT32 ScalableBusSpeed
:3;
259 /// All bit fields as a 32-bit value
263 /// All bit fields as a 64-bit value
266 } MSR_CORE_FSB_FREQ_REGISTER
;
272 @param ECX MSR_CORE_BBL_CR_CTL3 (0x0000011E)
273 @param EAX Lower 32-bits of MSR value.
274 Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.
275 @param EDX Upper 32-bits of MSR value.
276 Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.
280 MSR_CORE_BBL_CR_CTL3_REGISTER Msr;
282 Msr.Uint64 = AsmReadMsr64 (MSR_CORE_BBL_CR_CTL3);
283 AsmWriteMsr64 (MSR_CORE_BBL_CR_CTL3, Msr.Uint64);
285 @note MSR_CORE_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
287 #define MSR_CORE_BBL_CR_CTL3 0x0000011E
290 MSR information returned for MSR index #MSR_CORE_BBL_CR_CTL3
294 /// Individual bit fields
298 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
299 /// Indicates if the L2 is hardware-disabled.
301 UINT32 L2HardwareEnabled
:1;
304 /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
305 /// Disabled (default) Until this bit is set the processor will not
306 /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
311 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
313 UINT32 L2NotPresent
:1;
318 /// All bit fields as a 32-bit value
322 /// All bit fields as a 64-bit value
325 } MSR_CORE_BBL_CR_CTL3_REGISTER
;
331 @param ECX MSR_CORE_THERM2_CTL (0x0000019D)
332 @param EAX Lower 32-bits of MSR value.
333 Described by the type MSR_CORE_THERM2_CTL_REGISTER.
334 @param EDX Upper 32-bits of MSR value.
335 Described by the type MSR_CORE_THERM2_CTL_REGISTER.
339 MSR_CORE_THERM2_CTL_REGISTER Msr;
341 Msr.Uint64 = AsmReadMsr64 (MSR_CORE_THERM2_CTL);
342 AsmWriteMsr64 (MSR_CORE_THERM2_CTL, Msr.Uint64);
344 @note MSR_CORE_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
346 #define MSR_CORE_THERM2_CTL 0x0000019D
349 MSR information returned for MSR index #MSR_CORE_THERM2_CTL
353 /// Individual bit fields
358 /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
359 /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
360 /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
361 /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
362 /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
369 /// All bit fields as a 32-bit value
373 /// All bit fields as a 64-bit value
376 } MSR_CORE_THERM2_CTL_REGISTER
;
380 Enable Miscellaneous Processor Features (R/W) Allows a variety of processor
381 functions to be enabled and disabled.
383 @param ECX MSR_CORE_IA32_MISC_ENABLE (0x000001A0)
384 @param EAX Lower 32-bits of MSR value.
385 Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.
386 @param EDX Upper 32-bits of MSR value.
387 Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.
391 MSR_CORE_IA32_MISC_ENABLE_REGISTER Msr;
393 Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_MISC_ENABLE);
394 AsmWriteMsr64 (MSR_CORE_IA32_MISC_ENABLE, Msr.Uint64);
396 @note MSR_CORE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
398 #define MSR_CORE_IA32_MISC_ENABLE 0x000001A0
401 MSR information returned for MSR index #MSR_CORE_IA32_MISC_ENABLE
405 /// Individual bit fields
410 /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
413 UINT32 AutomaticThermalControlCircuit
:1;
416 /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.
418 UINT32 PerformanceMonitoring
:1;
421 /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
422 /// the processor to indicate a pending break event within the processor 0
423 /// = Indicates compatible FERR# signaling behavior This bit must be set
424 /// to 1 to support XAPIC interrupt model usage.
428 /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.
433 /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
434 /// thermal sensor indicates that the die temperature is at the
435 /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
436 /// TM2 will reduce the bus to core ratio and voltage according to the
437 /// value last written to MSR_THERM2_CTL bits 15:0. When this bit is clear
438 /// (0, default), the processor does not change the VID signals or the bus
439 /// to core ratio when the processor enters a thermal managed state. If
440 /// the TM2 feature flag (ECX[8]) is not set to 1 after executing CPUID
441 /// with EAX = 1, then this feature is not supported and BIOS must not
442 /// alter the contents of this bit location. The processor is operating
443 /// out of spec if both this bit and the TM1 bit are set to disabled
449 /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) 1 =
450 /// Enhanced Intel SpeedStep Technology enabled.
455 /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.
461 /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 35-2. Setting this
462 /// bit may cause behavior in software that depends on the availability of
463 /// CPUID leaves greater than 2.
465 UINT32 LimitCpuidMaxval
:1;
469 /// [Bit 34] Shared. XD Bit Disable (R/W) See Table 35-2.
472 UINT32 Reserved11
:29;
475 /// All bit fields as a 64-bit value
478 } MSR_CORE_IA32_MISC_ENABLE_REGISTER
;
482 Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
483 that points to the MSR containing the most recent branch record. See
484 MSR_LASTBRANCH_0_FROM_IP (at 40H).
486 @param ECX MSR_CORE_LASTBRANCH_TOS (0x000001C9)
487 @param EAX Lower 32-bits of MSR value.
488 @param EDX Upper 32-bits of MSR value.
494 Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_TOS);
495 AsmWriteMsr64 (MSR_CORE_LASTBRANCH_TOS, Msr);
497 @note MSR_CORE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
499 #define MSR_CORE_LASTBRANCH_TOS 0x000001C9
503 Unique. Last Exception Record From Linear IP (R) Contains a pointer to the
504 last branch instruction that the processor executed prior to the last
505 exception that was generated or the last interrupt that was handled.
507 @param ECX MSR_CORE_LER_FROM_LIP (0x000001DD)
508 @param EAX Lower 32-bits of MSR value.
509 @param EDX Upper 32-bits of MSR value.
515 Msr = AsmReadMsr64 (MSR_CORE_LER_FROM_LIP);
517 @note MSR_CORE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
519 #define MSR_CORE_LER_FROM_LIP 0x000001DD
523 Unique. Last Exception Record To Linear IP (R) This area contains a pointer
524 to the target of the last branch instruction that the processor executed
525 prior to the last exception that was generated or the last interrupt that
528 @param ECX MSR_CORE_LER_TO_LIP (0x000001DE)
529 @param EAX Lower 32-bits of MSR value.
530 @param EDX Upper 32-bits of MSR value.
536 Msr = AsmReadMsr64 (MSR_CORE_LER_TO_LIP);
538 @note MSR_CORE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
540 #define MSR_CORE_LER_TO_LIP 0x000001DE
546 @param ECX MSR_CORE_ROB_CR_BKUPTMPDR6 (0x000001E0)
547 @param EAX Lower 32-bits of MSR value.
548 Described by the type MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER.
549 @param EDX Upper 32-bits of MSR value.
550 Described by the type MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER.
554 MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER Msr;
556 Msr.Uint64 = AsmReadMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6);
557 AsmWriteMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6, Msr.Uint64);
559 @note MSR_CORE_ROB_CR_BKUPTMPDR6 is defined as ROB_CR_BKUPTMPDR6 in SDM.
561 #define MSR_CORE_ROB_CR_BKUPTMPDR6 0x000001E0
564 MSR information returned for MSR index #MSR_CORE_ROB_CR_BKUPTMPDR6
568 /// Individual bit fields
573 /// [Bit 2] Fast Strings Enable bit. (Default, enabled).
575 UINT32 FastStrings
:1;
580 /// All bit fields as a 32-bit value
584 /// All bit fields as a 64-bit value
587 } MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER
;
593 @param ECX MSR_CORE_MTRRPHYSBASEn
594 @param EAX Lower 32-bits of MSR value.
595 @param EDX Upper 32-bits of MSR value.
601 Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);
602 AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);
604 @note MSR_CORE_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.
605 MSR_CORE_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.
606 MSR_CORE_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.
607 MSR_CORE_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.
608 MSR_CORE_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.
609 MSR_CORE_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.
610 MSR_CORE_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.
611 MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.
614 #define MSR_CORE_MTRRPHYSBASE0 0x00000200
615 #define MSR_CORE_MTRRPHYSBASE1 0x00000202
616 #define MSR_CORE_MTRRPHYSBASE2 0x00000204
617 #define MSR_CORE_MTRRPHYSBASE3 0x00000206
618 #define MSR_CORE_MTRRPHYSBASE4 0x00000208
619 #define MSR_CORE_MTRRPHYSBASE5 0x0000020A
620 #define MSR_CORE_MTRRPHYSMASK6 0x0000020D
621 #define MSR_CORE_MTRRPHYSMASK7 0x0000020F
628 @param ECX MSR_CORE_MTRRPHYSMASKn (0x00000201)
629 @param EAX Lower 32-bits of MSR value.
630 @param EDX Upper 32-bits of MSR value.
636 Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);
637 AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);
639 @note MSR_CORE_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM.
640 MSR_CORE_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM.
641 MSR_CORE_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM.
642 MSR_CORE_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM.
643 MSR_CORE_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM.
644 MSR_CORE_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM.
645 MSR_CORE_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM.
646 MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.
649 #define MSR_CORE_MTRRPHYSMASK0 0x00000201
650 #define MSR_CORE_MTRRPHYSMASK1 0x00000203
651 #define MSR_CORE_MTRRPHYSMASK2 0x00000205
652 #define MSR_CORE_MTRRPHYSMASK3 0x00000207
653 #define MSR_CORE_MTRRPHYSMASK4 0x00000209
654 #define MSR_CORE_MTRRPHYSMASK5 0x0000020B
655 #define MSR_CORE_MTRRPHYSBASE6 0x0000020C
656 #define MSR_CORE_MTRRPHYSBASE7 0x0000020E
663 @param ECX MSR_CORE_MTRRFIX64K_00000 (0x00000250)
664 @param EAX Lower 32-bits of MSR value.
665 @param EDX Upper 32-bits of MSR value.
671 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX64K_00000);
672 AsmWriteMsr64 (MSR_CORE_MTRRFIX64K_00000, Msr);
674 @note MSR_CORE_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.
676 #define MSR_CORE_MTRRFIX64K_00000 0x00000250
682 @param ECX MSR_CORE_MTRRFIX16K_80000 (0x00000258)
683 @param EAX Lower 32-bits of MSR value.
684 @param EDX Upper 32-bits of MSR value.
690 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_80000);
691 AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_80000, Msr);
693 @note MSR_CORE_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.
695 #define MSR_CORE_MTRRFIX16K_80000 0x00000258
701 @param ECX MSR_CORE_MTRRFIX16K_A0000 (0x00000259)
702 @param EAX Lower 32-bits of MSR value.
703 @param EDX Upper 32-bits of MSR value.
709 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_A0000);
710 AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_A0000, Msr);
712 @note MSR_CORE_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.
714 #define MSR_CORE_MTRRFIX16K_A0000 0x00000259
720 @param ECX MSR_CORE_MTRRFIX4K_C0000 (0x00000268)
721 @param EAX Lower 32-bits of MSR value.
722 @param EDX Upper 32-bits of MSR value.
728 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C0000);
729 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C0000, Msr);
731 @note MSR_CORE_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.
733 #define MSR_CORE_MTRRFIX4K_C0000 0x00000268
739 @param ECX MSR_CORE_MTRRFIX4K_C8000 (0x00000269)
740 @param EAX Lower 32-bits of MSR value.
741 @param EDX Upper 32-bits of MSR value.
747 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C8000);
748 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C8000, Msr);
750 @note MSR_CORE_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.
752 #define MSR_CORE_MTRRFIX4K_C8000 0x00000269
758 @param ECX MSR_CORE_MTRRFIX4K_D0000 (0x0000026A)
759 @param EAX Lower 32-bits of MSR value.
760 @param EDX Upper 32-bits of MSR value.
766 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D0000);
767 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D0000, Msr);
769 @note MSR_CORE_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.
771 #define MSR_CORE_MTRRFIX4K_D0000 0x0000026A
777 @param ECX MSR_CORE_MTRRFIX4K_D8000 (0x0000026B)
778 @param EAX Lower 32-bits of MSR value.
779 @param EDX Upper 32-bits of MSR value.
785 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D8000);
786 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D8000, Msr);
788 @note MSR_CORE_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.
790 #define MSR_CORE_MTRRFIX4K_D8000 0x0000026B
796 @param ECX MSR_CORE_MTRRFIX4K_E0000 (0x0000026C)
797 @param EAX Lower 32-bits of MSR value.
798 @param EDX Upper 32-bits of MSR value.
804 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E0000);
805 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E0000, Msr);
807 @note MSR_CORE_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.
809 #define MSR_CORE_MTRRFIX4K_E0000 0x0000026C
815 @param ECX MSR_CORE_MTRRFIX4K_E8000 (0x0000026D)
816 @param EAX Lower 32-bits of MSR value.
817 @param EDX Upper 32-bits of MSR value.
823 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E8000);
824 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E8000, Msr);
826 @note MSR_CORE_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.
828 #define MSR_CORE_MTRRFIX4K_E8000 0x0000026D
834 @param ECX MSR_CORE_MTRRFIX4K_F0000 (0x0000026E)
835 @param EAX Lower 32-bits of MSR value.
836 @param EDX Upper 32-bits of MSR value.
842 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F0000);
843 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F0000, Msr);
845 @note MSR_CORE_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.
847 #define MSR_CORE_MTRRFIX4K_F0000 0x0000026E
853 @param ECX MSR_CORE_MTRRFIX4K_F8000 (0x0000026F)
854 @param EAX Lower 32-bits of MSR value.
855 @param EDX Upper 32-bits of MSR value.
861 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F8000);
862 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F8000, Msr);
864 @note MSR_CORE_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.
866 #define MSR_CORE_MTRRFIX4K_F8000 0x0000026F
870 Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
872 @param ECX MSR_CORE_MC4_CTL (0x0000040C)
873 @param EAX Lower 32-bits of MSR value.
874 @param EDX Upper 32-bits of MSR value.
880 Msr = AsmReadMsr64 (MSR_CORE_MC4_CTL);
881 AsmWriteMsr64 (MSR_CORE_MC4_CTL, Msr);
883 @note MSR_CORE_MC4_CTL is defined as MSR_MC4_CTL in SDM.
885 #define MSR_CORE_MC4_CTL 0x0000040C
889 Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
891 @param ECX MSR_CORE_MC4_STATUS (0x0000040D)
892 @param EAX Lower 32-bits of MSR value.
893 @param EDX Upper 32-bits of MSR value.
899 Msr = AsmReadMsr64 (MSR_CORE_MC4_STATUS);
900 AsmWriteMsr64 (MSR_CORE_MC4_STATUS, Msr);
902 @note MSR_CORE_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
904 #define MSR_CORE_MC4_STATUS 0x0000040D
908 Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR
909 register is either not implemented or contains no address if the ADDRV flag
910 in the MSR_MC4_STATUS register is clear. When not implemented in the
911 processor, all reads and writes to this MSR will cause a general-protection
914 @param ECX MSR_CORE_MC4_ADDR (0x0000040E)
915 @param EAX Lower 32-bits of MSR value.
916 @param EDX Upper 32-bits of MSR value.
922 Msr = AsmReadMsr64 (MSR_CORE_MC4_ADDR);
923 AsmWriteMsr64 (MSR_CORE_MC4_ADDR, Msr);
925 @note MSR_CORE_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
927 #define MSR_CORE_MC4_ADDR 0x0000040E
931 Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR
932 register is either not implemented or contains no address if the ADDRV flag
933 in the MSR_MC3_STATUS register is clear. When not implemented in the
934 processor, all reads and writes to this MSR will cause a general-protection
937 @param ECX MSR_CORE_MC3_ADDR (0x00000412)
938 @param EAX Lower 32-bits of MSR value.
939 @param EDX Upper 32-bits of MSR value.
945 Msr = AsmReadMsr64 (MSR_CORE_MC3_ADDR);
946 AsmWriteMsr64 (MSR_CORE_MC3_ADDR, Msr);
948 @note MSR_CORE_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
950 #define MSR_CORE_MC3_ADDR 0x00000412
956 @param ECX MSR_CORE_MC3_MISC (0x00000413)
957 @param EAX Lower 32-bits of MSR value.
958 @param EDX Upper 32-bits of MSR value.
964 Msr = AsmReadMsr64 (MSR_CORE_MC3_MISC);
965 AsmWriteMsr64 (MSR_CORE_MC3_MISC, Msr);
967 @note MSR_CORE_MC3_MISC is defined as MSR_MC3_MISC in SDM.
969 #define MSR_CORE_MC3_MISC 0x00000413
975 @param ECX MSR_CORE_MC5_CTL (0x00000414)
976 @param EAX Lower 32-bits of MSR value.
977 @param EDX Upper 32-bits of MSR value.
983 Msr = AsmReadMsr64 (MSR_CORE_MC5_CTL);
984 AsmWriteMsr64 (MSR_CORE_MC5_CTL, Msr);
986 @note MSR_CORE_MC5_CTL is defined as MSR_MC5_CTL in SDM.
988 #define MSR_CORE_MC5_CTL 0x00000414
994 @param ECX MSR_CORE_MC5_STATUS (0x00000415)
995 @param EAX Lower 32-bits of MSR value.
996 @param EDX Upper 32-bits of MSR value.
1002 Msr = AsmReadMsr64 (MSR_CORE_MC5_STATUS);
1003 AsmWriteMsr64 (MSR_CORE_MC5_STATUS, Msr);
1005 @note MSR_CORE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
1007 #define MSR_CORE_MC5_STATUS 0x00000415
1013 @param ECX MSR_CORE_MC5_ADDR (0x00000416)
1014 @param EAX Lower 32-bits of MSR value.
1015 @param EDX Upper 32-bits of MSR value.
1017 <b>Example usage</b>
1021 Msr = AsmReadMsr64 (MSR_CORE_MC5_ADDR);
1022 AsmWriteMsr64 (MSR_CORE_MC5_ADDR, Msr);
1024 @note MSR_CORE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
1026 #define MSR_CORE_MC5_ADDR 0x00000416
1032 @param ECX MSR_CORE_MC5_MISC (0x00000417)
1033 @param EAX Lower 32-bits of MSR value.
1034 @param EDX Upper 32-bits of MSR value.
1036 <b>Example usage</b>
1040 Msr = AsmReadMsr64 (MSR_CORE_MC5_MISC);
1041 AsmWriteMsr64 (MSR_CORE_MC5_MISC, Msr);
1043 @note MSR_CORE_MC5_MISC is defined as MSR_MC5_MISC in SDM.
1045 #define MSR_CORE_MC5_MISC 0x00000417
1049 Unique. See Table 35-2.
1051 @param ECX MSR_CORE_IA32_EFER (0xC0000080)
1052 @param EAX Lower 32-bits of MSR value.
1053 Described by the type MSR_CORE_IA32_EFER_REGISTER.
1054 @param EDX Upper 32-bits of MSR value.
1055 Described by the type MSR_CORE_IA32_EFER_REGISTER.
1057 <b>Example usage</b>
1059 MSR_CORE_IA32_EFER_REGISTER Msr;
1061 Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);
1062 AsmWriteMsr64 (MSR_CORE_IA32_EFER, Msr.Uint64);
1064 @note MSR_CORE_IA32_EFER is defined as IA32_EFER in SDM.
1066 #define MSR_CORE_IA32_EFER 0xC0000080
1069 MSR information returned for MSR index #MSR_CORE_IA32_EFER
1073 /// Individual bit fields
1076 UINT32 Reserved1
:11;
1078 /// [Bit 11] Execute Disable Bit Enable.
1081 UINT32 Reserved2
:20;
1082 UINT32 Reserved3
:32;
1085 /// All bit fields as a 32-bit value
1089 /// All bit fields as a 64-bit value
1092 } MSR_CORE_IA32_EFER_REGISTER
;