2 MSR Definitions for Intel Core Solo and Intel Core Duo Processors.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
20 May 2018, Volume 4: Model-Specific-Registers (MSR)
24 #ifndef __CORE_MSR_H__
25 #define __CORE_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Is Intel Core Solo and Intel Core Duo Processors?
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
38 #define IS_CORE_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
41 DisplayModel == 0x0E \
46 Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.
48 @param ECX MSR_CORE_P5_MC_ADDR (0x00000000)
49 @param EAX Lower 32-bits of MSR value.
50 @param EDX Upper 32-bits of MSR value.
56 Msr = AsmReadMsr64 (MSR_CORE_P5_MC_ADDR);
57 AsmWriteMsr64 (MSR_CORE_P5_MC_ADDR, Msr);
59 @note MSR_CORE_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
61 #define MSR_CORE_P5_MC_ADDR 0x00000000
65 Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.
67 @param ECX MSR_CORE_P5_MC_TYPE (0x00000001)
68 @param EAX Lower 32-bits of MSR value.
69 @param EDX Upper 32-bits of MSR value.
75 Msr = AsmReadMsr64 (MSR_CORE_P5_MC_TYPE);
76 AsmWriteMsr64 (MSR_CORE_P5_MC_TYPE, Msr);
78 @note MSR_CORE_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
80 #define MSR_CORE_P5_MC_TYPE 0x00000001
84 Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
85 processor features; (R) indicates current processor configuration.
87 @param ECX MSR_CORE_EBL_CR_POWERON (0x0000002A)
88 @param EAX Lower 32-bits of MSR value.
89 Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
90 @param EDX Upper 32-bits of MSR value.
91 Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
95 MSR_CORE_EBL_CR_POWERON_REGISTER Msr;
97 Msr.Uint64 = AsmReadMsr64 (MSR_CORE_EBL_CR_POWERON);
98 AsmWriteMsr64 (MSR_CORE_EBL_CR_POWERON, Msr.Uint64);
100 @note MSR_CORE_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
102 #define MSR_CORE_EBL_CR_POWERON 0x0000002A
105 MSR information returned for MSR index #MSR_CORE_EBL_CR_POWERON
109 /// Individual bit fields
114 /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
115 /// Note: Not all processor implements R/W.
117 UINT32 DataErrorCheckingEnable
:1;
119 /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
120 /// Note: Not all processor implements R/W.
122 UINT32 ResponseErrorCheckingEnable
:1;
124 /// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
125 /// all processor implements R/W.
127 UINT32 MCERR_DriveEnable
:1;
129 /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:
130 /// Not all processor implements R/W.
132 UINT32 AddressParityEnable
:1;
135 /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
136 /// all processor implements R/W.
138 UINT32 BINIT_DriverEnable
:1;
140 /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
142 UINT32 OutputTriStateEnable
:1;
144 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
146 UINT32 ExecuteBIST
:1;
148 /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
150 UINT32 MCERR_ObservationEnabled
:1;
153 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
155 UINT32 BINIT_ObservationEnabled
:1;
158 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
160 UINT32 ResetVector
:1;
163 /// [Bits 17:16] APIC Cluster ID (R/O).
165 UINT32 APICClusterID
:2;
167 /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved.
169 UINT32 SystemBusFrequency
:1;
172 /// [Bits 21:20] Symmetric Arbitration ID (R/O).
174 UINT32 SymmetricArbitrationID
:2;
176 /// [Bits 26:22] Clock Frequency Ratio (R/O).
178 UINT32 ClockFrequencyRatio
:5;
183 /// All bit fields as a 32-bit value
187 /// All bit fields as a 64-bit value
190 } MSR_CORE_EBL_CR_POWERON_REGISTER
;
194 Unique. Last Branch Record n (R/W) One of 8 last branch record registers on
195 the last branch record stack: bits 31-0 hold the 'from' address and bits
196 63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at
197 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording
198 (Pentium M Processors).".
200 @param ECX MSR_CORE_LASTBRANCH_n
201 @param EAX Lower 32-bits of MSR value.
202 @param EDX Upper 32-bits of MSR value.
208 Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);
209 AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);
211 @note MSR_CORE_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
212 MSR_CORE_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
213 MSR_CORE_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
214 MSR_CORE_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
215 MSR_CORE_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.
216 MSR_CORE_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.
217 MSR_CORE_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.
218 MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.
221 #define MSR_CORE_LASTBRANCH_0 0x00000040
222 #define MSR_CORE_LASTBRANCH_1 0x00000041
223 #define MSR_CORE_LASTBRANCH_2 0x00000042
224 #define MSR_CORE_LASTBRANCH_3 0x00000043
225 #define MSR_CORE_LASTBRANCH_4 0x00000044
226 #define MSR_CORE_LASTBRANCH_5 0x00000045
227 #define MSR_CORE_LASTBRANCH_6 0x00000046
228 #define MSR_CORE_LASTBRANCH_7 0x00000047
233 Shared. Scalable Bus Speed (RO) This field indicates the scalable bus
236 @param ECX MSR_CORE_FSB_FREQ (0x000000CD)
237 @param EAX Lower 32-bits of MSR value.
238 Described by the type MSR_CORE_FSB_FREQ_REGISTER.
239 @param EDX Upper 32-bits of MSR value.
240 Described by the type MSR_CORE_FSB_FREQ_REGISTER.
244 MSR_CORE_FSB_FREQ_REGISTER Msr;
246 Msr.Uint64 = AsmReadMsr64 (MSR_CORE_FSB_FREQ);
248 @note MSR_CORE_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
250 #define MSR_CORE_FSB_FREQ 0x000000CD
253 MSR information returned for MSR index #MSR_CORE_FSB_FREQ
257 /// Individual bit fields
261 /// [Bits 2:0] - Scalable Bus Speed
262 /// 101B: 100 MHz (FSB 400)
263 /// 001B: 133 MHz (FSB 533)
264 /// 011B: 167 MHz (FSB 667)
266 /// 133.33 MHz should be utilized if performing calculation with System Bus
267 /// Speed when encoding is 101B. 166.67 MHz should be utilized if
268 /// performing calculation with System Bus Speed when encoding is 001B.
270 UINT32 ScalableBusSpeed
:3;
275 /// All bit fields as a 32-bit value
279 /// All bit fields as a 64-bit value
282 } MSR_CORE_FSB_FREQ_REGISTER
;
288 @param ECX MSR_CORE_BBL_CR_CTL3 (0x0000011E)
289 @param EAX Lower 32-bits of MSR value.
290 Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.
291 @param EDX Upper 32-bits of MSR value.
292 Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.
296 MSR_CORE_BBL_CR_CTL3_REGISTER Msr;
298 Msr.Uint64 = AsmReadMsr64 (MSR_CORE_BBL_CR_CTL3);
299 AsmWriteMsr64 (MSR_CORE_BBL_CR_CTL3, Msr.Uint64);
301 @note MSR_CORE_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
303 #define MSR_CORE_BBL_CR_CTL3 0x0000011E
306 MSR information returned for MSR index #MSR_CORE_BBL_CR_CTL3
310 /// Individual bit fields
314 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
315 /// Indicates if the L2 is hardware-disabled.
317 UINT32 L2HardwareEnabled
:1;
320 /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
321 /// Disabled (default) Until this bit is set the processor will not
322 /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
327 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
329 UINT32 L2NotPresent
:1;
334 /// All bit fields as a 32-bit value
338 /// All bit fields as a 64-bit value
341 } MSR_CORE_BBL_CR_CTL3_REGISTER
;
347 @param ECX MSR_CORE_THERM2_CTL (0x0000019D)
348 @param EAX Lower 32-bits of MSR value.
349 Described by the type MSR_CORE_THERM2_CTL_REGISTER.
350 @param EDX Upper 32-bits of MSR value.
351 Described by the type MSR_CORE_THERM2_CTL_REGISTER.
355 MSR_CORE_THERM2_CTL_REGISTER Msr;
357 Msr.Uint64 = AsmReadMsr64 (MSR_CORE_THERM2_CTL);
358 AsmWriteMsr64 (MSR_CORE_THERM2_CTL, Msr.Uint64);
360 @note MSR_CORE_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
362 #define MSR_CORE_THERM2_CTL 0x0000019D
365 MSR information returned for MSR index #MSR_CORE_THERM2_CTL
369 /// Individual bit fields
374 /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
375 /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
376 /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
377 /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
378 /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
385 /// All bit fields as a 32-bit value
389 /// All bit fields as a 64-bit value
392 } MSR_CORE_THERM2_CTL_REGISTER
;
396 Enable Miscellaneous Processor Features (R/W) Allows a variety of processor
397 functions to be enabled and disabled.
399 @param ECX MSR_CORE_IA32_MISC_ENABLE (0x000001A0)
400 @param EAX Lower 32-bits of MSR value.
401 Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.
402 @param EDX Upper 32-bits of MSR value.
403 Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.
407 MSR_CORE_IA32_MISC_ENABLE_REGISTER Msr;
409 Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_MISC_ENABLE);
410 AsmWriteMsr64 (MSR_CORE_IA32_MISC_ENABLE, Msr.Uint64);
412 @note MSR_CORE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
414 #define MSR_CORE_IA32_MISC_ENABLE 0x000001A0
417 MSR information returned for MSR index #MSR_CORE_IA32_MISC_ENABLE
421 /// Individual bit fields
426 /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
429 UINT32 AutomaticThermalControlCircuit
:1;
432 /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
434 UINT32 PerformanceMonitoring
:1;
437 /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
438 /// the processor to indicate a pending break event within the processor 0
439 /// = Indicates compatible FERR# signaling behavior This bit must be set
440 /// to 1 to support XAPIC interrupt model usage.
444 /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
449 /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
450 /// thermal sensor indicates that the die temperature is at the
451 /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
452 /// TM2 will reduce the bus to core ratio and voltage according to the
453 /// value last written to MSR_THERM2_CTL bits 15:0. When this bit is clear
454 /// (0, default), the processor does not change the VID signals or the bus
455 /// to core ratio when the processor enters a thermal managed state. If
456 /// the TM2 feature flag (ECX[8]) is not set to 1 after executing CPUID
457 /// with EAX = 1, then this feature is not supported and BIOS must not
458 /// alter the contents of this bit location. The processor is operating
459 /// out of spec if both this bit and the TM1 bit are set to disabled
465 /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) 1 =
466 /// Enhanced Intel SpeedStep Technology enabled.
471 /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
477 /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2. Setting this
478 /// bit may cause behavior in software that depends on the availability of
479 /// CPUID leaves greater than 2.
481 UINT32 LimitCpuidMaxval
:1;
485 /// [Bit 34] Shared. XD Bit Disable (R/W) See Table 2-2.
488 UINT32 Reserved11
:29;
491 /// All bit fields as a 64-bit value
494 } MSR_CORE_IA32_MISC_ENABLE_REGISTER
;
498 Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
499 that points to the MSR containing the most recent branch record. See
500 MSR_LASTBRANCH_0_FROM_IP (at 40H).
502 @param ECX MSR_CORE_LASTBRANCH_TOS (0x000001C9)
503 @param EAX Lower 32-bits of MSR value.
504 @param EDX Upper 32-bits of MSR value.
510 Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_TOS);
511 AsmWriteMsr64 (MSR_CORE_LASTBRANCH_TOS, Msr);
513 @note MSR_CORE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
515 #define MSR_CORE_LASTBRANCH_TOS 0x000001C9
519 Unique. Last Exception Record From Linear IP (R) Contains a pointer to the
520 last branch instruction that the processor executed prior to the last
521 exception that was generated or the last interrupt that was handled.
523 @param ECX MSR_CORE_LER_FROM_LIP (0x000001DD)
524 @param EAX Lower 32-bits of MSR value.
525 @param EDX Upper 32-bits of MSR value.
531 Msr = AsmReadMsr64 (MSR_CORE_LER_FROM_LIP);
533 @note MSR_CORE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
535 #define MSR_CORE_LER_FROM_LIP 0x000001DD
539 Unique. Last Exception Record To Linear IP (R) This area contains a pointer
540 to the target of the last branch instruction that the processor executed
541 prior to the last exception that was generated or the last interrupt that
544 @param ECX MSR_CORE_LER_TO_LIP (0x000001DE)
545 @param EAX Lower 32-bits of MSR value.
546 @param EDX Upper 32-bits of MSR value.
552 Msr = AsmReadMsr64 (MSR_CORE_LER_TO_LIP);
554 @note MSR_CORE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
556 #define MSR_CORE_LER_TO_LIP 0x000001DE
561 @param ECX MSR_CORE_MTRRPHYSBASEn
562 @param EAX Lower 32-bits of MSR value.
563 @param EDX Upper 32-bits of MSR value.
569 Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);
570 AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);
572 @note MSR_CORE_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.
573 MSR_CORE_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.
574 MSR_CORE_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.
575 MSR_CORE_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.
576 MSR_CORE_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.
577 MSR_CORE_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.
578 MSR_CORE_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.
579 MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.
582 #define MSR_CORE_MTRRPHYSBASE0 0x00000200
583 #define MSR_CORE_MTRRPHYSBASE1 0x00000202
584 #define MSR_CORE_MTRRPHYSBASE2 0x00000204
585 #define MSR_CORE_MTRRPHYSBASE3 0x00000206
586 #define MSR_CORE_MTRRPHYSBASE4 0x00000208
587 #define MSR_CORE_MTRRPHYSBASE5 0x0000020A
588 #define MSR_CORE_MTRRPHYSMASK6 0x0000020D
589 #define MSR_CORE_MTRRPHYSMASK7 0x0000020F
596 @param ECX MSR_CORE_MTRRPHYSMASKn (0x00000201)
597 @param EAX Lower 32-bits of MSR value.
598 @param EDX Upper 32-bits of MSR value.
604 Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);
605 AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);
607 @note MSR_CORE_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM.
608 MSR_CORE_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM.
609 MSR_CORE_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM.
610 MSR_CORE_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM.
611 MSR_CORE_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM.
612 MSR_CORE_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM.
613 MSR_CORE_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM.
614 MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.
617 #define MSR_CORE_MTRRPHYSMASK0 0x00000201
618 #define MSR_CORE_MTRRPHYSMASK1 0x00000203
619 #define MSR_CORE_MTRRPHYSMASK2 0x00000205
620 #define MSR_CORE_MTRRPHYSMASK3 0x00000207
621 #define MSR_CORE_MTRRPHYSMASK4 0x00000209
622 #define MSR_CORE_MTRRPHYSMASK5 0x0000020B
623 #define MSR_CORE_MTRRPHYSBASE6 0x0000020C
624 #define MSR_CORE_MTRRPHYSBASE7 0x0000020E
631 @param ECX MSR_CORE_MTRRFIX64K_00000 (0x00000250)
632 @param EAX Lower 32-bits of MSR value.
633 @param EDX Upper 32-bits of MSR value.
639 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX64K_00000);
640 AsmWriteMsr64 (MSR_CORE_MTRRFIX64K_00000, Msr);
642 @note MSR_CORE_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.
644 #define MSR_CORE_MTRRFIX64K_00000 0x00000250
650 @param ECX MSR_CORE_MTRRFIX16K_80000 (0x00000258)
651 @param EAX Lower 32-bits of MSR value.
652 @param EDX Upper 32-bits of MSR value.
658 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_80000);
659 AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_80000, Msr);
661 @note MSR_CORE_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.
663 #define MSR_CORE_MTRRFIX16K_80000 0x00000258
669 @param ECX MSR_CORE_MTRRFIX16K_A0000 (0x00000259)
670 @param EAX Lower 32-bits of MSR value.
671 @param EDX Upper 32-bits of MSR value.
677 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_A0000);
678 AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_A0000, Msr);
680 @note MSR_CORE_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.
682 #define MSR_CORE_MTRRFIX16K_A0000 0x00000259
688 @param ECX MSR_CORE_MTRRFIX4K_C0000 (0x00000268)
689 @param EAX Lower 32-bits of MSR value.
690 @param EDX Upper 32-bits of MSR value.
696 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C0000);
697 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C0000, Msr);
699 @note MSR_CORE_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.
701 #define MSR_CORE_MTRRFIX4K_C0000 0x00000268
707 @param ECX MSR_CORE_MTRRFIX4K_C8000 (0x00000269)
708 @param EAX Lower 32-bits of MSR value.
709 @param EDX Upper 32-bits of MSR value.
715 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C8000);
716 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C8000, Msr);
718 @note MSR_CORE_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.
720 #define MSR_CORE_MTRRFIX4K_C8000 0x00000269
726 @param ECX MSR_CORE_MTRRFIX4K_D0000 (0x0000026A)
727 @param EAX Lower 32-bits of MSR value.
728 @param EDX Upper 32-bits of MSR value.
734 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D0000);
735 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D0000, Msr);
737 @note MSR_CORE_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.
739 #define MSR_CORE_MTRRFIX4K_D0000 0x0000026A
745 @param ECX MSR_CORE_MTRRFIX4K_D8000 (0x0000026B)
746 @param EAX Lower 32-bits of MSR value.
747 @param EDX Upper 32-bits of MSR value.
753 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D8000);
754 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D8000, Msr);
756 @note MSR_CORE_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.
758 #define MSR_CORE_MTRRFIX4K_D8000 0x0000026B
764 @param ECX MSR_CORE_MTRRFIX4K_E0000 (0x0000026C)
765 @param EAX Lower 32-bits of MSR value.
766 @param EDX Upper 32-bits of MSR value.
772 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E0000);
773 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E0000, Msr);
775 @note MSR_CORE_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.
777 #define MSR_CORE_MTRRFIX4K_E0000 0x0000026C
783 @param ECX MSR_CORE_MTRRFIX4K_E8000 (0x0000026D)
784 @param EAX Lower 32-bits of MSR value.
785 @param EDX Upper 32-bits of MSR value.
791 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E8000);
792 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E8000, Msr);
794 @note MSR_CORE_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.
796 #define MSR_CORE_MTRRFIX4K_E8000 0x0000026D
802 @param ECX MSR_CORE_MTRRFIX4K_F0000 (0x0000026E)
803 @param EAX Lower 32-bits of MSR value.
804 @param EDX Upper 32-bits of MSR value.
810 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F0000);
811 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F0000, Msr);
813 @note MSR_CORE_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.
815 #define MSR_CORE_MTRRFIX4K_F0000 0x0000026E
821 @param ECX MSR_CORE_MTRRFIX4K_F8000 (0x0000026F)
822 @param EAX Lower 32-bits of MSR value.
823 @param EDX Upper 32-bits of MSR value.
829 Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F8000);
830 AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F8000, Msr);
832 @note MSR_CORE_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.
834 #define MSR_CORE_MTRRFIX4K_F8000 0x0000026F
838 Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
840 @param ECX MSR_CORE_MC4_CTL (0x0000040C)
841 @param EAX Lower 32-bits of MSR value.
842 @param EDX Upper 32-bits of MSR value.
848 Msr = AsmReadMsr64 (MSR_CORE_MC4_CTL);
849 AsmWriteMsr64 (MSR_CORE_MC4_CTL, Msr);
851 @note MSR_CORE_MC4_CTL is defined as MSR_MC4_CTL in SDM.
853 #define MSR_CORE_MC4_CTL 0x0000040C
857 Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
859 @param ECX MSR_CORE_MC4_STATUS (0x0000040D)
860 @param EAX Lower 32-bits of MSR value.
861 @param EDX Upper 32-bits of MSR value.
867 Msr = AsmReadMsr64 (MSR_CORE_MC4_STATUS);
868 AsmWriteMsr64 (MSR_CORE_MC4_STATUS, Msr);
870 @note MSR_CORE_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
872 #define MSR_CORE_MC4_STATUS 0x0000040D
876 Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR
877 register is either not implemented or contains no address if the ADDRV flag
878 in the MSR_MC4_STATUS register is clear. When not implemented in the
879 processor, all reads and writes to this MSR will cause a general-protection
882 @param ECX MSR_CORE_MC4_ADDR (0x0000040E)
883 @param EAX Lower 32-bits of MSR value.
884 @param EDX Upper 32-bits of MSR value.
890 Msr = AsmReadMsr64 (MSR_CORE_MC4_ADDR);
891 AsmWriteMsr64 (MSR_CORE_MC4_ADDR, Msr);
893 @note MSR_CORE_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
895 #define MSR_CORE_MC4_ADDR 0x0000040E
899 Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR
900 register is either not implemented or contains no address if the ADDRV flag
901 in the MSR_MC3_STATUS register is clear. When not implemented in the
902 processor, all reads and writes to this MSR will cause a general-protection
905 @param ECX MSR_CORE_MC3_ADDR (0x00000412)
906 @param EAX Lower 32-bits of MSR value.
907 @param EDX Upper 32-bits of MSR value.
913 Msr = AsmReadMsr64 (MSR_CORE_MC3_ADDR);
914 AsmWriteMsr64 (MSR_CORE_MC3_ADDR, Msr);
916 @note MSR_CORE_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
918 #define MSR_CORE_MC3_ADDR 0x00000412
924 @param ECX MSR_CORE_MC3_MISC (0x00000413)
925 @param EAX Lower 32-bits of MSR value.
926 @param EDX Upper 32-bits of MSR value.
932 Msr = AsmReadMsr64 (MSR_CORE_MC3_MISC);
933 AsmWriteMsr64 (MSR_CORE_MC3_MISC, Msr);
935 @note MSR_CORE_MC3_MISC is defined as MSR_MC3_MISC in SDM.
937 #define MSR_CORE_MC3_MISC 0x00000413
943 @param ECX MSR_CORE_MC5_CTL (0x00000414)
944 @param EAX Lower 32-bits of MSR value.
945 @param EDX Upper 32-bits of MSR value.
951 Msr = AsmReadMsr64 (MSR_CORE_MC5_CTL);
952 AsmWriteMsr64 (MSR_CORE_MC5_CTL, Msr);
954 @note MSR_CORE_MC5_CTL is defined as MSR_MC5_CTL in SDM.
956 #define MSR_CORE_MC5_CTL 0x00000414
962 @param ECX MSR_CORE_MC5_STATUS (0x00000415)
963 @param EAX Lower 32-bits of MSR value.
964 @param EDX Upper 32-bits of MSR value.
970 Msr = AsmReadMsr64 (MSR_CORE_MC5_STATUS);
971 AsmWriteMsr64 (MSR_CORE_MC5_STATUS, Msr);
973 @note MSR_CORE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
975 #define MSR_CORE_MC5_STATUS 0x00000415
981 @param ECX MSR_CORE_MC5_ADDR (0x00000416)
982 @param EAX Lower 32-bits of MSR value.
983 @param EDX Upper 32-bits of MSR value.
989 Msr = AsmReadMsr64 (MSR_CORE_MC5_ADDR);
990 AsmWriteMsr64 (MSR_CORE_MC5_ADDR, Msr);
992 @note MSR_CORE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
994 #define MSR_CORE_MC5_ADDR 0x00000416
1000 @param ECX MSR_CORE_MC5_MISC (0x00000417)
1001 @param EAX Lower 32-bits of MSR value.
1002 @param EDX Upper 32-bits of MSR value.
1004 <b>Example usage</b>
1008 Msr = AsmReadMsr64 (MSR_CORE_MC5_MISC);
1009 AsmWriteMsr64 (MSR_CORE_MC5_MISC, Msr);
1011 @note MSR_CORE_MC5_MISC is defined as MSR_MC5_MISC in SDM.
1013 #define MSR_CORE_MC5_MISC 0x00000417
1017 Unique. See Table 2-2.
1019 @param ECX MSR_CORE_IA32_EFER (0xC0000080)
1020 @param EAX Lower 32-bits of MSR value.
1021 Described by the type MSR_CORE_IA32_EFER_REGISTER.
1022 @param EDX Upper 32-bits of MSR value.
1023 Described by the type MSR_CORE_IA32_EFER_REGISTER.
1025 <b>Example usage</b>
1027 MSR_CORE_IA32_EFER_REGISTER Msr;
1029 Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);
1030 AsmWriteMsr64 (MSR_CORE_IA32_EFER, Msr.Uint64);
1032 @note MSR_CORE_IA32_EFER is defined as IA32_EFER in SDM.
1034 #define MSR_CORE_IA32_EFER 0xC0000080
1037 MSR information returned for MSR index #MSR_CORE_IA32_EFER
1041 /// Individual bit fields
1044 UINT32 Reserved1
:11;
1046 /// [Bit 11] Execute Disable Bit Enable.
1049 UINT32 Reserved2
:20;
1050 UINT32 Reserved3
:32;
1053 /// All bit fields as a 32-bit value
1057 /// All bit fields as a 64-bit value
1060 } MSR_CORE_IA32_EFER_REGISTER
;