2 MSR Definitions for Intel Atom processors based on the Goldmont microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
20 May 2018, Volume 4: Model-Specific-Registers (MSR)
24 #ifndef __GOLDMONT_MSR_H__
25 #define __GOLDMONT_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Is Intel Atom processors based on the Goldmont microarchitecture?
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
38 #define IS_GOLDMONT_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
41 DisplayModel == 0x5C \
46 Core. Control Features in Intel 64Processor (R/W).
48 @param ECX MSR_GOLDMONT_FEATURE_CONTROL (0x0000003A)
49 @param EAX Lower 32-bits of MSR value.
50 Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER.
51 @param EDX Upper 32-bits of MSR value.
52 Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER.
56 MSR_GOLDMONT_FEATURE_CONTROL_REGISTER Msr;
58 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_FEATURE_CONTROL);
59 AsmWriteMsr64 (MSR_GOLDMONT_FEATURE_CONTROL, Msr.Uint64);
61 @note MSR_GOLDMONT_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
63 #define MSR_GOLDMONT_FEATURE_CONTROL 0x0000003A
66 MSR information returned for MSR index #MSR_GOLDMONT_FEATURE_CONTROL
70 /// Individual bit fields
74 /// [Bit 0] Lock bit (R/WL)
78 /// [Bit 1] Enable VMX inside SMX operation (R/WL)
80 UINT32 EnableVmxInsideSmx
:1;
82 /// [Bit 2] Enable VMX outside SMX operation (R/WL)
84 UINT32 EnableVmxOutsideSmx
:1;
87 /// [Bits 14:8] SENTER local function enables (R/WL)
89 UINT32 SenterLocalFunctionEnables
:7;
91 /// [Bit 15] SENTER global functions enable (R/WL)
93 UINT32 SenterGlobalEnable
:1;
96 /// [Bit 18] SGX global functions enable (R/WL)
103 /// All bit fields as a 32-bit value
107 /// All bit fields as a 64-bit value
110 } MSR_GOLDMONT_FEATURE_CONTROL_REGISTER
;
114 Package. See http://biosbits.org.
116 @param ECX MSR_GOLDMONT_PLATFORM_INFO (0x000000CE)
117 @param EAX Lower 32-bits of MSR value.
118 Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER.
119 @param EDX Upper 32-bits of MSR value.
120 Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER.
124 MSR_GOLDMONT_PLATFORM_INFO_REGISTER Msr;
126 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLATFORM_INFO);
127 AsmWriteMsr64 (MSR_GOLDMONT_PLATFORM_INFO, Msr.Uint64);
129 @note MSR_GOLDMONT_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
131 #define MSR_GOLDMONT_PLATFORM_INFO 0x000000CE
134 MSR information returned for MSR index #MSR_GOLDMONT_PLATFORM_INFO
138 /// Individual bit fields
143 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
144 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
147 UINT32 MaximumNonTurboRatio
:8;
150 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
151 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
152 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
153 /// Turbo mode is disabled.
157 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
158 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
159 /// and when set to 0, indicates TDP Limit for Turbo mode is not
164 /// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1,
165 /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to
166 /// specify an temperature offset.
172 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
173 /// minimum ratio (maximum efficiency) that the processor can operates, in
176 UINT32 MaximumEfficiencyRatio
:8;
180 /// All bit fields as a 64-bit value
183 } MSR_GOLDMONT_PLATFORM_INFO_REGISTER
;
187 Core. C-State Configuration Control (R/W) Note: C-state values are
188 processor specific C-state code names, unrelated to MWAIT extension C-state
189 parameters or ACPI CStates. See http://biosbits.org.
191 @param ECX MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)
192 @param EAX Lower 32-bits of MSR value.
193 Described by the type
194 MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
195 @param EDX Upper 32-bits of MSR value.
196 Described by the type
197 MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
201 MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
203 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL);
204 AsmWriteMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
206 @note MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
208 #define MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL 0x000000E2
211 MSR information returned for MSR index #MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL
215 /// Individual bit fields
219 /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest
220 /// processor-specific C-state code name (consuming the least power). for
221 /// the package. The default is set as factory-configured package C-state
222 /// limit. The following C-state code name encodings are supported: 0000b:
223 /// No limit 0001b: C1 0010b: C3 0011b: C6 0100b: C7 0101b: C7S 0110b: C8
224 /// 0111b: C9 1000b: C10.
229 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
230 /// IO_read instructions sent to IO register specified by
231 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
236 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
237 /// until next reset.
244 /// All bit fields as a 32-bit value
248 /// All bit fields as a 64-bit value
251 } MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER
;
255 Core. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement.
256 Accessible only while in SMM.
258 @param ECX MSR_GOLDMONT_SMM_MCA_CAP (0x0000017D)
259 @param EAX Lower 32-bits of MSR value.
260 Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER.
261 @param EDX Upper 32-bits of MSR value.
262 Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER.
266 MSR_GOLDMONT_SMM_MCA_CAP_REGISTER Msr;
268 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_MCA_CAP);
269 AsmWriteMsr64 (MSR_GOLDMONT_SMM_MCA_CAP, Msr.Uint64);
271 @note MSR_GOLDMONT_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
273 #define MSR_GOLDMONT_SMM_MCA_CAP 0x0000017D
276 MSR information returned for MSR index #MSR_GOLDMONT_SMM_MCA_CAP
280 /// Individual bit fields
286 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
287 /// SMM code access restriction is supported and the
288 /// MSR_SMM_FEATURE_CONTROL is supported.
290 UINT32 SMM_Code_Access_Chk
:1;
292 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
293 /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is
296 UINT32 Long_Flow_Indication
:1;
300 /// All bit fields as a 64-bit value
303 } MSR_GOLDMONT_SMM_MCA_CAP_REGISTER
;
307 Enable Misc. Processor Features (R/W) Allows a variety of processor
308 functions to be enabled and disabled.
310 @param ECX MSR_GOLDMONT_IA32_MISC_ENABLE (0x000001A0)
311 @param EAX Lower 32-bits of MSR value.
312 Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER.
313 @param EDX Upper 32-bits of MSR value.
314 Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER.
318 MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER Msr;
320 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE);
321 AsmWriteMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE, Msr.Uint64);
323 @note MSR_GOLDMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
325 #define MSR_GOLDMONT_IA32_MISC_ENABLE 0x000001A0
328 MSR information returned for MSR index #MSR_GOLDMONT_IA32_MISC_ENABLE
332 /// Individual bit fields
336 /// [Bit 0] Core. Fast-Strings Enable See Table 2-2.
338 UINT32 FastStrings
:1;
341 /// [Bit 3] Package. Automatic Thermal Control Circuit Enable (R/W) See
342 /// Table 2-2. Default value is 1.
344 UINT32 AutomaticThermalControlCircuit
:1;
347 /// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.
349 UINT32 PerformanceMonitoring
:1;
352 /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.
356 /// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See
362 /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
368 /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.
373 /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.
375 UINT32 LimitCpuidMaxval
:1;
377 /// [Bit 23] Package. xTPR Message Disable (R/W) See Table 2-2.
379 UINT32 xTPR_Message_Disable
:1;
383 /// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.
388 /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors
389 /// that support Intel Turbo Boost Technology, the turbo mode feature is
390 /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
391 /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
392 /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
393 /// the power-on default value is used by BIOS to detect hardware support
394 /// of turbo mode. If power-on default value is 1, turbo mode is available
395 /// in the processor. If power-on default value is 0, turbo mode is not
398 UINT32 TurboModeDisable
:1;
399 UINT32 Reserved10
:25;
402 /// All bit fields as a 64-bit value
405 } MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER
;
409 Miscellaneous Feature Control (R/W).
411 @param ECX MSR_GOLDMONT_MISC_FEATURE_CONTROL (0x000001A4)
412 @param EAX Lower 32-bits of MSR value.
413 Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER.
414 @param EDX Upper 32-bits of MSR value.
415 Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER.
419 MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER Msr;
421 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL);
422 AsmWriteMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL, Msr.Uint64);
424 @note MSR_GOLDMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
426 #define MSR_GOLDMONT_MISC_FEATURE_CONTROL 0x000001A4
429 MSR information returned for MSR index #MSR_GOLDMONT_MISC_FEATURE_CONTROL
433 /// Individual bit fields
437 /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
438 /// L2 hardware prefetcher, which fetches additional lines of code or data
439 /// into the L2 cache.
441 UINT32 L2HardwarePrefetcherDisable
:1;
444 /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables
445 /// the L1 data cache prefetcher, which fetches the next cache line into
448 UINT32 DCUHardwarePrefetcherDisable
:1;
453 /// All bit fields as a 32-bit value
457 /// All bit fields as a 64-bit value
460 } MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER
;
464 Package. See http://biosbits.org.
466 @param ECX MSR_GOLDMONT_MISC_PWR_MGMT (0x000001AA)
467 @param EAX Lower 32-bits of MSR value.
468 Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER.
469 @param EDX Upper 32-bits of MSR value.
470 Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER.
474 MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER Msr;
476 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT);
477 AsmWriteMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT, Msr.Uint64);
479 @note MSR_GOLDMONT_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.
481 #define MSR_GOLDMONT_MISC_PWR_MGMT 0x000001AA
484 MSR information returned for MSR index #MSR_GOLDMONT_MISC_PWR_MGMT
488 /// Individual bit fields
492 /// [Bit 0] EIST Hardware Coordination Disable (R/W) When 0, enables
493 /// hardware coordination of Enhanced Intel Speedstep Technology request
494 /// from processor cores; When 1, disables hardware coordination of
495 /// Enhanced Intel Speedstep Technology requests.
497 UINT32 EISTHardwareCoordinationDisable
:1;
500 /// [Bit 22] Thermal Interrupt Coordination Enable (R/W) If set, then
501 /// thermal interrupt on one core is routed to all cores.
503 UINT32 ThermalInterruptCoordinationEnable
:1;
508 /// All bit fields as a 32-bit value
512 /// All bit fields as a 64-bit value
515 } MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER
;
519 Package. Maximum Ratio Limit of Turbo Mode by Core Groups (RW) Specifies
520 Maximum Ratio Limit for each Core Group. Max ratio for groups with more
521 cores must decrease monotonically. For groups with less than 4 cores, the
522 max ratio must be 32 or less. For groups with 4-5 cores, the max ratio must
523 be 22 or less. For groups with more than 5 cores, the max ratio must be 16
526 @param ECX MSR_GOLDMONT_TURBO_RATIO_LIMIT (0x000001AD)
527 @param EAX Lower 32-bits of MSR value.
528 Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER.
529 @param EDX Upper 32-bits of MSR value.
530 Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER.
534 MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER Msr;
536 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT);
537 AsmWriteMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT, Msr.Uint64);
539 @note MSR_GOLDMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
541 #define MSR_GOLDMONT_TURBO_RATIO_LIMIT 0x000001AD
544 MSR information returned for MSR index #MSR_GOLDMONT_TURBO_RATIO_LIMIT
548 /// Individual bit fields
552 /// [Bits 7:0] Package. Maximum Ratio Limit for Active cores in Group 0
553 /// Maximum turbo ratio limit when number of active cores is less or equal
554 /// to Group 0 threshold.
556 UINT32 MaxRatioLimitGroup0
:8;
558 /// [Bits 15:8] Package. Maximum Ratio Limit for Active cores in Group 1
559 /// Maximum turbo ratio limit when number of active cores is less or equal
560 /// to Group 1 threshold and greater than Group 0 threshold.
562 UINT32 MaxRatioLimitGroup1
:8;
564 /// [Bits 23:16] Package. Maximum Ratio Limit for Active cores in Group 2
565 /// Maximum turbo ratio limit when number of active cores is less or equal
566 /// to Group 2 threshold and greater than Group 1 threshold.
568 UINT32 MaxRatioLimitGroup2
:8;
570 /// [Bits 31:24] Package. Maximum Ratio Limit for Active cores in Group 3
571 /// Maximum turbo ratio limit when number of active cores is less or equal
572 /// to Group 3 threshold and greater than Group 2 threshold.
574 UINT32 MaxRatioLimitGroup3
:8;
576 /// [Bits 39:32] Package. Maximum Ratio Limit for Active cores in Group 4
577 /// Maximum turbo ratio limit when number of active cores is less or equal
578 /// to Group 4 threshold and greater than Group 3 threshold.
580 UINT32 MaxRatioLimitGroup4
:8;
582 /// [Bits 47:40] Package. Maximum Ratio Limit for Active cores in Group 5
583 /// Maximum turbo ratio limit when number of active cores is less or equal
584 /// to Group 5 threshold and greater than Group 4 threshold.
586 UINT32 MaxRatioLimitGroup5
:8;
588 /// [Bits 55:48] Package. Maximum Ratio Limit for Active cores in Group 6
589 /// Maximum turbo ratio limit when number of active cores is less or equal
590 /// to Group 6 threshold and greater than Group 5 threshold.
592 UINT32 MaxRatioLimitGroup6
:8;
594 /// [Bits 63:56] Package. Maximum Ratio Limit for Active cores in Group 7
595 /// Maximum turbo ratio limit when number of active cores is less or equal
596 /// to Group 7 threshold and greater than Group 6 threshold.
598 UINT32 MaxRatioLimitGroup7
:8;
601 /// All bit fields as a 64-bit value
604 } MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER
;
608 Package. Group Size of Active Cores for Turbo Mode Operation (RW) Writes of
609 0 threshold is ignored.
611 @param ECX MSR_GOLDMONT_TURBO_GROUP_CORECNT (0x000001AE)
612 @param EAX Lower 32-bits of MSR value.
613 Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER.
614 @param EDX Upper 32-bits of MSR value.
615 Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER.
619 MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER Msr;
621 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT);
622 AsmWriteMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT, Msr.Uint64);
624 @note MSR_GOLDMONT_TURBO_GROUP_CORECNT is defined as MSR_TURBO_GROUP_CORECNT in SDM.
626 #define MSR_GOLDMONT_TURBO_GROUP_CORECNT 0x000001AE
629 MSR information returned for MSR index #MSR_GOLDMONT_TURBO_GROUP_CORECNT
633 /// Individual bit fields
637 /// [Bits 7:0] Package. Group 0 Core Count Threshold Maximum number of
638 /// active cores to operate under Group 0 Max Turbo Ratio limit.
640 UINT32 CoreCountThresholdGroup0
:8;
642 /// [Bits 15:8] Package. Group 1 Core Count Threshold Maximum number of
643 /// active cores to operate under Group 1 Max Turbo Ratio limit. Must be
644 /// greater than Group 0 Core Count.
646 UINT32 CoreCountThresholdGroup1
:8;
648 /// [Bits 23:16] Package. Group 2 Core Count Threshold Maximum number of
649 /// active cores to operate under Group 2 Max Turbo Ratio limit. Must be
650 /// greater than Group 1 Core Count.
652 UINT32 CoreCountThresholdGroup2
:8;
654 /// [Bits 31:24] Package. Group 3 Core Count Threshold Maximum number of
655 /// active cores to operate under Group 3 Max Turbo Ratio limit. Must be
656 /// greater than Group 2 Core Count.
658 UINT32 CoreCountThresholdGroup3
:8;
660 /// [Bits 39:32] Package. Group 4 Core Count Threshold Maximum number of
661 /// active cores to operate under Group 4 Max Turbo Ratio limit. Must be
662 /// greater than Group 3 Core Count.
664 UINT32 CoreCountThresholdGroup4
:8;
666 /// [Bits 47:40] Package. Group 5 Core Count Threshold Maximum number of
667 /// active cores to operate under Group 5 Max Turbo Ratio limit. Must be
668 /// greater than Group 4 Core Count.
670 UINT32 CoreCountThresholdGroup5
:8;
672 /// [Bits 55:48] Package. Group 6 Core Count Threshold Maximum number of
673 /// active cores to operate under Group 6 Max Turbo Ratio limit. Must be
674 /// greater than Group 5 Core Count.
676 UINT32 CoreCountThresholdGroup6
:8;
678 /// [Bits 63:56] Package. Group 7 Core Count Threshold Maximum number of
679 /// active cores to operate under Group 7 Max Turbo Ratio limit. Must be
680 /// greater than Group 6 Core Count and not less than the total number of
681 /// processor cores in the package. E.g. specify 255.
683 UINT32 CoreCountThresholdGroup7
:8;
686 /// All bit fields as a 64-bit value
689 } MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER
;
693 Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,
694 "Filtering of Last Branch Records.".
696 @param ECX MSR_GOLDMONT_LBR_SELECT (0x000001C8)
697 @param EAX Lower 32-bits of MSR value.
698 Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER.
699 @param EDX Upper 32-bits of MSR value.
700 Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER.
704 MSR_GOLDMONT_LBR_SELECT_REGISTER Msr;
706 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LBR_SELECT);
707 AsmWriteMsr64 (MSR_GOLDMONT_LBR_SELECT, Msr.Uint64);
709 @note MSR_GOLDMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
711 #define MSR_GOLDMONT_LBR_SELECT 0x000001C8
714 MSR information returned for MSR index #MSR_GOLDMONT_LBR_SELECT
718 /// Individual bit fields
722 /// [Bit 0] CPL_EQ_0.
726 /// [Bit 1] CPL_NEQ_0.
734 /// [Bit 3] NEAR_REL_CALL.
736 UINT32 NEAR_REL_CALL
:1;
738 /// [Bit 4] NEAR_IND_CALL.
740 UINT32 NEAR_IND_CALL
:1;
742 /// [Bit 5] NEAR_RET.
746 /// [Bit 6] NEAR_IND_JMP.
748 UINT32 NEAR_IND_JMP
:1;
750 /// [Bit 7] NEAR_REL_JMP.
752 UINT32 NEAR_REL_JMP
:1;
754 /// [Bit 8] FAR_BRANCH.
758 /// [Bit 9] EN_CALL_STACK.
760 UINT32 EN_CALL_STACK
:1;
765 /// All bit fields as a 32-bit value
769 /// All bit fields as a 64-bit value
772 } MSR_GOLDMONT_LBR_SELECT_REGISTER
;
776 Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4) that
777 points to the MSR containing the most recent branch record. See
778 MSR_LASTBRANCH_0_FROM_IP.
780 @param ECX MSR_GOLDMONT_LASTBRANCH_TOS (0x000001C9)
781 @param EAX Lower 32-bits of MSR value.
782 @param EDX Upper 32-bits of MSR value.
788 Msr = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS);
789 AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS, Msr);
791 @note MSR_GOLDMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
793 #define MSR_GOLDMONT_LASTBRANCH_TOS 0x000001C9
797 Core. Power Control Register. See http://biosbits.org.
799 @param ECX MSR_GOLDMONT_POWER_CTL (0x000001FC)
800 @param EAX Lower 32-bits of MSR value.
801 Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER.
802 @param EDX Upper 32-bits of MSR value.
803 Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER.
807 MSR_GOLDMONT_POWER_CTL_REGISTER Msr;
809 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_POWER_CTL);
810 AsmWriteMsr64 (MSR_GOLDMONT_POWER_CTL, Msr.Uint64);
812 @note MSR_GOLDMONT_POWER_CTL is defined as MSR_POWER_CTL in SDM.
814 #define MSR_GOLDMONT_POWER_CTL 0x000001FC
817 MSR information returned for MSR index #MSR_GOLDMONT_POWER_CTL
821 /// Individual bit fields
826 /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the
827 /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology
828 /// operating point when all execution cores enter MWAIT (C1).
835 /// All bit fields as a 32-bit value
839 /// All bit fields as a 64-bit value
842 } MSR_GOLDMONT_POWER_CTL_REGISTER
;
846 Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update
847 CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in
848 the package. Lower 64 bits of an 128-bit external entropy value for key
849 derivation of an enclave.
851 @param ECX MSR_GOLDMONT_SGXOWNEREPOCH0 (0x00000300)
852 @param EAX Lower 32-bits of MSR value.
853 @param EDX Upper 32-bits of MSR value.
859 Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH0);
861 @note MSR_GOLDMONT_SGXOWNEREPOCH0 is defined as MSR_SGXOWNEREPOCH0 in SDM.
863 #define MSR_GOLDMONT_SGXOWNEREPOCH0 0x00000300
867 // Define MSR_GOLDMONT_SGXOWNER0 for compatibility due to name change in the SDM.
869 #define MSR_GOLDMONT_SGXOWNER0 MSR_GOLDMONT_SGXOWNEREPOCH0
873 Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of
874 an 128-bit external entropy value for key derivation of an enclave.
876 @param ECX MSR_GOLDMONT_SGXOWNEREPOCH1 (0x00000301)
877 @param EAX Lower 32-bits of MSR value.
878 @param EDX Upper 32-bits of MSR value.
884 Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH1);
886 @note MSR_GOLDMONT_SGXOWNEREPOCH1 is defined as MSR_SGXOWNEREPOCH1 in SDM.
888 #define MSR_GOLDMONT_SGXOWNEREPOCH1 0x00000301
892 // Define MSR_GOLDMONT_SGXOWNER1 for compatibility due to name change in the SDM.
894 #define MSR_GOLDMONT_SGXOWNER1 MSR_GOLDMONT_SGXOWNEREPOCH1
898 Core. See Table 2-2. See Section 18.2.4, "Architectural Performance
899 Monitoring Version 4.".
901 @param ECX MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
902 @param EAX Lower 32-bits of MSR value.
903 Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
904 @param EDX Upper 32-bits of MSR value.
905 Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
909 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;
911 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET);
912 AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
914 @note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
916 #define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
919 MSR information returned for MSR index
920 #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET
924 /// Individual bit fields
928 /// [Bit 0] Set 1 to clear Ovf_PMC0.
932 /// [Bit 1] Set 1 to clear Ovf_PMC1.
936 /// [Bit 2] Set 1 to clear Ovf_PMC2.
940 /// [Bit 3] Set 1 to clear Ovf_PMC3.
945 /// [Bit 32] Set 1 to clear Ovf_FixedCtr0.
947 UINT32 Ovf_FixedCtr0
:1;
949 /// [Bit 33] Set 1 to clear Ovf_FixedCtr1.
951 UINT32 Ovf_FixedCtr1
:1;
953 /// [Bit 34] Set 1 to clear Ovf_FixedCtr2.
955 UINT32 Ovf_FixedCtr2
:1;
958 /// [Bit 55] Set 1 to clear Trace_ToPA_PMI.
960 UINT32 Trace_ToPA_PMI
:1;
963 /// [Bit 58] Set 1 to clear LBR_Frz.
967 /// [Bit 59] Set 1 to clear CTR_Frz.
971 /// [Bit 60] Set 1 to clear ASCI.
975 /// [Bit 61] Set 1 to clear Ovf_Uncore.
979 /// [Bit 62] Set 1 to clear Ovf_BufDSSAVE.
981 UINT32 Ovf_BufDSSAVE
:1;
983 /// [Bit 63] Set 1 to clear CondChgd.
988 /// All bit fields as a 64-bit value
991 } MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
;
995 Core. See Table 2-2. See Section 18.2.4, "Architectural Performance
996 Monitoring Version 4.".
998 @param ECX MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
999 @param EAX Lower 32-bits of MSR value.
1000 Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
1001 @param EDX Upper 32-bits of MSR value.
1002 Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
1004 <b>Example usage</b>
1006 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;
1008 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET);
1009 AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
1011 @note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
1013 #define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
1016 MSR information returned for MSR index
1017 #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET
1021 /// Individual bit fields
1025 /// [Bit 0] Set 1 to cause Ovf_PMC0 = 1.
1029 /// [Bit 1] Set 1 to cause Ovf_PMC1 = 1.
1033 /// [Bit 2] Set 1 to cause Ovf_PMC2 = 1.
1037 /// [Bit 3] Set 1 to cause Ovf_PMC3 = 1.
1040 UINT32 Reserved1
:28;
1042 /// [Bit 32] Set 1 to cause Ovf_FixedCtr0 = 1.
1044 UINT32 Ovf_FixedCtr0
:1;
1046 /// [Bit 33] Set 1 to cause Ovf_FixedCtr1 = 1.
1048 UINT32 Ovf_FixedCtr1
:1;
1050 /// [Bit 34] Set 1 to cause Ovf_FixedCtr2 = 1.
1052 UINT32 Ovf_FixedCtr2
:1;
1053 UINT32 Reserved2
:20;
1055 /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1.
1057 UINT32 Trace_ToPA_PMI
:1;
1060 /// [Bit 58] Set 1 to cause LBR_Frz = 1.
1064 /// [Bit 59] Set 1 to cause CTR_Frz = 1.
1068 /// [Bit 60] Set 1 to cause ASCI = 1.
1072 /// [Bit 61] Set 1 to cause Ovf_Uncore.
1074 UINT32 Ovf_Uncore
:1;
1076 /// [Bit 62] Set 1 to cause Ovf_BufDSSAVE.
1078 UINT32 Ovf_BufDSSAVE
:1;
1082 /// All bit fields as a 64-bit value
1085 } MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
;
1089 Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
1092 @param ECX MSR_GOLDMONT_PEBS_ENABLE (0x000003F1)
1093 @param EAX Lower 32-bits of MSR value.
1094 Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER.
1095 @param EDX Upper 32-bits of MSR value.
1096 Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER.
1098 <b>Example usage</b>
1100 MSR_GOLDMONT_PEBS_ENABLE_REGISTER Msr;
1102 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PEBS_ENABLE);
1103 AsmWriteMsr64 (MSR_GOLDMONT_PEBS_ENABLE, Msr.Uint64);
1105 @note MSR_GOLDMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1107 #define MSR_GOLDMONT_PEBS_ENABLE 0x000003F1
1110 MSR information returned for MSR index #MSR_GOLDMONT_PEBS_ENABLE
1114 /// Individual bit fields
1118 /// [Bit 0] Enable PEBS trigger and recording for the programmed event
1119 /// (precise or otherwise) on IA32_PMC0. (R/W).
1122 UINT32 Reserved1
:31;
1123 UINT32 Reserved2
:32;
1126 /// All bit fields as a 32-bit value
1130 /// All bit fields as a 64-bit value
1133 } MSR_GOLDMONT_PEBS_ENABLE_REGISTER
;
1137 Package. Note: C-state values are processor specific C-state code names,
1138 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3
1139 Residency Counter. (R/O) Value since last reset that this package is in
1140 processor-specific C3 states. Count at the same frequency as the TSC.
1142 @param ECX MSR_GOLDMONT_PKG_C3_RESIDENCY (0x000003F8)
1143 @param EAX Lower 32-bits of MSR value.
1144 @param EDX Upper 32-bits of MSR value.
1146 <b>Example usage</b>
1150 Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY);
1151 AsmWriteMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY, Msr);
1153 @note MSR_GOLDMONT_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
1155 #define MSR_GOLDMONT_PKG_C3_RESIDENCY 0x000003F8
1159 Package. Note: C-state values are processor specific C-state code names,
1160 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
1161 Residency Counter. (R/O) Value since last reset that this package is in
1162 processor-specific C6 states. Count at the same frequency as the TSC.
1164 @param ECX MSR_GOLDMONT_PKG_C6_RESIDENCY (0x000003F9)
1165 @param EAX Lower 32-bits of MSR value.
1166 @param EDX Upper 32-bits of MSR value.
1168 <b>Example usage</b>
1172 Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY);
1173 AsmWriteMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY, Msr);
1175 @note MSR_GOLDMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
1177 #define MSR_GOLDMONT_PKG_C6_RESIDENCY 0x000003F9
1181 Core. Note: C-state values are processor specific C-state code names,
1182 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3
1183 Residency Counter. (R/O) Value since last reset that this core is in
1184 processor-specific C3 states. Count at the same frequency as the TSC.
1186 @param ECX MSR_GOLDMONT_CORE_C3_RESIDENCY (0x000003FC)
1187 @param EAX Lower 32-bits of MSR value.
1188 @param EDX Upper 32-bits of MSR value.
1190 <b>Example usage</b>
1194 Msr = AsmReadMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY);
1195 AsmWriteMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY, Msr);
1197 @note MSR_GOLDMONT_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.
1199 #define MSR_GOLDMONT_CORE_C3_RESIDENCY 0x000003FC
1203 Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability
1204 Enhancement. Accessible only while in SMM.
1206 @param ECX MSR_GOLDMONT_SMM_FEATURE_CONTROL (0x000004E0)
1207 @param EAX Lower 32-bits of MSR value.
1208 Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER.
1209 @param EDX Upper 32-bits of MSR value.
1210 Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER.
1212 <b>Example usage</b>
1214 MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER Msr;
1216 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL);
1217 AsmWriteMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL, Msr.Uint64);
1219 @note MSR_GOLDMONT_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.
1221 #define MSR_GOLDMONT_SMM_FEATURE_CONTROL 0x000004E0
1224 MSR information returned for MSR index #MSR_GOLDMONT_SMM_FEATURE_CONTROL
1228 /// Individual bit fields
1232 /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from
1233 /// further changes.
1238 /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if
1239 /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the
1240 /// logical processors are prevented from executing SMM code outside the
1241 /// ranges defined by the SMRR. When set to '1' any logical processor in
1242 /// the package that attempts to execute SMM code not within the ranges
1243 /// defined by the SMRR will assert an unrecoverable MCE.
1245 UINT32 SMM_Code_Chk_En
:1;
1246 UINT32 Reserved2
:29;
1247 UINT32 Reserved3
:32;
1250 /// All bit fields as a 32-bit value
1254 /// All bit fields as a 64-bit value
1257 } MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER
;
1261 Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical
1262 processors in the package. Available only while in SMM and
1263 MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.
1265 @param ECX MSR_GOLDMONT_SMM_DELAYED (0x000004E2)
1266 @param EAX Lower 32-bits of MSR value.
1267 Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER.
1268 @param EDX Upper 32-bits of MSR value.
1269 Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER.
1271 <b>Example usage</b>
1273 MSR_GOLDMONT_SMM_DELAYED_REGISTER Msr;
1275 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_DELAYED);
1276 AsmWriteMsr64 (MSR_GOLDMONT_SMM_DELAYED, Msr.Uint64);
1278 @note MSR_GOLDMONT_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.
1280 #define MSR_GOLDMONT_SMM_DELAYED 0x000004E2
1284 Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical
1285 processors in the package. Available only while in SMM.
1287 @param ECX MSR_GOLDMONT_SMM_BLOCKED (0x000004E3)
1288 @param EAX Lower 32-bits of MSR value.
1289 Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER.
1290 @param EDX Upper 32-bits of MSR value.
1291 Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER.
1293 <b>Example usage</b>
1295 MSR_GOLDMONT_SMM_BLOCKED_REGISTER Msr;
1297 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_BLOCKED);
1298 AsmWriteMsr64 (MSR_GOLDMONT_SMM_BLOCKED, Msr.Uint64);
1300 @note MSR_GOLDMONT_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.
1302 #define MSR_GOLDMONT_SMM_BLOCKED 0x000004E3
1306 Core. Trace Control Register (R/W).
1308 @param ECX MSR_GOLDMONT_IA32_RTIT_CTL (0x00000570)
1309 @param EAX Lower 32-bits of MSR value.
1310 Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER.
1311 @param EDX Upper 32-bits of MSR value.
1312 Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER.
1314 <b>Example usage</b>
1316 MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER Msr;
1318 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL);
1319 AsmWriteMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL, Msr.Uint64);
1321 @note MSR_GOLDMONT_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.
1323 #define MSR_IA32_RTIT_CTL 0x00000570
1326 MSR information returned for MSR index #MSR_IA32_RTIT_CTL
1330 /// Individual bit fields
1334 /// [Bit 0] TraceEn.
1351 /// [Bit 7] CR3 filter.
1355 /// [Bit 8] ToPA. Writing 0 will #GP if also setting TraceEn.
1367 /// [Bit 11] DisRETC.
1372 /// [Bit 13] BranchEn.
1376 /// [Bits 17:14] MTCFreq.
1381 /// [Bits 22:19] CYCThresh.
1386 /// [Bits 27:24] PSBFreq.
1391 /// [Bits 35:32] ADDR0_CFG.
1395 /// [Bits 39:36] ADDR1_CFG.
1398 UINT32 Reserved6
:24;
1401 /// All bit fields as a 64-bit value
1404 } MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER
;
1408 Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,
1411 @param ECX MSR_GOLDMONT_RAPL_POWER_UNIT (0x00000606)
1412 @param EAX Lower 32-bits of MSR value.
1413 Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER.
1414 @param EDX Upper 32-bits of MSR value.
1415 Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER.
1417 <b>Example usage</b>
1419 MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER Msr;
1421 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_RAPL_POWER_UNIT);
1423 @note MSR_GOLDMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
1425 #define MSR_GOLDMONT_RAPL_POWER_UNIT 0x00000606
1428 MSR information returned for MSR index #MSR_GOLDMONT_RAPL_POWER_UNIT
1432 /// Individual bit fields
1436 /// [Bits 3:0] Power Units. Power related information (in Watts) is in
1437 /// unit of, 1W/2^PU; where PU is an unsigned integer represented by bits
1438 /// 3:0. Default value is 1000b, indicating power unit is in 3.9
1439 /// milliWatts increment.
1441 UINT32 PowerUnits
:4;
1444 /// [Bits 12:8] Energy Status Units. Energy related information (in
1445 /// Joules) is in unit of, 1Joule/ (2^ESU); where ESU is an unsigned
1446 /// integer represented by bits 12:8. Default value is 01110b, indicating
1447 /// energy unit is in 61 microJoules.
1449 UINT32 EnergyStatusUnits
:5;
1452 /// [Bits 19:16] Time Unit. Time related information (in seconds) is in
1453 /// unit of, 1S/2^TU; where TU is an unsigned integer represented by bits
1454 /// 19:16. Default value is 1010b, indicating power unit is in 0.977
1458 UINT32 Reserved3
:12;
1459 UINT32 Reserved4
:32;
1462 /// All bit fields as a 32-bit value
1466 /// All bit fields as a 64-bit value
1469 } MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER
;
1473 Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are
1474 processor specific C-state code names, unrelated to MWAIT extension C-state
1475 parameters or ACPI CStates.
1477 @param ECX MSR_GOLDMONT_PKGC3_IRTL (0x0000060A)
1478 @param EAX Lower 32-bits of MSR value.
1479 Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER.
1480 @param EDX Upper 32-bits of MSR value.
1481 Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER.
1483 <b>Example usage</b>
1485 MSR_GOLDMONT_PKGC3_IRTL_REGISTER Msr;
1487 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC3_IRTL);
1488 AsmWriteMsr64 (MSR_GOLDMONT_PKGC3_IRTL, Msr.Uint64);
1490 @note MSR_GOLDMONT_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.
1492 #define MSR_GOLDMONT_PKGC3_IRTL 0x0000060A
1495 MSR information returned for MSR index #MSR_GOLDMONT_PKGC3_IRTL
1499 /// Individual bit fields
1503 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
1504 /// that should be used to decide if the package should be put into a
1505 /// package C3 state.
1507 UINT32 InterruptResponseTimeLimit
:10;
1509 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
1510 /// of the interrupt response time limit. See Table 2-19 for supported
1511 /// time unit encodings.
1516 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
1517 /// valid and can be used by the processor for package C-sate management.
1520 UINT32 Reserved2
:16;
1521 UINT32 Reserved3
:32;
1524 /// All bit fields as a 32-bit value
1528 /// All bit fields as a 64-bit value
1531 } MSR_GOLDMONT_PKGC3_IRTL_REGISTER
;
1535 Package. Package C6/C7S Interrupt Response Limit 1 (R/W) This MSR defines
1536 the interrupt response time limit used by the processor to manage transition
1537 to package C6 or C7S state. Note: C-state values are processor specific
1538 C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
1541 @param ECX MSR_GOLDMONT_PKGC_IRTL1 (0x0000060B)
1542 @param EAX Lower 32-bits of MSR value.
1543 Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER.
1544 @param EDX Upper 32-bits of MSR value.
1545 Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER.
1547 <b>Example usage</b>
1549 MSR_GOLDMONT_PKGC_IRTL1_REGISTER Msr;
1551 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL1);
1552 AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL1, Msr.Uint64);
1554 @note MSR_GOLDMONT_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.
1556 #define MSR_GOLDMONT_PKGC_IRTL1 0x0000060B
1559 MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL1
1563 /// Individual bit fields
1567 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
1568 /// that should be used to decide if the package should be put into a
1569 /// package C6 or C7S state.
1571 UINT32 InterruptResponseTimeLimit
:10;
1573 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
1574 /// of the interrupt response time limit. See Table 2-19 for supported
1575 /// time unit encodings.
1580 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
1581 /// valid and can be used by the processor for package C-sate management.
1584 UINT32 Reserved2
:16;
1585 UINT32 Reserved3
:32;
1588 /// All bit fields as a 32-bit value
1592 /// All bit fields as a 64-bit value
1595 } MSR_GOLDMONT_PKGC_IRTL1_REGISTER
;
1599 Package. Package C7 Interrupt Response Limit 2 (R/W) This MSR defines the
1600 interrupt response time limit used by the processor to manage transition to
1601 package C7 state. Note: C-state values are processor specific C-state code
1602 names, unrelated to MWAIT extension C-state parameters or ACPI CStates.
1604 @param ECX MSR_GOLDMONT_PKGC_IRTL2 (0x0000060C)
1605 @param EAX Lower 32-bits of MSR value.
1606 Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER.
1607 @param EDX Upper 32-bits of MSR value.
1608 Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER.
1610 <b>Example usage</b>
1612 MSR_GOLDMONT_PKGC_IRTL2_REGISTER Msr;
1614 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL2);
1615 AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL2, Msr.Uint64);
1617 @note MSR_GOLDMONT_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.
1619 #define MSR_GOLDMONT_PKGC_IRTL2 0x0000060C
1622 MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL2
1626 /// Individual bit fields
1630 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
1631 /// that should be used to decide if the package should be put into a
1632 /// package C7 state.
1634 UINT32 InterruptResponseTimeLimit
:10;
1636 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
1637 /// of the interrupt response time limit. See Table 2-19 for supported
1638 /// time unit encodings.
1643 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
1644 /// valid and can be used by the processor for package C-sate management.
1647 UINT32 Reserved2
:16;
1648 UINT32 Reserved3
:32;
1651 /// All bit fields as a 32-bit value
1655 /// All bit fields as a 64-bit value
1658 } MSR_GOLDMONT_PKGC_IRTL2_REGISTER
;
1662 Package. Note: C-state values are processor specific C-state code names,
1663 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2
1664 Residency Counter. (R/O) Value since last reset that this package is in
1665 processor-specific C2 states. Count at the same frequency as the TSC.
1667 @param ECX MSR_GOLDMONT_PKG_C2_RESIDENCY (0x0000060D)
1668 @param EAX Lower 32-bits of MSR value.
1669 @param EDX Upper 32-bits of MSR value.
1671 <b>Example usage</b>
1675 Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY);
1676 AsmWriteMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY, Msr);
1678 @note MSR_GOLDMONT_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
1680 #define MSR_GOLDMONT_PKG_C2_RESIDENCY 0x0000060D
1684 Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
1687 @param ECX MSR_GOLDMONT_PKG_POWER_LIMIT (0x00000610)
1688 @param EAX Lower 32-bits of MSR value.
1689 @param EDX Upper 32-bits of MSR value.
1691 <b>Example usage</b>
1695 Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT);
1696 AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT, Msr);
1698 @note MSR_GOLDMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
1700 #define MSR_GOLDMONT_PKG_POWER_LIMIT 0x00000610
1704 Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1706 @param ECX MSR_GOLDMONT_PKG_ENERGY_STATUS (0x00000611)
1707 @param EAX Lower 32-bits of MSR value.
1708 @param EDX Upper 32-bits of MSR value.
1710 <b>Example usage</b>
1714 Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_ENERGY_STATUS);
1716 @note MSR_GOLDMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
1718 #define MSR_GOLDMONT_PKG_ENERGY_STATUS 0x00000611
1722 Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1724 @param ECX MSR_GOLDMONT_PKG_PERF_STATUS (0x00000613)
1725 @param EAX Lower 32-bits of MSR value.
1726 @param EDX Upper 32-bits of MSR value.
1728 <b>Example usage</b>
1732 Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_PERF_STATUS);
1734 @note MSR_GOLDMONT_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
1736 #define MSR_GOLDMONT_PKG_PERF_STATUS 0x00000613
1740 Package. PKG RAPL Parameters (R/W).
1742 @param ECX MSR_GOLDMONT_PKG_POWER_INFO (0x00000614)
1743 @param EAX Lower 32-bits of MSR value.
1744 Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER.
1745 @param EDX Upper 32-bits of MSR value.
1746 Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER.
1748 <b>Example usage</b>
1750 MSR_GOLDMONT_PKG_POWER_INFO_REGISTER Msr;
1752 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_INFO);
1753 AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_INFO, Msr.Uint64);
1755 @note MSR_GOLDMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
1757 #define MSR_GOLDMONT_PKG_POWER_INFO 0x00000614
1760 MSR information returned for MSR index #MSR_GOLDMONT_PKG_POWER_INFO
1764 /// Individual bit fields
1768 /// [Bits 14:0] Thermal Spec Power (R/W) See Section 14.9.3, "Package
1771 UINT32 ThermalSpecPower
:15;
1774 /// [Bits 30:16] Minimum Power (R/W) See Section 14.9.3, "Package RAPL
1777 UINT32 MinimumPower
:15;
1780 /// [Bits 46:32] Maximum Power (R/W) See Section 14.9.3, "Package RAPL
1783 UINT32 MaximumPower
:15;
1786 /// [Bits 54:48] Maximum Time Window (R/W) Specified by 2^Y * (1.0 +
1787 /// Z/4.0) * Time_Unit, where "Y" is the unsigned integer value
1788 /// represented. by bits 52:48, "Z" is an unsigned integer represented by
1789 /// bits 54:53. "Time_Unit" is specified by the "Time Units" field of
1790 /// MSR_RAPL_POWER_UNIT.
1792 UINT32 MaximumTimeWindow
:7;
1796 /// All bit fields as a 64-bit value
1799 } MSR_GOLDMONT_PKG_POWER_INFO_REGISTER
;
1803 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
1806 @param ECX MSR_GOLDMONT_DRAM_POWER_LIMIT (0x00000618)
1807 @param EAX Lower 32-bits of MSR value.
1808 @param EDX Upper 32-bits of MSR value.
1810 <b>Example usage</b>
1814 Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT);
1815 AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT, Msr);
1817 @note MSR_GOLDMONT_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
1819 #define MSR_GOLDMONT_DRAM_POWER_LIMIT 0x00000618
1823 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
1825 @param ECX MSR_GOLDMONT_DRAM_ENERGY_STATUS (0x00000619)
1826 @param EAX Lower 32-bits of MSR value.
1827 @param EDX Upper 32-bits of MSR value.
1829 <b>Example usage</b>
1833 Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_ENERGY_STATUS);
1835 @note MSR_GOLDMONT_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
1837 #define MSR_GOLDMONT_DRAM_ENERGY_STATUS 0x00000619
1841 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
1844 @param ECX MSR_GOLDMONT_DRAM_PERF_STATUS (0x0000061B)
1845 @param EAX Lower 32-bits of MSR value.
1846 @param EDX Upper 32-bits of MSR value.
1848 <b>Example usage</b>
1852 Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_PERF_STATUS);
1854 @note MSR_GOLDMONT_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
1856 #define MSR_GOLDMONT_DRAM_PERF_STATUS 0x0000061B
1860 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
1862 @param ECX MSR_GOLDMONT_DRAM_POWER_INFO (0x0000061C)
1863 @param EAX Lower 32-bits of MSR value.
1864 @param EDX Upper 32-bits of MSR value.
1866 <b>Example usage</b>
1870 Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO);
1871 AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO, Msr);
1873 @note MSR_GOLDMONT_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
1875 #define MSR_GOLDMONT_DRAM_POWER_INFO 0x0000061C
1879 Package. Note: C-state values are processor specific C-state code names,.
1880 Package C10 Residency Counter. (R/O) Value since last reset that the entire
1881 SOC is in an S0i3 state. Count at the same frequency as the TSC.
1883 @param ECX MSR_GOLDMONT_PKG_C10_RESIDENCY (0x00000632)
1884 @param EAX Lower 32-bits of MSR value.
1885 @param EDX Upper 32-bits of MSR value.
1887 <b>Example usage</b>
1891 Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY);
1892 AsmWriteMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY, Msr);
1894 @note MSR_GOLDMONT_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.
1896 #define MSR_GOLDMONT_PKG_C10_RESIDENCY 0x00000632
1900 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1903 @param ECX MSR_GOLDMONT_PP0_ENERGY_STATUS (0x00000639)
1904 @param EAX Lower 32-bits of MSR value.
1905 @param EDX Upper 32-bits of MSR value.
1907 <b>Example usage</b>
1911 Msr = AsmReadMsr64 (MSR_GOLDMONT_PP0_ENERGY_STATUS);
1913 @note MSR_GOLDMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
1915 #define MSR_GOLDMONT_PP0_ENERGY_STATUS 0x00000639
1919 Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1922 @param ECX MSR_GOLDMONT_PP1_ENERGY_STATUS (0x00000641)
1923 @param EAX Lower 32-bits of MSR value.
1924 @param EDX Upper 32-bits of MSR value.
1926 <b>Example usage</b>
1930 Msr = AsmReadMsr64 (MSR_GOLDMONT_PP1_ENERGY_STATUS);
1932 @note MSR_GOLDMONT_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.
1934 #define MSR_GOLDMONT_PP1_ENERGY_STATUS 0x00000641
1938 Package. ConfigTDP Control (R/W).
1940 @param ECX MSR_GOLDMONT_TURBO_ACTIVATION_RATIO (0x0000064C)
1941 @param EAX Lower 32-bits of MSR value.
1942 Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER.
1943 @param EDX Upper 32-bits of MSR value.
1944 Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER.
1946 <b>Example usage</b>
1948 MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER Msr;
1950 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO);
1951 AsmWriteMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO, Msr.Uint64);
1953 @note MSR_GOLDMONT_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
1955 #define MSR_GOLDMONT_TURBO_ACTIVATION_RATIO 0x0000064C
1958 MSR information returned for MSR index #MSR_GOLDMONT_TURBO_ACTIVATION_RATIO
1962 /// Individual bit fields
1966 /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this
1969 UINT32 MAX_NON_TURBO_RATIO
:8;
1970 UINT32 Reserved1
:23;
1972 /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the
1973 /// content of this register is locked until a reset.
1975 UINT32 TURBO_ACTIVATION_RATIO_Lock
:1;
1976 UINT32 Reserved2
:32;
1979 /// All bit fields as a 32-bit value
1983 /// All bit fields as a 64-bit value
1986 } MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER
;
1990 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
1991 refers to processor core frequency).
1993 @param ECX MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS (0x0000064F)
1994 @param EAX Lower 32-bits of MSR value.
1995 Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER.
1996 @param EDX Upper 32-bits of MSR value.
1997 Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER.
1999 <b>Example usage</b>
2001 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
2003 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS);
2004 AsmWriteMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
2006 @note MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
2008 #define MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS 0x0000064F
2011 MSR information returned for MSR index #MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS
2015 /// Individual bit fields
2019 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
2020 /// reduced below the operating system request due to assertion of
2021 /// external PROCHOT.
2023 UINT32 PROCHOTStatus
:1;
2025 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
2026 /// operating system request due to a thermal event.
2028 UINT32 ThermalStatus
:1;
2030 /// [Bit 2] Package-Level Power Limiting PL1 Status (R0) When set,
2031 /// frequency is reduced below the operating system request due to
2032 /// package-level power limiting PL1.
2036 /// [Bit 3] Package-Level PL2 Power Limiting Status (R0) When set,
2037 /// frequency is reduced below the operating system request due to
2038 /// package-level power limiting PL2.
2043 /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced
2044 /// below the operating system request due to domain-level power limiting.
2046 UINT32 PowerLimitingStatus
:1;
2048 /// [Bit 10] VR Therm Alert Status (R0) When set, frequency is reduced
2049 /// below the operating system request due to a thermal alert from the
2050 /// Voltage Regulator.
2052 UINT32 VRThermAlertStatus
:1;
2054 /// [Bit 11] Max Turbo Limit Status (R0) When set, frequency is reduced
2055 /// below the operating system request due to multi-core turbo limits.
2057 UINT32 MaxTurboLimitStatus
:1;
2059 /// [Bit 12] Electrical Design Point Status (R0) When set, frequency is
2060 /// reduced below the operating system request due to electrical design
2061 /// point constraints (e.g. maximum electrical current consumption).
2063 UINT32 ElectricalDesignPointStatus
:1;
2065 /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency
2066 /// is reduced below the operating system request due to Turbo transition
2067 /// attenuation. This prevents performance degradation due to frequent
2068 /// operating ratio changes.
2070 UINT32 TurboTransitionAttenuationStatus
:1;
2072 /// [Bit 14] Maximum Efficiency Frequency Status (R0) When set, frequency
2073 /// is reduced below the maximum efficiency frequency.
2075 UINT32 MaximumEfficiencyFrequencyStatus
:1;
2078 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
2079 /// has asserted since the log bit was last cleared. This log bit will
2080 /// remain set until cleared by software writing 0.
2084 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
2085 /// has asserted since the log bit was last cleared. This log bit will
2086 /// remain set until cleared by software writing 0.
2088 UINT32 ThermalLog
:1;
2090 /// [Bit 18] Package-Level PL1 Power Limiting Log When set, indicates
2091 /// that the Package Level PL1 Power Limiting Status bit has asserted
2092 /// since the log bit was last cleared. This log bit will remain set until
2093 /// cleared by software writing 0.
2097 /// [Bit 19] Package-Level PL2 Power Limiting Log When set, indicates that
2098 /// the Package Level PL2 Power Limiting Status bit has asserted since the
2099 /// log bit was last cleared. This log bit will remain set until cleared
2100 /// by software writing 0.
2105 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core
2106 /// Power Limiting Status bit has asserted since the log bit was last
2107 /// cleared. This log bit will remain set until cleared by software
2110 UINT32 CorePowerLimitingLog
:1;
2112 /// [Bit 26] VR Therm Alert Log When set, indicates that the VR Therm
2113 /// Alert Status bit has asserted since the log bit was last cleared. This
2114 /// log bit will remain set until cleared by software writing 0.
2116 UINT32 VRThermAlertLog
:1;
2118 /// [Bit 27] Max Turbo Limit Log When set, indicates that the Max Turbo
2119 /// Limit Status bit has asserted since the log bit was last cleared. This
2120 /// log bit will remain set until cleared by software writing 0.
2122 UINT32 MaxTurboLimitLog
:1;
2124 /// [Bit 28] Electrical Design Point Log When set, indicates that the EDP
2125 /// Status bit has asserted since the log bit was last cleared. This log
2126 /// bit will remain set until cleared by software writing 0.
2128 UINT32 ElectricalDesignPointLog
:1;
2130 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
2131 /// Turbo Transition Attenuation Status bit has asserted since the log bit
2132 /// was last cleared. This log bit will remain set until cleared by
2133 /// software writing 0.
2135 UINT32 TurboTransitionAttenuationLog
:1;
2137 /// [Bit 30] Maximum Efficiency Frequency Log When set, indicates that
2138 /// the Maximum Efficiency Frequency Status bit has asserted since the log
2139 /// bit was last cleared. This log bit will remain set until cleared by
2140 /// software writing 0.
2142 UINT32 MaximumEfficiencyFrequencyLog
:1;
2144 UINT32 Reserved5
:32;
2147 /// All bit fields as a 32-bit value
2151 /// All bit fields as a 64-bit value
2154 } MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER
;
2158 Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch
2159 record registers on the last branch record stack. The From_IP part of the
2160 stack contains pointers to the source instruction . See also: - Last Branch
2161 Record Stack TOS at 1C9H - Section 17.6 and record format in Section
2164 @param ECX MSR_GOLDMONT_LASTBRANCH_n_FROM_IP
2165 @param EAX Lower 32-bits of MSR value.
2166 Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER.
2167 @param EDX Upper 32-bits of MSR value.
2168 Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER.
2170 <b>Example usage</b>
2172 MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER Msr;
2174 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP);
2175 AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP, Msr.Uint64);
2177 @note MSR_GOLDMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
2178 MSR_GOLDMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
2179 MSR_GOLDMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
2180 MSR_GOLDMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
2181 MSR_GOLDMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
2182 MSR_GOLDMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
2183 MSR_GOLDMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
2184 MSR_GOLDMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
2185 MSR_GOLDMONT_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.
2186 MSR_GOLDMONT_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.
2187 MSR_GOLDMONT_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.
2188 MSR_GOLDMONT_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.
2189 MSR_GOLDMONT_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.
2190 MSR_GOLDMONT_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.
2191 MSR_GOLDMONT_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.
2192 MSR_GOLDMONT_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.
2193 MSR_GOLDMONT_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM.
2194 MSR_GOLDMONT_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM.
2195 MSR_GOLDMONT_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM.
2196 MSR_GOLDMONT_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM.
2197 MSR_GOLDMONT_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM.
2198 MSR_GOLDMONT_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM.
2199 MSR_GOLDMONT_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM.
2200 MSR_GOLDMONT_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM.
2201 MSR_GOLDMONT_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM.
2202 MSR_GOLDMONT_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM.
2203 MSR_GOLDMONT_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM.
2204 MSR_GOLDMONT_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM.
2205 MSR_GOLDMONT_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM.
2206 MSR_GOLDMONT_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM.
2207 MSR_GOLDMONT_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM.
2208 MSR_GOLDMONT_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.
2211 #define MSR_GOLDMONT_LASTBRANCH_0_FROM_IP 0x00000680
2212 #define MSR_GOLDMONT_LASTBRANCH_1_FROM_IP 0x00000681
2213 #define MSR_GOLDMONT_LASTBRANCH_2_FROM_IP 0x00000682
2214 #define MSR_GOLDMONT_LASTBRANCH_3_FROM_IP 0x00000683
2215 #define MSR_GOLDMONT_LASTBRANCH_4_FROM_IP 0x00000684
2216 #define MSR_GOLDMONT_LASTBRANCH_5_FROM_IP 0x00000685
2217 #define MSR_GOLDMONT_LASTBRANCH_6_FROM_IP 0x00000686
2218 #define MSR_GOLDMONT_LASTBRANCH_7_FROM_IP 0x00000687
2219 #define MSR_GOLDMONT_LASTBRANCH_8_FROM_IP 0x00000688
2220 #define MSR_GOLDMONT_LASTBRANCH_9_FROM_IP 0x00000689
2221 #define MSR_GOLDMONT_LASTBRANCH_10_FROM_IP 0x0000068A
2222 #define MSR_GOLDMONT_LASTBRANCH_11_FROM_IP 0x0000068B
2223 #define MSR_GOLDMONT_LASTBRANCH_12_FROM_IP 0x0000068C
2224 #define MSR_GOLDMONT_LASTBRANCH_13_FROM_IP 0x0000068D
2225 #define MSR_GOLDMONT_LASTBRANCH_14_FROM_IP 0x0000068E
2226 #define MSR_GOLDMONT_LASTBRANCH_15_FROM_IP 0x0000068F
2227 #define MSR_GOLDMONT_LASTBRANCH_16_FROM_IP 0x00000690
2228 #define MSR_GOLDMONT_LASTBRANCH_17_FROM_IP 0x00000691
2229 #define MSR_GOLDMONT_LASTBRANCH_18_FROM_IP 0x00000692
2230 #define MSR_GOLDMONT_LASTBRANCH_19_FROM_IP 0x00000693
2231 #define MSR_GOLDMONT_LASTBRANCH_20_FROM_IP 0x00000694
2232 #define MSR_GOLDMONT_LASTBRANCH_21_FROM_IP 0x00000695
2233 #define MSR_GOLDMONT_LASTBRANCH_22_FROM_IP 0x00000696
2234 #define MSR_GOLDMONT_LASTBRANCH_23_FROM_IP 0x00000697
2235 #define MSR_GOLDMONT_LASTBRANCH_24_FROM_IP 0x00000698
2236 #define MSR_GOLDMONT_LASTBRANCH_25_FROM_IP 0x00000699
2237 #define MSR_GOLDMONT_LASTBRANCH_26_FROM_IP 0x0000069A
2238 #define MSR_GOLDMONT_LASTBRANCH_27_FROM_IP 0x0000069B
2239 #define MSR_GOLDMONT_LASTBRANCH_28_FROM_IP 0x0000069C
2240 #define MSR_GOLDMONT_LASTBRANCH_29_FROM_IP 0x0000069D
2241 #define MSR_GOLDMONT_LASTBRANCH_30_FROM_IP 0x0000069E
2242 #define MSR_GOLDMONT_LASTBRANCH_31_FROM_IP 0x0000069F
2246 MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_FROM_IP
2247 to #MSR_GOLDMONT_LASTBRANCH_31_FROM_IP.
2251 /// Individual bit fields
2255 /// [Bit 31:0] From Linear Address (R/W).
2257 UINT32 FromLinearAddress
:32;
2259 /// [Bit 47:32] From Linear Address (R/W).
2261 UINT32 FromLinearAddressHi
:16;
2263 /// [Bits 62:48] Signed extension of bits 47:0.
2265 UINT32 SignedExtension
:15;
2267 /// [Bit 63] Mispred.
2272 /// All bit fields as a 32-bit value
2276 /// All bit fields as a 64-bit value
2279 } MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER
;
2283 Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record
2284 registers on the last branch record stack. The To_IP part of the stack
2285 contains pointers to the Destination instruction and elapsed cycles from
2286 last LBR update. See also: - Section 17.6.
2288 @param ECX MSR_GOLDMONT_LASTBRANCH_n_TO_IP
2289 @param EAX Lower 32-bits of MSR value.
2290 Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER.
2291 @param EDX Upper 32-bits of MSR value.
2292 Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER.
2294 <b>Example usage</b>
2296 MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER Msr;
2298 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP);
2299 AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP, Msr.Uint64);
2301 @note MSR_GOLDMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
2302 MSR_GOLDMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
2303 MSR_GOLDMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
2304 MSR_GOLDMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
2305 MSR_GOLDMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
2306 MSR_GOLDMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
2307 MSR_GOLDMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
2308 MSR_GOLDMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
2309 MSR_GOLDMONT_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.
2310 MSR_GOLDMONT_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.
2311 MSR_GOLDMONT_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.
2312 MSR_GOLDMONT_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.
2313 MSR_GOLDMONT_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.
2314 MSR_GOLDMONT_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.
2315 MSR_GOLDMONT_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.
2316 MSR_GOLDMONT_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.
2317 MSR_GOLDMONT_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM.
2318 MSR_GOLDMONT_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM.
2319 MSR_GOLDMONT_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM.
2320 MSR_GOLDMONT_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM.
2321 MSR_GOLDMONT_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM.
2322 MSR_GOLDMONT_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM.
2323 MSR_GOLDMONT_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM.
2324 MSR_GOLDMONT_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM.
2325 MSR_GOLDMONT_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM.
2326 MSR_GOLDMONT_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM.
2327 MSR_GOLDMONT_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM.
2328 MSR_GOLDMONT_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM.
2329 MSR_GOLDMONT_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM.
2330 MSR_GOLDMONT_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM.
2331 MSR_GOLDMONT_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM.
2332 MSR_GOLDMONT_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.
2335 #define MSR_GOLDMONT_LASTBRANCH_0_TO_IP 0x000006C0
2336 #define MSR_GOLDMONT_LASTBRANCH_1_TO_IP 0x000006C1
2337 #define MSR_GOLDMONT_LASTBRANCH_2_TO_IP 0x000006C2
2338 #define MSR_GOLDMONT_LASTBRANCH_3_TO_IP 0x000006C3
2339 #define MSR_GOLDMONT_LASTBRANCH_4_TO_IP 0x000006C4
2340 #define MSR_GOLDMONT_LASTBRANCH_5_TO_IP 0x000006C5
2341 #define MSR_GOLDMONT_LASTBRANCH_6_TO_IP 0x000006C6
2342 #define MSR_GOLDMONT_LASTBRANCH_7_TO_IP 0x000006C7
2343 #define MSR_GOLDMONT_LASTBRANCH_8_TO_IP 0x000006C8
2344 #define MSR_GOLDMONT_LASTBRANCH_9_TO_IP 0x000006C9
2345 #define MSR_GOLDMONT_LASTBRANCH_10_TO_IP 0x000006CA
2346 #define MSR_GOLDMONT_LASTBRANCH_11_TO_IP 0x000006CB
2347 #define MSR_GOLDMONT_LASTBRANCH_12_TO_IP 0x000006CC
2348 #define MSR_GOLDMONT_LASTBRANCH_13_TO_IP 0x000006CD
2349 #define MSR_GOLDMONT_LASTBRANCH_14_TO_IP 0x000006CE
2350 #define MSR_GOLDMONT_LASTBRANCH_15_TO_IP 0x000006CF
2351 #define MSR_GOLDMONT_LASTBRANCH_16_TO_IP 0x000006D0
2352 #define MSR_GOLDMONT_LASTBRANCH_17_TO_IP 0x000006D1
2353 #define MSR_GOLDMONT_LASTBRANCH_18_TO_IP 0x000006D2
2354 #define MSR_GOLDMONT_LASTBRANCH_19_TO_IP 0x000006D3
2355 #define MSR_GOLDMONT_LASTBRANCH_20_TO_IP 0x000006D4
2356 #define MSR_GOLDMONT_LASTBRANCH_21_TO_IP 0x000006D5
2357 #define MSR_GOLDMONT_LASTBRANCH_22_TO_IP 0x000006D6
2358 #define MSR_GOLDMONT_LASTBRANCH_23_TO_IP 0x000006D7
2359 #define MSR_GOLDMONT_LASTBRANCH_24_TO_IP 0x000006D8
2360 #define MSR_GOLDMONT_LASTBRANCH_25_TO_IP 0x000006D9
2361 #define MSR_GOLDMONT_LASTBRANCH_26_TO_IP 0x000006DA
2362 #define MSR_GOLDMONT_LASTBRANCH_27_TO_IP 0x000006DB
2363 #define MSR_GOLDMONT_LASTBRANCH_28_TO_IP 0x000006DC
2364 #define MSR_GOLDMONT_LASTBRANCH_29_TO_IP 0x000006DD
2365 #define MSR_GOLDMONT_LASTBRANCH_30_TO_IP 0x000006DE
2366 #define MSR_GOLDMONT_LASTBRANCH_31_TO_IP 0x000006DF
2370 MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_TO_IP to
2371 #MSR_GOLDMONT_LASTBRANCH_31_TO_IP.
2375 /// Individual bit fields
2379 /// [Bit 31:0] Target Linear Address (R/W).
2381 UINT32 TargetLinearAddress
:32;
2383 /// [Bit 47:32] Target Linear Address (R/W).
2385 UINT32 TargetLinearAddressHi
:16;
2387 /// [Bits 63:48] Elapsed cycles from last update to the LBR.
2389 UINT32 ElapsedCycles
:16;
2392 /// All bit fields as a 32-bit value
2396 /// All bit fields as a 64-bit value
2399 } MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER
;
2403 Core. Resource Association Register (R/W).
2405 @param ECX MSR_GOLDMONT_IA32_PQR_ASSOC (0x00000C8F)
2406 @param EAX Lower 32-bits of MSR value.
2407 Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER.
2408 @param EDX Upper 32-bits of MSR value.
2409 Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER.
2411 <b>Example usage</b>
2413 MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER Msr;
2415 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC);
2416 AsmWriteMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC, Msr.Uint64);
2418 @note MSR_GOLDMONT_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
2420 #define MSR_GOLDMONT_IA32_PQR_ASSOC 0x00000C8F
2423 MSR information returned for MSR index #MSR_GOLDMONT_IA32_PQR_ASSOC
2427 /// Individual bit fields
2430 UINT32 Reserved1
:32;
2432 /// [Bits 33:32] COS (R/W).
2435 UINT32 Reserved2
:30;
2438 /// All bit fields as a 64-bit value
2441 } MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER
;
2445 Module. L2 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,
2446 ECX=1):EDX.COS_MAX[15:0] >=n.
2448 @param ECX MSR_GOLDMONT_IA32_L2_QOS_MASK_n
2449 @param EAX Lower 32-bits of MSR value.
2450 Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER.
2451 @param EDX Upper 32-bits of MSR value.
2452 Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER.
2454 <b>Example usage</b>
2456 MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER Msr;
2458 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n);
2459 AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n, Msr.Uint64);
2461 @note MSR_GOLDMONT_IA32_L2_QOS_MASK_0 is defined as IA32_L2_QOS_MASK_0 in SDM.
2462 MSR_GOLDMONT_IA32_L2_QOS_MASK_1 is defined as IA32_L2_QOS_MASK_1 in SDM.
2463 MSR_GOLDMONT_IA32_L2_QOS_MASK_2 is defined as IA32_L2_QOS_MASK_2 in SDM.
2466 #define MSR_GOLDMONT_IA32_L2_QOS_MASK_0 0x00000D10
2467 #define MSR_GOLDMONT_IA32_L2_QOS_MASK_1 0x00000D11
2468 #define MSR_GOLDMONT_IA32_L2_QOS_MASK_2 0x00000D12
2472 MSR information returned for MSR indexes #MSR_GOLDMONT_IA32_L2_QOS_MASK_0 to
2473 #MSR_GOLDMONT_IA32_L2_QOS_MASK_2.
2477 /// Individual bit fields
2481 /// [Bits 7:0] CBM: Bit vector of available L2 ways for COS 0 enforcement
2484 UINT32 Reserved1
:24;
2485 UINT32 Reserved2
:32;
2488 /// All bit fields as a 32-bit value
2492 /// All bit fields as a 64-bit value
2495 } MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER
;
2499 Package. L2 Class Of Service Mask - COS 3 (R/W) if CPUID.(EAX=10H,
2500 ECX=1):EDX.COS_MAX[15:0] >=3.
2502 @param ECX MSR_GOLDMONT_IA32_L2_QOS_MASK_3
2503 @param EAX Lower 32-bits of MSR value.
2504 Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER.
2505 @param EDX Upper 32-bits of MSR value.
2506 Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER.
2508 <b>Example usage</b>
2510 MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER Msr;
2512 Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3);
2513 AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3, Msr.Uint64);
2515 @note MSR_GOLDMONT_IA32_L2_QOS_MASK_3 is defined as IA32_L2_QOS_MASK_3 in SDM.
2517 #define MSR_GOLDMONT_IA32_L2_QOS_MASK_3 0x00000D13
2520 MSR information returned for MSR index #MSR_GOLDMONT_IA32_L2_QOS_MASK_3.
2524 /// Individual bit fields
2528 /// [Bits 19:0] CBM: Bit vector of available L2 ways for COS 0 enforcement
2531 UINT32 Reserved1
:12;
2532 UINT32 Reserved2
:32;
2535 /// All bit fields as a 32-bit value
2539 /// All bit fields as a 64-bit value
2542 } MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER
;