2 MSR Definitions for Intel processors based on the Haswell microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
18 #ifndef __HASWELL_MSR_H__
19 #define __HASWELL_MSR_H__
21 #include <Register/ArchitecturalMsr.h>
24 Is Intel processors based on the Haswell microarchitecture?
26 @param DisplayFamily Display Family ID
27 @param DisplayModel Display Model ID
29 @retval TRUE Yes, it is.
30 @retval FALSE No, it isn't.
32 #define IS_HASWELL_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
35 DisplayModel == 0x3C || \
36 DisplayModel == 0x45 || \
37 DisplayModel == 0x46 \
44 @param ECX MSR_HASWELL_PLATFORM_INFO (0x000000CE)
45 @param EAX Lower 32-bits of MSR value.
46 Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.
47 @param EDX Upper 32-bits of MSR value.
48 Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.
52 MSR_HASWELL_PLATFORM_INFO_REGISTER Msr;
54 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PLATFORM_INFO);
55 AsmWriteMsr64 (MSR_HASWELL_PLATFORM_INFO, Msr.Uint64);
57 @note MSR_HASWELL_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
59 #define MSR_HASWELL_PLATFORM_INFO 0x000000CE
62 MSR information returned for MSR index #MSR_HASWELL_PLATFORM_INFO
66 /// Individual bit fields
71 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
72 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
75 UINT32 MaximumNonTurboRatio
:8;
78 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
79 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
80 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
81 /// Turbo mode is disabled.
85 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
86 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
87 /// and when set to 0, indicates TDP Limit for Turbo mode is not
93 /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,
94 /// indicates that LPM is supported, and when set to 0, indicates LPM is
97 UINT32 LowPowerModeSupport
:1;
99 /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base
100 /// TDP level available. 01: One additional TDP level available. 02: Two
101 /// additional TDP level available. 11: Reserved.
103 UINT32 ConfigTDPLevels
:2;
106 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
107 /// minimum ratio (maximum efficiency) that the processor can operates, in
110 UINT32 MaximumEfficiencyRatio
:8;
112 /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the
113 /// minimum supported operating ratio in units of 100 MHz.
115 UINT32 MinimumOperatingRatio
:8;
119 /// All bit fields as a 64-bit value
122 } MSR_HASWELL_PLATFORM_INFO_REGISTER
;
126 Thread. Performance Event Select for Counter n (R/W) Supports all fields
127 described inTable 2-2 and the fields below.
129 @param ECX MSR_HASWELL_IA32_PERFEVTSELn
130 @param EAX Lower 32-bits of MSR value.
131 Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.
132 @param EDX Upper 32-bits of MSR value.
133 Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.
137 MSR_HASWELL_IA32_PERFEVTSEL_REGISTER Msr;
139 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0);
140 AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0, Msr.Uint64);
142 @note MSR_HASWELL_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.
143 MSR_HASWELL_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.
144 MSR_HASWELL_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.
147 #define MSR_HASWELL_IA32_PERFEVTSEL0 0x00000186
148 #define MSR_HASWELL_IA32_PERFEVTSEL1 0x00000187
149 #define MSR_HASWELL_IA32_PERFEVTSEL3 0x00000189
153 MSR information returned for MSR indexes #MSR_HASWELL_IA32_PERFEVTSEL0,
154 #MSR_HASWELL_IA32_PERFEVTSEL1, and #MSR_HASWELL_IA32_PERFEVTSEL3.
158 /// Individual bit fields
162 /// [Bits 7:0] Event Select: Selects a performance event logic unit.
164 UINT32 EventSelect
:8;
166 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
167 /// detect on the selected event logic.
171 /// [Bit 16] USR: Counts while in privilege level is not ring 0.
175 /// [Bit 17] OS: Counts while in privilege level is ring 0.
179 /// [Bit 18] Edge: Enables edge detection if set.
183 /// [Bit 19] PC: enables pin control.
187 /// [Bit 20] INT: enables interrupt on counter overflow.
191 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
192 /// event conditions occurring across all logical processors sharing a
193 /// processor core. When set to 0, the counter only increments the
194 /// associated event conditions occurring in the logical processor which
195 /// programmed the MSR.
199 /// [Bit 22] EN: enables the corresponding performance counter to commence
200 /// counting when this bit is set.
204 /// [Bit 23] INV: invert the CMASK.
208 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
209 /// performance counter increments each cycle if the event count is
210 /// greater than or equal to the CMASK.
215 /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,
216 /// AnyThread (bit 21) should be cleared to prevent incorrect results.
222 /// All bit fields as a 64-bit value
225 } MSR_HASWELL_IA32_PERFEVTSEL_REGISTER
;
229 Thread. Performance Event Select for Counter 2 (R/W) Supports all fields
230 described inTable 2-2 and the fields below.
232 @param ECX MSR_HASWELL_IA32_PERFEVTSEL2 (0x00000188)
233 @param EAX Lower 32-bits of MSR value.
234 Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.
235 @param EDX Upper 32-bits of MSR value.
236 Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.
240 MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER Msr;
242 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2);
243 AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2, Msr.Uint64);
245 @note MSR_HASWELL_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.
247 #define MSR_HASWELL_IA32_PERFEVTSEL2 0x00000188
250 MSR information returned for MSR index #MSR_HASWELL_IA32_PERFEVTSEL2
254 /// Individual bit fields
258 /// [Bits 7:0] Event Select: Selects a performance event logic unit.
260 UINT32 EventSelect
:8;
262 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
263 /// detect on the selected event logic.
267 /// [Bit 16] USR: Counts while in privilege level is not ring 0.
271 /// [Bit 17] OS: Counts while in privilege level is ring 0.
275 /// [Bit 18] Edge: Enables edge detection if set.
279 /// [Bit 19] PC: enables pin control.
283 /// [Bit 20] INT: enables interrupt on counter overflow.
287 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
288 /// event conditions occurring across all logical processors sharing a
289 /// processor core. When set to 0, the counter only increments the
290 /// associated event conditions occurring in the logical processor which
291 /// programmed the MSR.
295 /// [Bit 22] EN: enables the corresponding performance counter to commence
296 /// counting when this bit is set.
300 /// [Bit 23] INV: invert the CMASK.
304 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
305 /// performance counter increments each cycle if the event count is
306 /// greater than or equal to the CMASK.
311 /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,
312 /// AnyThread (bit 21) should be cleared to prevent incorrect results.
316 /// [Bit 33] IN_TXCP: see Section 18.3.6.5.1 When IN_TXCP=1 & IN_TX=1 and
317 /// in sampling, spurious PMI may occur and transactions may continuously
318 /// abort near overflow conditions. Software should favor using IN_TXCP
319 /// for counting over sampling. If sampling, software should use large
320 /// "sample-after" value after clearing the counter configured to use
321 /// IN_TXCP and also always reset the counter even when no overflow
322 /// condition was reported.
328 /// All bit fields as a 64-bit value
331 } MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER
;
335 Thread. Last Branch Record Filtering Select Register (R/W).
337 @param ECX MSR_HASWELL_LBR_SELECT (0x000001C8)
338 @param EAX Lower 32-bits of MSR value.
339 Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.
340 @param EDX Upper 32-bits of MSR value.
341 Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.
345 MSR_HASWELL_LBR_SELECT_REGISTER Msr;
347 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_LBR_SELECT);
348 AsmWriteMsr64 (MSR_HASWELL_LBR_SELECT, Msr.Uint64);
350 @note MSR_HASWELL_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
352 #define MSR_HASWELL_LBR_SELECT 0x000001C8
355 MSR information returned for MSR index #MSR_HASWELL_LBR_SELECT
359 /// Individual bit fields
363 /// [Bit 0] CPL_EQ_0.
367 /// [Bit 1] CPL_NEQ_0.
375 /// [Bit 3] NEAR_REL_CALL.
377 UINT32 NEAR_REL_CALL
:1;
379 /// [Bit 4] NEAR_IND_CALL.
381 UINT32 NEAR_IND_CALL
:1;
383 /// [Bit 5] NEAR_RET.
387 /// [Bit 6] NEAR_IND_JMP.
389 UINT32 NEAR_IND_JMP
:1;
391 /// [Bit 7] NEAR_REL_JMP.
393 UINT32 NEAR_REL_JMP
:1;
395 /// [Bit 8] FAR_BRANCH.
399 /// [Bit 9] EN_CALL_STACK.
401 UINT32 EN_CALL_STACK
:1;
406 /// All bit fields as a 32-bit value
410 /// All bit fields as a 64-bit value
413 } MSR_HASWELL_LBR_SELECT_REGISTER
;
417 Package. Package C6/C7 Interrupt Response Limit 1 (R/W) This MSR defines
418 the interrupt response time limit used by the processor to manage transition
419 to package C6 or C7 state. The latency programmed in this register is for
420 the shorter-latency sub C-states used by an MWAIT hint to C6 or C7 state.
421 Note: C-state values are processor specific C-state code names, unrelated to
422 MWAIT extension C-state parameters or ACPI C-States.
424 @param ECX MSR_HASWELL_PKGC_IRTL1 (0x0000060B)
425 @param EAX Lower 32-bits of MSR value.
426 Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.
427 @param EDX Upper 32-bits of MSR value.
428 Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.
432 MSR_HASWELL_PKGC_IRTL1_REGISTER Msr;
434 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL1);
435 AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL1, Msr.Uint64);
437 @note MSR_HASWELL_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.
439 #define MSR_HASWELL_PKGC_IRTL1 0x0000060B
442 MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL1
446 /// Individual bit fields
450 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
451 /// that should be used to decide if the package should be put into a
452 /// package C6 or C7 state.
454 UINT32 InterruptResponseTimeLimit
:10;
456 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
457 /// of the interrupt response time limit. See Table 2-19 for supported
458 /// time unit encodings.
463 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
464 /// valid and can be used by the processor for package C-sate management.
471 /// All bit fields as a 32-bit value
475 /// All bit fields as a 64-bit value
478 } MSR_HASWELL_PKGC_IRTL1_REGISTER
;
482 Package. Package C6/C7 Interrupt Response Limit 2 (R/W) This MSR defines
483 the interrupt response time limit used by the processor to manage transition
484 to package C6 or C7 state. The latency programmed in this register is for
485 the longer-latency sub Cstates used by an MWAIT hint to C6 or C7 state.
486 Note: C-state values are processor specific C-state code names, unrelated to
487 MWAIT extension C-state parameters or ACPI C-States.
489 @param ECX MSR_HASWELL_PKGC_IRTL2 (0x0000060C)
490 @param EAX Lower 32-bits of MSR value.
491 Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.
492 @param EDX Upper 32-bits of MSR value.
493 Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.
497 MSR_HASWELL_PKGC_IRTL2_REGISTER Msr;
499 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL2);
500 AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL2, Msr.Uint64);
502 @note MSR_HASWELL_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.
504 #define MSR_HASWELL_PKGC_IRTL2 0x0000060C
507 MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL2
511 /// Individual bit fields
515 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
516 /// that should be used to decide if the package should be put into a
517 /// package C6 or C7 state.
519 UINT32 InterruptResponseTimeLimit
:10;
521 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
522 /// of the interrupt response time limit. See Table 2-19 for supported
523 /// time unit encodings.
528 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
529 /// valid and can be used by the processor for package C-sate management.
536 /// All bit fields as a 32-bit value
540 /// All bit fields as a 64-bit value
543 } MSR_HASWELL_PKGC_IRTL2_REGISTER
;
547 Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
549 @param ECX MSR_HASWELL_PKG_PERF_STATUS (0x00000613)
550 @param EAX Lower 32-bits of MSR value.
551 @param EDX Upper 32-bits of MSR value.
557 Msr = AsmReadMsr64 (MSR_HASWELL_PKG_PERF_STATUS);
559 @note MSR_HASWELL_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
561 #define MSR_HASWELL_PKG_PERF_STATUS 0x00000613
565 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
567 @param ECX MSR_HASWELL_DRAM_ENERGY_STATUS (0x00000619)
568 @param EAX Lower 32-bits of MSR value.
569 @param EDX Upper 32-bits of MSR value.
575 Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_ENERGY_STATUS);
577 @note MSR_HASWELL_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
579 #define MSR_HASWELL_DRAM_ENERGY_STATUS 0x00000619
583 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
586 @param ECX MSR_HASWELL_DRAM_PERF_STATUS (0x0000061B)
587 @param EAX Lower 32-bits of MSR value.
588 @param EDX Upper 32-bits of MSR value.
594 Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_PERF_STATUS);
596 @note MSR_HASWELL_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
598 #define MSR_HASWELL_DRAM_PERF_STATUS 0x0000061B
602 Package. Base TDP Ratio (R/O).
604 @param ECX MSR_HASWELL_CONFIG_TDP_NOMINAL (0x00000648)
605 @param EAX Lower 32-bits of MSR value.
606 Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.
607 @param EDX Upper 32-bits of MSR value.
608 Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.
612 MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER Msr;
614 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_NOMINAL);
616 @note MSR_HASWELL_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
618 #define MSR_HASWELL_CONFIG_TDP_NOMINAL 0x00000648
621 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_NOMINAL
625 /// Individual bit fields
629 /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this
630 /// specific processor (in units of 100 MHz).
632 UINT32 Config_TDP_Base
:8;
637 /// All bit fields as a 32-bit value
641 /// All bit fields as a 64-bit value
644 } MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER
;
648 Package. ConfigTDP Level 1 ratio and power level (R/O).
650 @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL1 (0x00000649)
651 @param EAX Lower 32-bits of MSR value.
652 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.
653 @param EDX Upper 32-bits of MSR value.
654 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.
658 MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER Msr;
660 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL1);
662 @note MSR_HASWELL_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
664 #define MSR_HASWELL_CONFIG_TDP_LEVEL1 0x00000649
667 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL1
671 /// Individual bit fields
675 /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.
677 UINT32 PKG_TDP_LVL1
:15;
680 /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used
681 /// for this specific processor.
683 UINT32 Config_TDP_LVL1_Ratio
:8;
686 /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP
689 UINT32 PKG_MAX_PWR_LVL1
:15;
691 /// [Bits 62:47] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP
694 UINT32 PKG_MIN_PWR_LVL1
:16;
698 /// All bit fields as a 64-bit value
701 } MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER
;
705 Package. ConfigTDP Level 2 ratio and power level (R/O).
707 @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL2 (0x0000064A)
708 @param EAX Lower 32-bits of MSR value.
709 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.
710 @param EDX Upper 32-bits of MSR value.
711 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.
715 MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER Msr;
717 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL2);
719 @note MSR_HASWELL_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
721 #define MSR_HASWELL_CONFIG_TDP_LEVEL2 0x0000064A
724 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL2
728 /// Individual bit fields
732 /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.
734 UINT32 PKG_TDP_LVL2
:15;
737 /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used
738 /// for this specific processor.
740 UINT32 Config_TDP_LVL2_Ratio
:8;
743 /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP
746 UINT32 PKG_MAX_PWR_LVL2
:15;
748 /// [Bits 62:47] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP
751 UINT32 PKG_MIN_PWR_LVL2
:16;
755 /// All bit fields as a 64-bit value
758 } MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER
;
762 Package. ConfigTDP Control (R/W).
764 @param ECX MSR_HASWELL_CONFIG_TDP_CONTROL (0x0000064B)
765 @param EAX Lower 32-bits of MSR value.
766 Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.
767 @param EDX Upper 32-bits of MSR value.
768 Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.
772 MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER Msr;
774 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL);
775 AsmWriteMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL, Msr.Uint64);
777 @note MSR_HASWELL_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
779 #define MSR_HASWELL_CONFIG_TDP_CONTROL 0x0000064B
782 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_CONTROL
786 /// Individual bit fields
790 /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.
795 /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of
796 /// this register is locked until a reset.
798 UINT32 Config_TDP_Lock
:1;
802 /// All bit fields as a 32-bit value
806 /// All bit fields as a 64-bit value
809 } MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER
;
813 Package. ConfigTDP Control (R/W).
815 @param ECX MSR_HASWELL_TURBO_ACTIVATION_RATIO (0x0000064C)
816 @param EAX Lower 32-bits of MSR value.
817 Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.
818 @param EDX Upper 32-bits of MSR value.
819 Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.
823 MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER Msr;
825 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO);
826 AsmWriteMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO, Msr.Uint64);
828 @note MSR_HASWELL_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
830 #define MSR_HASWELL_TURBO_ACTIVATION_RATIO 0x0000064C
833 MSR information returned for MSR index #MSR_HASWELL_TURBO_ACTIVATION_RATIO
837 /// Individual bit fields
841 /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this
844 UINT32 MAX_NON_TURBO_RATIO
:8;
847 /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the
848 /// content of this register is locked until a reset.
850 UINT32 TURBO_ACTIVATION_RATIO_Lock
:1;
854 /// All bit fields as a 32-bit value
858 /// All bit fields as a 64-bit value
861 } MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER
;
865 Core. C-State Configuration Control (R/W) Note: C-state values are processor
866 specific C-state code names, unrelated to MWAIT extension C-state parameters
867 or ACPI Cstates. `See http://biosbits.org. <http://biosbits.org>`__.
869 @param ECX MSR_HASWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)
870 @param EAX Lower 32-bits of MSR value.
871 Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
872 @param EDX Upper 32-bits of MSR value.
873 Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
877 MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
879 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL);
880 AsmWriteMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
882 @note MSR_HASWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
884 #define MSR_HASWELL_PKG_CST_CONFIG_CONTROL 0x000000E2
887 MSR information returned for MSR index #MSR_HASWELL_PKG_CST_CONFIG_CONTROL
891 /// Individual bit fields
895 /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest
896 /// processor-specific C-state code name (consuming the least power) for
897 /// the package. The default is set as factory-configured package C-state
898 /// limit. The following C-state code name encodings are supported: 0000b:
899 /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6
900 /// 0100b: C7 0101b: C7s Package C states C7 are not available to
901 /// processor with signature 06_3CH.
906 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
911 /// [Bit 15] CFG Lock (R/WO).
916 /// [Bit 25] C3 State Auto Demotion Enable (R/W).
918 UINT32 C3AutoDemotion
:1;
920 /// [Bit 26] C1 State Auto Demotion Enable (R/W).
922 UINT32 C1AutoDemotion
:1;
924 /// [Bit 27] Enable C3 Undemotion (R/W).
926 UINT32 C3Undemotion
:1;
928 /// [Bit 28] Enable C1 Undemotion (R/W).
930 UINT32 C1Undemotion
:1;
935 /// All bit fields as a 32-bit value
939 /// All bit fields as a 64-bit value
942 } MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER
;
946 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
947 Enhancement. Accessible only while in SMM.
949 @param ECX MSR_HASWELL_SMM_MCA_CAP (0x0000017D)
950 @param EAX Lower 32-bits of MSR value.
951 Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.
952 @param EDX Upper 32-bits of MSR value.
953 Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.
957 MSR_HASWELL_SMM_MCA_CAP_REGISTER Msr;
959 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_MCA_CAP);
960 AsmWriteMsr64 (MSR_HASWELL_SMM_MCA_CAP, Msr.Uint64);
962 @note MSR_HASWELL_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
964 #define MSR_HASWELL_SMM_MCA_CAP 0x0000017D
967 MSR information returned for MSR index #MSR_HASWELL_SMM_MCA_CAP
971 /// Individual bit fields
977 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
978 /// SMM code access restriction is supported and the
979 /// MSR_SMM_FEATURE_CONTROL is supported.
981 UINT32 SMM_Code_Access_Chk
:1;
983 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
984 /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is
987 UINT32 Long_Flow_Indication
:1;
991 /// All bit fields as a 64-bit value
994 } MSR_HASWELL_SMM_MCA_CAP_REGISTER
;
998 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
999 RW if MSR_PLATFORM_INFO.[28] = 1.
1001 @param ECX MSR_HASWELL_TURBO_RATIO_LIMIT (0x000001AD)
1002 @param EAX Lower 32-bits of MSR value.
1003 Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.
1004 @param EDX Upper 32-bits of MSR value.
1005 Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.
1007 <b>Example usage</b>
1009 MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER Msr;
1011 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_RATIO_LIMIT);
1013 @note MSR_HASWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
1015 #define MSR_HASWELL_TURBO_RATIO_LIMIT 0x000001AD
1018 MSR information returned for MSR index #MSR_HASWELL_TURBO_RATIO_LIMIT
1022 /// Individual bit fields
1026 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
1027 /// limit of 1 core active.
1031 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
1032 /// limit of 2 core active.
1036 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
1037 /// limit of 3 core active.
1041 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
1042 /// limit of 4 core active.
1048 /// All bit fields as a 32-bit value
1052 /// All bit fields as a 64-bit value
1055 } MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER
;
1059 Package. Uncore PMU global control.
1061 @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_CTRL (0x00000391)
1062 @param EAX Lower 32-bits of MSR value.
1063 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.
1064 @param EDX Upper 32-bits of MSR value.
1065 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.
1067 <b>Example usage</b>
1069 MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;
1071 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL);
1072 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);
1074 @note MSR_HASWELL_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.
1076 #define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL 0x00000391
1079 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_CTRL
1083 /// Individual bit fields
1087 /// [Bit 0] Core 0 select.
1089 UINT32 PMI_Sel_Core0
:1;
1091 /// [Bit 1] Core 1 select.
1093 UINT32 PMI_Sel_Core1
:1;
1095 /// [Bit 2] Core 2 select.
1097 UINT32 PMI_Sel_Core2
:1;
1099 /// [Bit 3] Core 3 select.
1101 UINT32 PMI_Sel_Core3
:1;
1102 UINT32 Reserved1
:15;
1103 UINT32 Reserved2
:10;
1105 /// [Bit 29] Enable all uncore counters.
1109 /// [Bit 30] Enable wake on PMI.
1113 /// [Bit 31] Enable Freezing counter when overflow.
1116 UINT32 Reserved3
:32;
1119 /// All bit fields as a 32-bit value
1123 /// All bit fields as a 64-bit value
1126 } MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER
;
1130 Package. Uncore PMU main status.
1132 @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_STATUS (0x00000392)
1133 @param EAX Lower 32-bits of MSR value.
1134 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.
1135 @param EDX Upper 32-bits of MSR value.
1136 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.
1138 <b>Example usage</b>
1140 MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;
1142 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS);
1143 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);
1145 @note MSR_HASWELL_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.
1147 #define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS 0x00000392
1150 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_STATUS
1154 /// Individual bit fields
1158 /// [Bit 0] Fixed counter overflowed.
1162 /// [Bit 1] An ARB counter overflowed.
1167 /// [Bit 3] A CBox counter overflowed (on any slice).
1170 UINT32 Reserved2
:28;
1171 UINT32 Reserved3
:32;
1174 /// All bit fields as a 32-bit value
1178 /// All bit fields as a 64-bit value
1181 } MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER
;
1185 Package. Uncore fixed counter control (R/W).
1187 @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTRL (0x00000394)
1188 @param EAX Lower 32-bits of MSR value.
1189 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.
1190 @param EDX Upper 32-bits of MSR value.
1191 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.
1193 <b>Example usage</b>
1195 MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER Msr;
1197 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL);
1198 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL, Msr.Uint64);
1200 @note MSR_HASWELL_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.
1202 #define MSR_HASWELL_UNC_PERF_FIXED_CTRL 0x00000394
1205 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTRL
1209 /// Individual bit fields
1212 UINT32 Reserved1
:20;
1214 /// [Bit 20] Enable overflow propagation.
1216 UINT32 EnableOverflow
:1;
1219 /// [Bit 22] Enable counting.
1221 UINT32 EnableCounting
:1;
1223 UINT32 Reserved4
:32;
1226 /// All bit fields as a 32-bit value
1230 /// All bit fields as a 64-bit value
1233 } MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER
;
1237 Package. Uncore fixed counter.
1239 @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTR (0x00000395)
1240 @param EAX Lower 32-bits of MSR value.
1241 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.
1242 @param EDX Upper 32-bits of MSR value.
1243 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.
1245 <b>Example usage</b>
1247 MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER Msr;
1249 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR);
1250 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR, Msr.Uint64);
1252 @note MSR_HASWELL_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.
1254 #define MSR_HASWELL_UNC_PERF_FIXED_CTR 0x00000395
1257 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTR
1261 /// Individual bit fields
1265 /// [Bits 31:0] Current count.
1267 UINT32 CurrentCount
:32;
1269 /// [Bits 47:32] Current count.
1271 UINT32 CurrentCountHi
:16;
1275 /// All bit fields as a 64-bit value
1278 } MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER
;
1282 Package. Uncore C-Box configuration information (R/O).
1284 @param ECX MSR_HASWELL_UNC_CBO_CONFIG (0x00000396)
1285 @param EAX Lower 32-bits of MSR value.
1286 Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.
1287 @param EDX Upper 32-bits of MSR value.
1288 Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.
1290 <b>Example usage</b>
1292 MSR_HASWELL_UNC_CBO_CONFIG_REGISTER Msr;
1294 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_CONFIG);
1296 @note MSR_HASWELL_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.
1298 #define MSR_HASWELL_UNC_CBO_CONFIG 0x00000396
1301 MSR information returned for MSR index #MSR_HASWELL_UNC_CBO_CONFIG
1305 /// Individual bit fields
1309 /// [Bits 3:0] Encoded number of C-Box, derive value by "-1".
1312 UINT32 Reserved1
:28;
1313 UINT32 Reserved2
:32;
1316 /// All bit fields as a 32-bit value
1320 /// All bit fields as a 64-bit value
1323 } MSR_HASWELL_UNC_CBO_CONFIG_REGISTER
;
1327 Package. Uncore Arb unit, performance counter 0.
1329 @param ECX MSR_HASWELL_UNC_ARB_PERFCTR0 (0x000003B0)
1330 @param EAX Lower 32-bits of MSR value.
1331 @param EDX Upper 32-bits of MSR value.
1333 <b>Example usage</b>
1337 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0);
1338 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0, Msr);
1340 @note MSR_HASWELL_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.
1342 #define MSR_HASWELL_UNC_ARB_PERFCTR0 0x000003B0
1346 Package. Uncore Arb unit, performance counter 1.
1348 @param ECX MSR_HASWELL_UNC_ARB_PERFCTR1 (0x000003B1)
1349 @param EAX Lower 32-bits of MSR value.
1350 @param EDX Upper 32-bits of MSR value.
1352 <b>Example usage</b>
1356 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1);
1357 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1, Msr);
1359 @note MSR_HASWELL_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.
1361 #define MSR_HASWELL_UNC_ARB_PERFCTR1 0x000003B1
1365 Package. Uncore Arb unit, counter 0 event select MSR.
1367 @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL0 (0x000003B2)
1368 @param EAX Lower 32-bits of MSR value.
1369 @param EDX Upper 32-bits of MSR value.
1371 <b>Example usage</b>
1375 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0);
1376 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0, Msr);
1378 @note MSR_HASWELL_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.
1380 #define MSR_HASWELL_UNC_ARB_PERFEVTSEL0 0x000003B2
1384 Package. Uncore Arb unit, counter 1 event select MSR.
1386 @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL1 (0x000003B3)
1387 @param EAX Lower 32-bits of MSR value.
1388 @param EDX Upper 32-bits of MSR value.
1390 <b>Example usage</b>
1394 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1);
1395 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1, Msr);
1397 @note MSR_HASWELL_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.
1399 #define MSR_HASWELL_UNC_ARB_PERFEVTSEL1 0x000003B3
1403 Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability
1404 Enhancement. Accessible only while in SMM.
1406 @param ECX MSR_HASWELL_SMM_FEATURE_CONTROL (0x000004E0)
1407 @param EAX Lower 32-bits of MSR value.
1408 Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.
1409 @param EDX Upper 32-bits of MSR value.
1410 Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.
1412 <b>Example usage</b>
1414 MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER Msr;
1416 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL);
1417 AsmWriteMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL, Msr.Uint64);
1419 @note MSR_HASWELL_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.
1421 #define MSR_HASWELL_SMM_FEATURE_CONTROL 0x000004E0
1424 MSR information returned for MSR index #MSR_HASWELL_SMM_FEATURE_CONTROL
1428 /// Individual bit fields
1432 /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from
1433 /// further changes.
1438 /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if
1439 /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the
1440 /// logical processors are prevented from executing SMM code outside the
1441 /// ranges defined by the SMRR. When set to '1' any logical processor in
1442 /// the package that attempts to execute SMM code not within the ranges
1443 /// defined by the SMRR will assert an unrecoverable MCE.
1445 UINT32 SMM_Code_Chk_En
:1;
1446 UINT32 Reserved2
:29;
1447 UINT32 Reserved3
:32;
1450 /// All bit fields as a 32-bit value
1454 /// All bit fields as a 64-bit value
1457 } MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER
;
1461 Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical
1462 processors in the package. Available only while in SMM and
1463 MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.
1465 [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
1466 processor of its state in a long flow of internal operation which
1467 delays servicing an interrupt. The corresponding bit will be set at
1468 the start of long events such as: Microcode Update Load, C6, WBINVD,
1469 Ratio Change, Throttle. The bit is automatically cleared at the end of
1470 each long event. The reset value of this field is 0. Only bit
1471 positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be
1474 [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
1475 processor of its state in a long flow of internal operation which
1476 delays servicing an interrupt. The corresponding bit will be set at
1477 the start of long events such as: Microcode Update Load, C6, WBINVD,
1478 Ratio Change, Throttle. The bit is automatically cleared at the end of
1479 each long event. The reset value of this field is 0. Only bit
1480 positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be
1483 @param ECX MSR_HASWELL_SMM_DELAYED (0x000004E2)
1484 @param EAX Lower 32-bits of MSR value.
1485 @param EDX Upper 32-bits of MSR value.
1487 <b>Example usage</b>
1491 Msr = AsmReadMsr64 (MSR_HASWELL_SMM_DELAYED);
1493 @note MSR_HASWELL_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.
1495 #define MSR_HASWELL_SMM_DELAYED 0x000004E2
1499 Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical
1500 processors in the package. Available only while in SMM.
1502 [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
1503 processor of its blocked state to service an SMI. The corresponding
1504 bit will be set if the logical processor is in one of the following
1505 states: Wait For SIPI or SENTER Sleep. The reset value of this field
1506 is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,
1507 ECX=PKG_LVL):EBX[15:0] can be updated.
1510 [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
1511 processor of its blocked state to service an SMI. The corresponding
1512 bit will be set if the logical processor is in one of the following
1513 states: Wait For SIPI or SENTER Sleep. The reset value of this field
1514 is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,
1515 ECX=PKG_LVL):EBX[15:0] can be updated.
1517 @param ECX MSR_HASWELL_SMM_BLOCKED (0x000004E3)
1518 @param EAX Lower 32-bits of MSR value.
1519 @param EDX Upper 32-bits of MSR value.
1521 <b>Example usage</b>
1525 Msr = AsmReadMsr64 (MSR_HASWELL_SMM_BLOCKED);
1527 @note MSR_HASWELL_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.
1529 #define MSR_HASWELL_SMM_BLOCKED 0x000004E3
1533 Package. Unit Multipliers used in RAPL Interfaces (R/O).
1535 @param ECX MSR_HASWELL_RAPL_POWER_UNIT (0x00000606)
1536 @param EAX Lower 32-bits of MSR value.
1537 Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.
1538 @param EDX Upper 32-bits of MSR value.
1539 Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.
1541 <b>Example usage</b>
1543 MSR_HASWELL_RAPL_POWER_UNIT_REGISTER Msr;
1545 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RAPL_POWER_UNIT);
1547 @note MSR_HASWELL_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
1549 #define MSR_HASWELL_RAPL_POWER_UNIT 0x00000606
1552 MSR information returned for MSR index #MSR_HASWELL_RAPL_POWER_UNIT
1556 /// Individual bit fields
1560 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
1562 UINT32 PowerUnits
:4;
1565 /// [Bits 12:8] Package. Energy Status Units Energy related information
1566 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
1567 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
1570 UINT32 EnergyStatusUnits
:5;
1573 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
1577 UINT32 Reserved3
:12;
1578 UINT32 Reserved4
:32;
1581 /// All bit fields as a 32-bit value
1585 /// All bit fields as a 64-bit value
1588 } MSR_HASWELL_RAPL_POWER_UNIT_REGISTER
;
1592 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1595 @param ECX MSR_HASWELL_PP0_ENERGY_STATUS (0x00000639)
1596 @param EAX Lower 32-bits of MSR value.
1597 @param EDX Upper 32-bits of MSR value.
1599 <b>Example usage</b>
1603 Msr = AsmReadMsr64 (MSR_HASWELL_PP0_ENERGY_STATUS);
1605 @note MSR_HASWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
1607 #define MSR_HASWELL_PP0_ENERGY_STATUS 0x00000639
1611 Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
1614 @param ECX MSR_HASWELL_PP1_POWER_LIMIT (0x00000640)
1615 @param EAX Lower 32-bits of MSR value.
1616 @param EDX Upper 32-bits of MSR value.
1618 <b>Example usage</b>
1622 Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POWER_LIMIT);
1623 AsmWriteMsr64 (MSR_HASWELL_PP1_POWER_LIMIT, Msr);
1625 @note MSR_HASWELL_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.
1627 #define MSR_HASWELL_PP1_POWER_LIMIT 0x00000640
1631 Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1634 @param ECX MSR_HASWELL_PP1_ENERGY_STATUS (0x00000641)
1635 @param EAX Lower 32-bits of MSR value.
1636 @param EDX Upper 32-bits of MSR value.
1638 <b>Example usage</b>
1642 Msr = AsmReadMsr64 (MSR_HASWELL_PP1_ENERGY_STATUS);
1644 @note MSR_HASWELL_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.
1646 #define MSR_HASWELL_PP1_ENERGY_STATUS 0x00000641
1650 Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
1653 @param ECX MSR_HASWELL_PP1_POLICY (0x00000642)
1654 @param EAX Lower 32-bits of MSR value.
1655 @param EDX Upper 32-bits of MSR value.
1657 <b>Example usage</b>
1661 Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POLICY);
1662 AsmWriteMsr64 (MSR_HASWELL_PP1_POLICY, Msr);
1664 @note MSR_HASWELL_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.
1666 #define MSR_HASWELL_PP1_POLICY 0x00000642
1670 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
1671 refers to processor core frequency).
1673 @param ECX MSR_HASWELL_CORE_PERF_LIMIT_REASONS (0x00000690)
1674 @param EAX Lower 32-bits of MSR value.
1675 Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.
1676 @param EDX Upper 32-bits of MSR value.
1677 Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.
1679 <b>Example usage</b>
1681 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
1683 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS);
1684 AsmWriteMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
1686 @note MSR_HASWELL_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
1688 #define MSR_HASWELL_CORE_PERF_LIMIT_REASONS 0x00000690
1691 MSR information returned for MSR index #MSR_HASWELL_CORE_PERF_LIMIT_REASONS
1695 /// Individual bit fields
1699 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
1700 /// reduced below the operating system request due to assertion of
1701 /// external PROCHOT.
1703 UINT32 PROCHOT_Status
:1;
1705 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
1706 /// operating system request due to a thermal event.
1708 UINT32 ThermalStatus
:1;
1711 /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced
1712 /// below the operating system request due to Processor Graphics driver
1715 UINT32 GraphicsDriverStatus
:1;
1717 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
1718 /// When set, frequency is reduced below the operating system request
1719 /// because the processor has detected that utilization is low.
1721 UINT32 AutonomousUtilizationBasedFrequencyControlStatus
:1;
1723 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
1724 /// below the operating system request due to a thermal alert from the
1725 /// Voltage Regulator.
1727 UINT32 VRThermAlertStatus
:1;
1730 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
1731 /// reduced below the operating system request due to electrical design
1732 /// point constraints (e.g. maximum electrical current consumption).
1734 UINT32 ElectricalDesignPointStatus
:1;
1736 /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced
1737 /// below the operating system request due to domain-level power limiting.
1741 /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,
1742 /// frequency is reduced below the operating system request due to
1743 /// package-level power limiting PL1.
1747 /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,
1748 /// frequency is reduced below the operating system request due to
1749 /// package-level power limiting PL2.
1753 /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced
1754 /// below the operating system request due to multi-core turbo limits.
1756 UINT32 MaxTurboLimitStatus
:1;
1758 /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency
1759 /// is reduced below the operating system request due to Turbo transition
1760 /// attenuation. This prevents performance degradation due to frequent
1761 /// operating ratio changes.
1763 UINT32 TurboTransitionAttenuationStatus
:1;
1766 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
1767 /// has asserted since the log bit was last cleared. This log bit will
1768 /// remain set until cleared by software writing 0.
1770 UINT32 PROCHOT_Log
:1;
1772 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
1773 /// has asserted since the log bit was last cleared. This log bit will
1774 /// remain set until cleared by software writing 0.
1776 UINT32 ThermalLog
:1;
1779 /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics
1780 /// Driver Status bit has asserted since the log bit was last cleared.
1781 /// This log bit will remain set until cleared by software writing 0.
1783 UINT32 GraphicsDriverLog
:1;
1785 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
1786 /// indicates that the Autonomous Utilization-Based Frequency Control
1787 /// Status bit has asserted since the log bit was last cleared. This log
1788 /// bit will remain set until cleared by software writing 0.
1790 UINT32 AutonomousUtilizationBasedFrequencyControlLog
:1;
1792 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
1793 /// Alert Status bit has asserted since the log bit was last cleared. This
1794 /// log bit will remain set until cleared by software writing 0.
1796 UINT32 VRThermAlertLog
:1;
1799 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
1800 /// Status bit has asserted since the log bit was last cleared. This log
1801 /// bit will remain set until cleared by software writing 0.
1803 UINT32 ElectricalDesignPointLog
:1;
1805 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core
1806 /// Power Limiting Status bit has asserted since the log bit was last
1807 /// cleared. This log bit will remain set until cleared by software
1812 /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates
1813 /// that the Package Level PL1 Power Limiting Status bit has asserted
1814 /// since the log bit was last cleared. This log bit will remain set until
1815 /// cleared by software writing 0.
1819 /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that
1820 /// the Package Level PL2 Power Limiting Status bit has asserted since the
1821 /// log bit was last cleared. This log bit will remain set until cleared
1822 /// by software writing 0.
1826 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
1827 /// Limit Status bit has asserted since the log bit was last cleared. This
1828 /// log bit will remain set until cleared by software writing 0.
1830 UINT32 MaxTurboLimitLog
:1;
1832 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
1833 /// Turbo Transition Attenuation Status bit has asserted since the log bit
1834 /// was last cleared. This log bit will remain set until cleared by
1835 /// software writing 0.
1837 UINT32 TurboTransitionAttenuationLog
:1;
1839 UINT32 Reserved7
:32;
1842 /// All bit fields as a 32-bit value
1846 /// All bit fields as a 64-bit value
1849 } MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER
;
1853 Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)
1854 (frequency refers to processor graphics frequency).
1856 @param ECX MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)
1857 @param EAX Lower 32-bits of MSR value.
1858 Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
1859 @param EDX Upper 32-bits of MSR value.
1860 Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
1862 <b>Example usage</b>
1864 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr;
1866 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS);
1867 AsmWriteMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);
1869 @note MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.
1871 #define MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0
1874 MSR information returned for MSR index
1875 #MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS
1879 /// Individual bit fields
1883 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the
1884 /// operating system request due to assertion of external PROCHOT.
1886 UINT32 PROCHOT_Status
:1;
1888 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
1889 /// operating system request due to a thermal event.
1891 UINT32 ThermalStatus
:1;
1894 /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced
1895 /// below the operating system request due to Processor Graphics driver
1898 UINT32 GraphicsDriverStatus
:1;
1900 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
1901 /// When set, frequency is reduced below the operating system request
1902 /// because the processor has detected that utilization is low.
1904 UINT32 AutonomousUtilizationBasedFrequencyControlStatus
:1;
1906 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
1907 /// below the operating system request due to a thermal alert from the
1908 /// Voltage Regulator.
1910 UINT32 VRThermAlertStatus
:1;
1913 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
1914 /// reduced below the operating system request due to electrical design
1915 /// point constraints (e.g. maximum electrical current consumption).
1917 UINT32 ElectricalDesignPointStatus
:1;
1919 /// [Bit 9] Graphics Power Limiting Status (R0) When set, frequency is
1920 /// reduced below the operating system request due to domain-level power
1923 UINT32 GraphicsPowerLimitingStatus
:1;
1925 /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,
1926 /// frequency is reduced below the operating system request due to
1927 /// package-level power limiting PL1.
1931 /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,
1932 /// frequency is reduced below the operating system request due to
1933 /// package-level power limiting PL2.
1938 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
1939 /// has asserted since the log bit was last cleared. This log bit will
1940 /// remain set until cleared by software writing 0.
1942 UINT32 PROCHOT_Log
:1;
1944 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
1945 /// has asserted since the log bit was last cleared. This log bit will
1946 /// remain set until cleared by software writing 0.
1948 UINT32 ThermalLog
:1;
1951 /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics
1952 /// Driver Status bit has asserted since the log bit was last cleared.
1953 /// This log bit will remain set until cleared by software writing 0.
1955 UINT32 GraphicsDriverLog
:1;
1957 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
1958 /// indicates that the Autonomous Utilization-Based Frequency Control
1959 /// Status bit has asserted since the log bit was last cleared. This log
1960 /// bit will remain set until cleared by software writing 0.
1962 UINT32 AutonomousUtilizationBasedFrequencyControlLog
:1;
1964 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
1965 /// Alert Status bit has asserted since the log bit was last cleared. This
1966 /// log bit will remain set until cleared by software writing 0.
1968 UINT32 VRThermAlertLog
:1;
1971 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
1972 /// Status bit has asserted since the log bit was last cleared. This log
1973 /// bit will remain set until cleared by software writing 0.
1975 UINT32 ElectricalDesignPointLog
:1;
1977 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core
1978 /// Power Limiting Status bit has asserted since the log bit was last
1979 /// cleared. This log bit will remain set until cleared by software
1982 UINT32 CorePowerLimitingLog
:1;
1984 /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates
1985 /// that the Package Level PL1 Power Limiting Status bit has asserted
1986 /// since the log bit was last cleared. This log bit will remain set until
1987 /// cleared by software writing 0.
1991 /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that
1992 /// the Package Level PL2 Power Limiting Status bit has asserted since the
1993 /// log bit was last cleared. This log bit will remain set until cleared
1994 /// by software writing 0.
1998 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
1999 /// Limit Status bit has asserted since the log bit was last cleared. This
2000 /// log bit will remain set until cleared by software writing 0.
2002 UINT32 MaxTurboLimitLog
:1;
2004 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
2005 /// Turbo Transition Attenuation Status bit has asserted since the log bit
2006 /// was last cleared. This log bit will remain set until cleared by
2007 /// software writing 0.
2009 UINT32 TurboTransitionAttenuationLog
:1;
2011 UINT32 Reserved7
:32;
2014 /// All bit fields as a 32-bit value
2018 /// All bit fields as a 64-bit value
2021 } MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER
;
2025 Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)
2026 (frequency refers to ring interconnect in the uncore).
2028 @param ECX MSR_HASWELL_RING_PERF_LIMIT_REASONS (0x000006B1)
2029 @param EAX Lower 32-bits of MSR value.
2030 Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.
2031 @param EDX Upper 32-bits of MSR value.
2032 Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.
2034 <b>Example usage</b>
2036 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER Msr;
2038 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS);
2039 AsmWriteMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS, Msr.Uint64);
2041 @note MSR_HASWELL_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.
2043 #define MSR_HASWELL_RING_PERF_LIMIT_REASONS 0x000006B1
2046 MSR information returned for MSR index #MSR_HASWELL_RING_PERF_LIMIT_REASONS
2050 /// Individual bit fields
2054 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the
2055 /// operating system request due to assertion of external PROCHOT.
2057 UINT32 PROCHOT_Status
:1;
2059 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
2060 /// operating system request due to a thermal event.
2062 UINT32 ThermalStatus
:1;
2065 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
2066 /// below the operating system request due to a thermal alert from the
2067 /// Voltage Regulator.
2069 UINT32 VRThermAlertStatus
:1;
2072 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
2073 /// reduced below the operating system request due to electrical design
2074 /// point constraints (e.g. maximum electrical current consumption).
2076 UINT32 ElectricalDesignPointStatus
:1;
2079 /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,
2080 /// frequency is reduced below the operating system request due to
2081 /// package-level power limiting PL1.
2085 /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,
2086 /// frequency is reduced below the operating system request due to
2087 /// package-level power limiting PL2.
2092 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
2093 /// has asserted since the log bit was last cleared. This log bit will
2094 /// remain set until cleared by software writing 0.
2096 UINT32 PROCHOT_Log
:1;
2098 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
2099 /// has asserted since the log bit was last cleared. This log bit will
2100 /// remain set until cleared by software writing 0.
2102 UINT32 ThermalLog
:1;
2105 /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics
2106 /// Driver Status bit has asserted since the log bit was last cleared.
2107 /// This log bit will remain set until cleared by software writing 0.
2109 UINT32 GraphicsDriverLog
:1;
2111 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
2112 /// indicates that the Autonomous Utilization-Based Frequency Control
2113 /// Status bit has asserted since the log bit was last cleared. This log
2114 /// bit will remain set until cleared by software writing 0.
2116 UINT32 AutonomousUtilizationBasedFrequencyControlLog
:1;
2118 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
2119 /// Alert Status bit has asserted since the log bit was last cleared. This
2120 /// log bit will remain set until cleared by software writing 0.
2122 UINT32 VRThermAlertLog
:1;
2125 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
2126 /// Status bit has asserted since the log bit was last cleared. This log
2127 /// bit will remain set until cleared by software writing 0.
2129 UINT32 ElectricalDesignPointLog
:1;
2131 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core
2132 /// Power Limiting Status bit has asserted since the log bit was last
2133 /// cleared. This log bit will remain set until cleared by software
2136 UINT32 CorePowerLimitingLog
:1;
2138 /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates
2139 /// that the Package Level PL1 Power Limiting Status bit has asserted
2140 /// since the log bit was last cleared. This log bit will remain set until
2141 /// cleared by software writing 0.
2145 /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that
2146 /// the Package Level PL2 Power Limiting Status bit has asserted since the
2147 /// log bit was last cleared. This log bit will remain set until cleared
2148 /// by software writing 0.
2152 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
2153 /// Limit Status bit has asserted since the log bit was last cleared. This
2154 /// log bit will remain set until cleared by software writing 0.
2156 UINT32 MaxTurboLimitLog
:1;
2158 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
2159 /// Turbo Transition Attenuation Status bit has asserted since the log bit
2160 /// was last cleared. This log bit will remain set until cleared by
2161 /// software writing 0.
2163 UINT32 TurboTransitionAttenuationLog
:1;
2165 UINT32 Reserved8
:32;
2168 /// All bit fields as a 32-bit value
2172 /// All bit fields as a 64-bit value
2175 } MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER
;
2179 Package. Uncore C-Box 0, counter 0 event select MSR.
2181 @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 (0x00000700)
2182 @param EAX Lower 32-bits of MSR value.
2183 @param EDX Upper 32-bits of MSR value.
2185 <b>Example usage</b>
2189 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0);
2190 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0, Msr);
2192 @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.
2194 #define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 0x00000700
2198 Package. Uncore C-Box 0, counter 1 event select MSR.
2200 @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 (0x00000701)
2201 @param EAX Lower 32-bits of MSR value.
2202 @param EDX Upper 32-bits of MSR value.
2204 <b>Example usage</b>
2208 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1);
2209 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1, Msr);
2211 @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.
2213 #define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 0x00000701
2217 Package. Uncore C-Box 0, performance counter 0.
2219 @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR0 (0x00000706)
2220 @param EAX Lower 32-bits of MSR value.
2221 @param EDX Upper 32-bits of MSR value.
2223 <b>Example usage</b>
2227 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0);
2228 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0, Msr);
2230 @note MSR_HASWELL_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.
2232 #define MSR_HASWELL_UNC_CBO_0_PERFCTR0 0x00000706
2236 Package. Uncore C-Box 0, performance counter 1.
2238 @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR1 (0x00000707)
2239 @param EAX Lower 32-bits of MSR value.
2240 @param EDX Upper 32-bits of MSR value.
2242 <b>Example usage</b>
2246 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1);
2247 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1, Msr);
2249 @note MSR_HASWELL_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.
2251 #define MSR_HASWELL_UNC_CBO_0_PERFCTR1 0x00000707
2255 Package. Uncore C-Box 1, counter 0 event select MSR.
2257 @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 (0x00000710)
2258 @param EAX Lower 32-bits of MSR value.
2259 @param EDX Upper 32-bits of MSR value.
2261 <b>Example usage</b>
2265 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0);
2266 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0, Msr);
2268 @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.
2270 #define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 0x00000710
2274 Package. Uncore C-Box 1, counter 1 event select MSR.
2276 @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 (0x00000711)
2277 @param EAX Lower 32-bits of MSR value.
2278 @param EDX Upper 32-bits of MSR value.
2280 <b>Example usage</b>
2284 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1);
2285 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1, Msr);
2287 @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.
2289 #define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 0x00000711
2293 Package. Uncore C-Box 1, performance counter 0.
2295 @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR0 (0x00000716)
2296 @param EAX Lower 32-bits of MSR value.
2297 @param EDX Upper 32-bits of MSR value.
2299 <b>Example usage</b>
2303 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0);
2304 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0, Msr);
2306 @note MSR_HASWELL_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.
2308 #define MSR_HASWELL_UNC_CBO_1_PERFCTR0 0x00000716
2312 Package. Uncore C-Box 1, performance counter 1.
2314 @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR1 (0x00000717)
2315 @param EAX Lower 32-bits of MSR value.
2316 @param EDX Upper 32-bits of MSR value.
2318 <b>Example usage</b>
2322 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1);
2323 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1, Msr);
2325 @note MSR_HASWELL_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.
2327 #define MSR_HASWELL_UNC_CBO_1_PERFCTR1 0x00000717
2331 Package. Uncore C-Box 2, counter 0 event select MSR.
2333 @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 (0x00000720)
2334 @param EAX Lower 32-bits of MSR value.
2335 @param EDX Upper 32-bits of MSR value.
2337 <b>Example usage</b>
2341 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0);
2342 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0, Msr);
2344 @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.
2346 #define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 0x00000720
2350 Package. Uncore C-Box 2, counter 1 event select MSR.
2352 @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 (0x00000721)
2353 @param EAX Lower 32-bits of MSR value.
2354 @param EDX Upper 32-bits of MSR value.
2356 <b>Example usage</b>
2360 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1);
2361 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1, Msr);
2363 @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.
2365 #define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 0x00000721
2369 Package. Uncore C-Box 2, performance counter 0.
2371 @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR0 (0x00000726)
2372 @param EAX Lower 32-bits of MSR value.
2373 @param EDX Upper 32-bits of MSR value.
2375 <b>Example usage</b>
2379 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0);
2380 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0, Msr);
2382 @note MSR_HASWELL_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.
2384 #define MSR_HASWELL_UNC_CBO_2_PERFCTR0 0x00000726
2388 Package. Uncore C-Box 2, performance counter 1.
2390 @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR1 (0x00000727)
2391 @param EAX Lower 32-bits of MSR value.
2392 @param EDX Upper 32-bits of MSR value.
2394 <b>Example usage</b>
2398 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1);
2399 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1, Msr);
2401 @note MSR_HASWELL_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.
2403 #define MSR_HASWELL_UNC_CBO_2_PERFCTR1 0x00000727
2407 Package. Uncore C-Box 3, counter 0 event select MSR.
2409 @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 (0x00000730)
2410 @param EAX Lower 32-bits of MSR value.
2411 @param EDX Upper 32-bits of MSR value.
2413 <b>Example usage</b>
2417 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0);
2418 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0, Msr);
2420 @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.
2422 #define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 0x00000730
2426 Package. Uncore C-Box 3, counter 1 event select MSR.
2428 @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 (0x00000731)
2429 @param EAX Lower 32-bits of MSR value.
2430 @param EDX Upper 32-bits of MSR value.
2432 <b>Example usage</b>
2436 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1);
2437 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1, Msr);
2439 @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.
2441 #define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 0x00000731
2445 Package. Uncore C-Box 3, performance counter 0.
2447 @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR0 (0x00000736)
2448 @param EAX Lower 32-bits of MSR value.
2449 @param EDX Upper 32-bits of MSR value.
2451 <b>Example usage</b>
2455 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0);
2456 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0, Msr);
2458 @note MSR_HASWELL_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.
2460 #define MSR_HASWELL_UNC_CBO_3_PERFCTR0 0x00000736
2464 Package. Uncore C-Box 3, performance counter 1.
2466 @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR1 (0x00000737)
2467 @param EAX Lower 32-bits of MSR value.
2468 @param EDX Upper 32-bits of MSR value.
2470 <b>Example usage</b>
2474 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1);
2475 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1, Msr);
2477 @note MSR_HASWELL_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.
2479 #define MSR_HASWELL_UNC_CBO_3_PERFCTR1 0x00000737
2483 Package. Note: C-state values are processor specific C-state code names,
2484 unrelated to MWAIT extension C-state parameters or ACPI C-States.
2486 @param ECX MSR_HASWELL_PKG_C8_RESIDENCY (0x00000630)
2487 @param EAX Lower 32-bits of MSR value.
2488 Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.
2489 @param EDX Upper 32-bits of MSR value.
2490 Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.
2492 <b>Example usage</b>
2494 MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER Msr;
2496 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY);
2497 AsmWriteMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY, Msr.Uint64);
2499 @note MSR_HASWELL_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM.
2501 #define MSR_HASWELL_PKG_C8_RESIDENCY 0x00000630
2504 MSR information returned for MSR index #MSR_HASWELL_PKG_C8_RESIDENCY
2508 /// Individual bit fields
2512 /// [Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset
2513 /// that this package is in processor-specific C8 states. Count at the
2514 /// same frequency as the TSC.
2516 UINT32 C8ResidencyCounter
:32;
2518 /// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last
2519 /// reset that this package is in processor-specific C8 states. Count at
2520 /// the same frequency as the TSC.
2522 UINT32 C8ResidencyCounterHi
:28;
2526 /// All bit fields as a 64-bit value
2529 } MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER
;
2533 Package. Note: C-state values are processor specific C-state code names,
2534 unrelated to MWAIT extension C-state parameters or ACPI C-States.
2536 @param ECX MSR_HASWELL_PKG_C9_RESIDENCY (0x00000631)
2537 @param EAX Lower 32-bits of MSR value.
2538 Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.
2539 @param EDX Upper 32-bits of MSR value.
2540 Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.
2542 <b>Example usage</b>
2544 MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER Msr;
2546 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY);
2547 AsmWriteMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY, Msr.Uint64);
2549 @note MSR_HASWELL_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM.
2551 #define MSR_HASWELL_PKG_C9_RESIDENCY 0x00000631
2554 MSR information returned for MSR index #MSR_HASWELL_PKG_C9_RESIDENCY
2558 /// Individual bit fields
2562 /// [Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset
2563 /// that this package is in processor-specific C9 states. Count at the
2564 /// same frequency as the TSC.
2566 UINT32 C9ResidencyCounter
:32;
2568 /// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last
2569 /// reset that this package is in processor-specific C9 states. Count at
2570 /// the same frequency as the TSC.
2572 UINT32 C9ResidencyCounterHi
:28;
2576 /// All bit fields as a 64-bit value
2579 } MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER
;
2583 Package. Note: C-state values are processor specific C-state code names,
2584 unrelated to MWAIT extension C-state parameters or ACPI C-States.
2586 @param ECX MSR_HASWELL_PKG_C10_RESIDENCY (0x00000632)
2587 @param EAX Lower 32-bits of MSR value.
2588 Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.
2589 @param EDX Upper 32-bits of MSR value.
2590 Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.
2592 <b>Example usage</b>
2594 MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER Msr;
2596 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY);
2597 AsmWriteMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY, Msr.Uint64);
2599 @note MSR_HASWELL_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.
2601 #define MSR_HASWELL_PKG_C10_RESIDENCY 0x00000632
2604 MSR information returned for MSR index #MSR_HASWELL_PKG_C10_RESIDENCY
2608 /// Individual bit fields
2612 /// [Bits 31:0] Package C10 Residency Counter. (R/O) Value since last
2613 /// reset that this package is in processor-specific C10 states. Count at
2614 /// the same frequency as the TSC.
2616 UINT32 C10ResidencyCounter
:32;
2618 /// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last
2619 /// reset that this package is in processor-specific C10 states. Count at
2620 /// the same frequency as the TSC.
2622 UINT32 C10ResidencyCounterHi
:28;
2626 /// All bit fields as a 64-bit value
2629 } MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER
;