2 MSR Definitions for Intel processors based on the Haswell microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
20 May 2018, Volume 4: Model-Specific-Registers (MSR)
24 #ifndef __HASWELL_MSR_H__
25 #define __HASWELL_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Is Intel processors based on the Haswell microarchitecture?
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
38 #define IS_HASWELL_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
41 DisplayModel == 0x3C || \
42 DisplayModel == 0x45 || \
43 DisplayModel == 0x46 \
50 @param ECX MSR_HASWELL_PLATFORM_INFO (0x000000CE)
51 @param EAX Lower 32-bits of MSR value.
52 Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.
53 @param EDX Upper 32-bits of MSR value.
54 Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.
58 MSR_HASWELL_PLATFORM_INFO_REGISTER Msr;
60 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PLATFORM_INFO);
61 AsmWriteMsr64 (MSR_HASWELL_PLATFORM_INFO, Msr.Uint64);
63 @note MSR_HASWELL_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
65 #define MSR_HASWELL_PLATFORM_INFO 0x000000CE
68 MSR information returned for MSR index #MSR_HASWELL_PLATFORM_INFO
72 /// Individual bit fields
77 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
78 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
81 UINT32 MaximumNonTurboRatio
:8;
84 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
85 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
86 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
87 /// Turbo mode is disabled.
91 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
92 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
93 /// and when set to 0, indicates TDP Limit for Turbo mode is not
99 /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,
100 /// indicates that LPM is supported, and when set to 0, indicates LPM is
103 UINT32 LowPowerModeSupport
:1;
105 /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base
106 /// TDP level available. 01: One additional TDP level available. 02: Two
107 /// additional TDP level available. 11: Reserved.
109 UINT32 ConfigTDPLevels
:2;
112 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
113 /// minimum ratio (maximum efficiency) that the processor can operates, in
116 UINT32 MaximumEfficiencyRatio
:8;
118 /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the
119 /// minimum supported operating ratio in units of 100 MHz.
121 UINT32 MinimumOperatingRatio
:8;
125 /// All bit fields as a 64-bit value
128 } MSR_HASWELL_PLATFORM_INFO_REGISTER
;
132 Thread. Performance Event Select for Counter n (R/W) Supports all fields
133 described inTable 2-2 and the fields below.
135 @param ECX MSR_HASWELL_IA32_PERFEVTSELn
136 @param EAX Lower 32-bits of MSR value.
137 Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.
138 @param EDX Upper 32-bits of MSR value.
139 Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.
143 MSR_HASWELL_IA32_PERFEVTSEL_REGISTER Msr;
145 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0);
146 AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0, Msr.Uint64);
148 @note MSR_HASWELL_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.
149 MSR_HASWELL_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.
150 MSR_HASWELL_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.
153 #define MSR_HASWELL_IA32_PERFEVTSEL0 0x00000186
154 #define MSR_HASWELL_IA32_PERFEVTSEL1 0x00000187
155 #define MSR_HASWELL_IA32_PERFEVTSEL3 0x00000189
159 MSR information returned for MSR indexes #MSR_HASWELL_IA32_PERFEVTSEL0,
160 #MSR_HASWELL_IA32_PERFEVTSEL1, and #MSR_HASWELL_IA32_PERFEVTSEL3.
164 /// Individual bit fields
168 /// [Bits 7:0] Event Select: Selects a performance event logic unit.
170 UINT32 EventSelect
:8;
172 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
173 /// detect on the selected event logic.
177 /// [Bit 16] USR: Counts while in privilege level is not ring 0.
181 /// [Bit 17] OS: Counts while in privilege level is ring 0.
185 /// [Bit 18] Edge: Enables edge detection if set.
189 /// [Bit 19] PC: enables pin control.
193 /// [Bit 20] INT: enables interrupt on counter overflow.
197 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
198 /// event conditions occurring across all logical processors sharing a
199 /// processor core. When set to 0, the counter only increments the
200 /// associated event conditions occurring in the logical processor which
201 /// programmed the MSR.
205 /// [Bit 22] EN: enables the corresponding performance counter to commence
206 /// counting when this bit is set.
210 /// [Bit 23] INV: invert the CMASK.
214 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
215 /// performance counter increments each cycle if the event count is
216 /// greater than or equal to the CMASK.
221 /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,
222 /// AnyThread (bit 21) should be cleared to prevent incorrect results.
228 /// All bit fields as a 64-bit value
231 } MSR_HASWELL_IA32_PERFEVTSEL_REGISTER
;
235 Thread. Performance Event Select for Counter 2 (R/W) Supports all fields
236 described inTable 2-2 and the fields below.
238 @param ECX MSR_HASWELL_IA32_PERFEVTSEL2 (0x00000188)
239 @param EAX Lower 32-bits of MSR value.
240 Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.
241 @param EDX Upper 32-bits of MSR value.
242 Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.
246 MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER Msr;
248 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2);
249 AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2, Msr.Uint64);
251 @note MSR_HASWELL_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.
253 #define MSR_HASWELL_IA32_PERFEVTSEL2 0x00000188
256 MSR information returned for MSR index #MSR_HASWELL_IA32_PERFEVTSEL2
260 /// Individual bit fields
264 /// [Bits 7:0] Event Select: Selects a performance event logic unit.
266 UINT32 EventSelect
:8;
268 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
269 /// detect on the selected event logic.
273 /// [Bit 16] USR: Counts while in privilege level is not ring 0.
277 /// [Bit 17] OS: Counts while in privilege level is ring 0.
281 /// [Bit 18] Edge: Enables edge detection if set.
285 /// [Bit 19] PC: enables pin control.
289 /// [Bit 20] INT: enables interrupt on counter overflow.
293 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
294 /// event conditions occurring across all logical processors sharing a
295 /// processor core. When set to 0, the counter only increments the
296 /// associated event conditions occurring in the logical processor which
297 /// programmed the MSR.
301 /// [Bit 22] EN: enables the corresponding performance counter to commence
302 /// counting when this bit is set.
306 /// [Bit 23] INV: invert the CMASK.
310 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
311 /// performance counter increments each cycle if the event count is
312 /// greater than or equal to the CMASK.
317 /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,
318 /// AnyThread (bit 21) should be cleared to prevent incorrect results.
322 /// [Bit 33] IN_TXCP: see Section 18.3.6.5.1 When IN_TXCP=1 & IN_TX=1 and
323 /// in sampling, spurious PMI may occur and transactions may continuously
324 /// abort near overflow conditions. Software should favor using IN_TXCP
325 /// for counting over sampling. If sampling, software should use large
326 /// "sample-after" value after clearing the counter configured to use
327 /// IN_TXCP and also always reset the counter even when no overflow
328 /// condition was reported.
334 /// All bit fields as a 64-bit value
337 } MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER
;
341 Thread. Last Branch Record Filtering Select Register (R/W).
343 @param ECX MSR_HASWELL_LBR_SELECT (0x000001C8)
344 @param EAX Lower 32-bits of MSR value.
345 Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.
346 @param EDX Upper 32-bits of MSR value.
347 Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.
351 MSR_HASWELL_LBR_SELECT_REGISTER Msr;
353 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_LBR_SELECT);
354 AsmWriteMsr64 (MSR_HASWELL_LBR_SELECT, Msr.Uint64);
356 @note MSR_HASWELL_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
358 #define MSR_HASWELL_LBR_SELECT 0x000001C8
361 MSR information returned for MSR index #MSR_HASWELL_LBR_SELECT
365 /// Individual bit fields
369 /// [Bit 0] CPL_EQ_0.
373 /// [Bit 1] CPL_NEQ_0.
381 /// [Bit 3] NEAR_REL_CALL.
383 UINT32 NEAR_REL_CALL
:1;
385 /// [Bit 4] NEAR_IND_CALL.
387 UINT32 NEAR_IND_CALL
:1;
389 /// [Bit 5] NEAR_RET.
393 /// [Bit 6] NEAR_IND_JMP.
395 UINT32 NEAR_IND_JMP
:1;
397 /// [Bit 7] NEAR_REL_JMP.
399 UINT32 NEAR_REL_JMP
:1;
401 /// [Bit 8] FAR_BRANCH.
405 /// [Bit 9] EN_CALL_STACK.
407 UINT32 EN_CALL_STACK
:1;
412 /// All bit fields as a 32-bit value
416 /// All bit fields as a 64-bit value
419 } MSR_HASWELL_LBR_SELECT_REGISTER
;
423 Package. Package C6/C7 Interrupt Response Limit 1 (R/W) This MSR defines
424 the interrupt response time limit used by the processor to manage transition
425 to package C6 or C7 state. The latency programmed in this register is for
426 the shorter-latency sub C-states used by an MWAIT hint to C6 or C7 state.
427 Note: C-state values are processor specific C-state code names, unrelated to
428 MWAIT extension C-state parameters or ACPI C-States.
430 @param ECX MSR_HASWELL_PKGC_IRTL1 (0x0000060B)
431 @param EAX Lower 32-bits of MSR value.
432 Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.
433 @param EDX Upper 32-bits of MSR value.
434 Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.
438 MSR_HASWELL_PKGC_IRTL1_REGISTER Msr;
440 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL1);
441 AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL1, Msr.Uint64);
443 @note MSR_HASWELL_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.
445 #define MSR_HASWELL_PKGC_IRTL1 0x0000060B
448 MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL1
452 /// Individual bit fields
456 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
457 /// that should be used to decide if the package should be put into a
458 /// package C6 or C7 state.
460 UINT32 InterruptResponseTimeLimit
:10;
462 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
463 /// of the interrupt response time limit. See Table 2-19 for supported
464 /// time unit encodings.
469 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
470 /// valid and can be used by the processor for package C-sate management.
477 /// All bit fields as a 32-bit value
481 /// All bit fields as a 64-bit value
484 } MSR_HASWELL_PKGC_IRTL1_REGISTER
;
488 Package. Package C6/C7 Interrupt Response Limit 2 (R/W) This MSR defines
489 the interrupt response time limit used by the processor to manage transition
490 to package C6 or C7 state. The latency programmed in this register is for
491 the longer-latency sub Cstates used by an MWAIT hint to C6 or C7 state.
492 Note: C-state values are processor specific C-state code names, unrelated to
493 MWAIT extension C-state parameters or ACPI C-States.
495 @param ECX MSR_HASWELL_PKGC_IRTL2 (0x0000060C)
496 @param EAX Lower 32-bits of MSR value.
497 Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.
498 @param EDX Upper 32-bits of MSR value.
499 Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.
503 MSR_HASWELL_PKGC_IRTL2_REGISTER Msr;
505 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL2);
506 AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL2, Msr.Uint64);
508 @note MSR_HASWELL_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.
510 #define MSR_HASWELL_PKGC_IRTL2 0x0000060C
513 MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL2
517 /// Individual bit fields
521 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
522 /// that should be used to decide if the package should be put into a
523 /// package C6 or C7 state.
525 UINT32 InterruptResponseTimeLimit
:10;
527 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
528 /// of the interrupt response time limit. See Table 2-19 for supported
529 /// time unit encodings.
534 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
535 /// valid and can be used by the processor for package C-sate management.
542 /// All bit fields as a 32-bit value
546 /// All bit fields as a 64-bit value
549 } MSR_HASWELL_PKGC_IRTL2_REGISTER
;
553 Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
555 @param ECX MSR_HASWELL_PKG_PERF_STATUS (0x00000613)
556 @param EAX Lower 32-bits of MSR value.
557 @param EDX Upper 32-bits of MSR value.
563 Msr = AsmReadMsr64 (MSR_HASWELL_PKG_PERF_STATUS);
565 @note MSR_HASWELL_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
567 #define MSR_HASWELL_PKG_PERF_STATUS 0x00000613
571 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
573 @param ECX MSR_HASWELL_DRAM_ENERGY_STATUS (0x00000619)
574 @param EAX Lower 32-bits of MSR value.
575 @param EDX Upper 32-bits of MSR value.
581 Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_ENERGY_STATUS);
583 @note MSR_HASWELL_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
585 #define MSR_HASWELL_DRAM_ENERGY_STATUS 0x00000619
589 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
592 @param ECX MSR_HASWELL_DRAM_PERF_STATUS (0x0000061B)
593 @param EAX Lower 32-bits of MSR value.
594 @param EDX Upper 32-bits of MSR value.
600 Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_PERF_STATUS);
602 @note MSR_HASWELL_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
604 #define MSR_HASWELL_DRAM_PERF_STATUS 0x0000061B
608 Package. Base TDP Ratio (R/O).
610 @param ECX MSR_HASWELL_CONFIG_TDP_NOMINAL (0x00000648)
611 @param EAX Lower 32-bits of MSR value.
612 Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.
613 @param EDX Upper 32-bits of MSR value.
614 Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.
618 MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER Msr;
620 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_NOMINAL);
622 @note MSR_HASWELL_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
624 #define MSR_HASWELL_CONFIG_TDP_NOMINAL 0x00000648
627 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_NOMINAL
631 /// Individual bit fields
635 /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this
636 /// specific processor (in units of 100 MHz).
638 UINT32 Config_TDP_Base
:8;
643 /// All bit fields as a 32-bit value
647 /// All bit fields as a 64-bit value
650 } MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER
;
654 Package. ConfigTDP Level 1 ratio and power level (R/O).
656 @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL1 (0x00000649)
657 @param EAX Lower 32-bits of MSR value.
658 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.
659 @param EDX Upper 32-bits of MSR value.
660 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.
664 MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER Msr;
666 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL1);
668 @note MSR_HASWELL_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
670 #define MSR_HASWELL_CONFIG_TDP_LEVEL1 0x00000649
673 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL1
677 /// Individual bit fields
681 /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.
683 UINT32 PKG_TDP_LVL1
:15;
686 /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used
687 /// for this specific processor.
689 UINT32 Config_TDP_LVL1_Ratio
:8;
692 /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP
695 UINT32 PKG_MAX_PWR_LVL1
:15;
697 /// [Bits 62:47] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP
700 UINT32 PKG_MIN_PWR_LVL1
:16;
704 /// All bit fields as a 64-bit value
707 } MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER
;
711 Package. ConfigTDP Level 2 ratio and power level (R/O).
713 @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL2 (0x0000064A)
714 @param EAX Lower 32-bits of MSR value.
715 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.
716 @param EDX Upper 32-bits of MSR value.
717 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.
721 MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER Msr;
723 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL2);
725 @note MSR_HASWELL_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
727 #define MSR_HASWELL_CONFIG_TDP_LEVEL2 0x0000064A
730 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL2
734 /// Individual bit fields
738 /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.
740 UINT32 PKG_TDP_LVL2
:15;
743 /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used
744 /// for this specific processor.
746 UINT32 Config_TDP_LVL2_Ratio
:8;
749 /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP
752 UINT32 PKG_MAX_PWR_LVL2
:15;
754 /// [Bits 62:47] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP
757 UINT32 PKG_MIN_PWR_LVL2
:16;
761 /// All bit fields as a 64-bit value
764 } MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER
;
768 Package. ConfigTDP Control (R/W).
770 @param ECX MSR_HASWELL_CONFIG_TDP_CONTROL (0x0000064B)
771 @param EAX Lower 32-bits of MSR value.
772 Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.
773 @param EDX Upper 32-bits of MSR value.
774 Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.
778 MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER Msr;
780 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL);
781 AsmWriteMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL, Msr.Uint64);
783 @note MSR_HASWELL_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
785 #define MSR_HASWELL_CONFIG_TDP_CONTROL 0x0000064B
788 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_CONTROL
792 /// Individual bit fields
796 /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.
801 /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of
802 /// this register is locked until a reset.
804 UINT32 Config_TDP_Lock
:1;
808 /// All bit fields as a 32-bit value
812 /// All bit fields as a 64-bit value
815 } MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER
;
819 Package. ConfigTDP Control (R/W).
821 @param ECX MSR_HASWELL_TURBO_ACTIVATION_RATIO (0x0000064C)
822 @param EAX Lower 32-bits of MSR value.
823 Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.
824 @param EDX Upper 32-bits of MSR value.
825 Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.
829 MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER Msr;
831 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO);
832 AsmWriteMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO, Msr.Uint64);
834 @note MSR_HASWELL_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
836 #define MSR_HASWELL_TURBO_ACTIVATION_RATIO 0x0000064C
839 MSR information returned for MSR index #MSR_HASWELL_TURBO_ACTIVATION_RATIO
843 /// Individual bit fields
847 /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this
850 UINT32 MAX_NON_TURBO_RATIO
:8;
853 /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the
854 /// content of this register is locked until a reset.
856 UINT32 TURBO_ACTIVATION_RATIO_Lock
:1;
860 /// All bit fields as a 32-bit value
864 /// All bit fields as a 64-bit value
867 } MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER
;
871 Core. C-State Configuration Control (R/W) Note: C-state values are processor
872 specific C-state code names, unrelated to MWAIT extension C-state parameters
873 or ACPI Cstates. `See http://biosbits.org. <http://biosbits.org>`__.
875 @param ECX MSR_HASWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)
876 @param EAX Lower 32-bits of MSR value.
877 Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
878 @param EDX Upper 32-bits of MSR value.
879 Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
883 MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
885 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL);
886 AsmWriteMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
888 @note MSR_HASWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
890 #define MSR_HASWELL_PKG_CST_CONFIG_CONTROL 0x000000E2
893 MSR information returned for MSR index #MSR_HASWELL_PKG_CST_CONFIG_CONTROL
897 /// Individual bit fields
901 /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest
902 /// processor-specific C-state code name (consuming the least power) for
903 /// the package. The default is set as factory-configured package C-state
904 /// limit. The following C-state code name encodings are supported: 0000b:
905 /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6
906 /// 0100b: C7 0101b: C7s Package C states C7 are not available to
907 /// processor with signature 06_3CH.
912 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
917 /// [Bit 15] CFG Lock (R/WO).
922 /// [Bit 25] C3 State Auto Demotion Enable (R/W).
924 UINT32 C3AutoDemotion
:1;
926 /// [Bit 26] C1 State Auto Demotion Enable (R/W).
928 UINT32 C1AutoDemotion
:1;
930 /// [Bit 27] Enable C3 Undemotion (R/W).
932 UINT32 C3Undemotion
:1;
934 /// [Bit 28] Enable C1 Undemotion (R/W).
936 UINT32 C1Undemotion
:1;
941 /// All bit fields as a 32-bit value
945 /// All bit fields as a 64-bit value
948 } MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER
;
952 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
953 Enhancement. Accessible only while in SMM.
955 @param ECX MSR_HASWELL_SMM_MCA_CAP (0x0000017D)
956 @param EAX Lower 32-bits of MSR value.
957 Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.
958 @param EDX Upper 32-bits of MSR value.
959 Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.
963 MSR_HASWELL_SMM_MCA_CAP_REGISTER Msr;
965 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_MCA_CAP);
966 AsmWriteMsr64 (MSR_HASWELL_SMM_MCA_CAP, Msr.Uint64);
968 @note MSR_HASWELL_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
970 #define MSR_HASWELL_SMM_MCA_CAP 0x0000017D
973 MSR information returned for MSR index #MSR_HASWELL_SMM_MCA_CAP
977 /// Individual bit fields
983 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
984 /// SMM code access restriction is supported and the
985 /// MSR_SMM_FEATURE_CONTROL is supported.
987 UINT32 SMM_Code_Access_Chk
:1;
989 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
990 /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is
993 UINT32 Long_Flow_Indication
:1;
997 /// All bit fields as a 64-bit value
1000 } MSR_HASWELL_SMM_MCA_CAP_REGISTER
;
1004 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
1005 RW if MSR_PLATFORM_INFO.[28] = 1.
1007 @param ECX MSR_HASWELL_TURBO_RATIO_LIMIT (0x000001AD)
1008 @param EAX Lower 32-bits of MSR value.
1009 Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.
1010 @param EDX Upper 32-bits of MSR value.
1011 Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.
1013 <b>Example usage</b>
1015 MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER Msr;
1017 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_RATIO_LIMIT);
1019 @note MSR_HASWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
1021 #define MSR_HASWELL_TURBO_RATIO_LIMIT 0x000001AD
1024 MSR information returned for MSR index #MSR_HASWELL_TURBO_RATIO_LIMIT
1028 /// Individual bit fields
1032 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
1033 /// limit of 1 core active.
1037 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
1038 /// limit of 2 core active.
1042 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
1043 /// limit of 3 core active.
1047 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
1048 /// limit of 4 core active.
1054 /// All bit fields as a 32-bit value
1058 /// All bit fields as a 64-bit value
1061 } MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER
;
1065 Package. Uncore PMU global control.
1067 @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_CTRL (0x00000391)
1068 @param EAX Lower 32-bits of MSR value.
1069 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.
1070 @param EDX Upper 32-bits of MSR value.
1071 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.
1073 <b>Example usage</b>
1075 MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;
1077 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL);
1078 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);
1080 @note MSR_HASWELL_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.
1082 #define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL 0x00000391
1085 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_CTRL
1089 /// Individual bit fields
1093 /// [Bit 0] Core 0 select.
1095 UINT32 PMI_Sel_Core0
:1;
1097 /// [Bit 1] Core 1 select.
1099 UINT32 PMI_Sel_Core1
:1;
1101 /// [Bit 2] Core 2 select.
1103 UINT32 PMI_Sel_Core2
:1;
1105 /// [Bit 3] Core 3 select.
1107 UINT32 PMI_Sel_Core3
:1;
1108 UINT32 Reserved1
:15;
1109 UINT32 Reserved2
:10;
1111 /// [Bit 29] Enable all uncore counters.
1115 /// [Bit 30] Enable wake on PMI.
1119 /// [Bit 31] Enable Freezing counter when overflow.
1122 UINT32 Reserved3
:32;
1125 /// All bit fields as a 32-bit value
1129 /// All bit fields as a 64-bit value
1132 } MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER
;
1136 Package. Uncore PMU main status.
1138 @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_STATUS (0x00000392)
1139 @param EAX Lower 32-bits of MSR value.
1140 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.
1141 @param EDX Upper 32-bits of MSR value.
1142 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.
1144 <b>Example usage</b>
1146 MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;
1148 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS);
1149 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);
1151 @note MSR_HASWELL_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.
1153 #define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS 0x00000392
1156 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_STATUS
1160 /// Individual bit fields
1164 /// [Bit 0] Fixed counter overflowed.
1168 /// [Bit 1] An ARB counter overflowed.
1173 /// [Bit 3] A CBox counter overflowed (on any slice).
1176 UINT32 Reserved2
:28;
1177 UINT32 Reserved3
:32;
1180 /// All bit fields as a 32-bit value
1184 /// All bit fields as a 64-bit value
1187 } MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER
;
1191 Package. Uncore fixed counter control (R/W).
1193 @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTRL (0x00000394)
1194 @param EAX Lower 32-bits of MSR value.
1195 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.
1196 @param EDX Upper 32-bits of MSR value.
1197 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.
1199 <b>Example usage</b>
1201 MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER Msr;
1203 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL);
1204 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL, Msr.Uint64);
1206 @note MSR_HASWELL_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.
1208 #define MSR_HASWELL_UNC_PERF_FIXED_CTRL 0x00000394
1211 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTRL
1215 /// Individual bit fields
1218 UINT32 Reserved1
:20;
1220 /// [Bit 20] Enable overflow propagation.
1222 UINT32 EnableOverflow
:1;
1225 /// [Bit 22] Enable counting.
1227 UINT32 EnableCounting
:1;
1229 UINT32 Reserved4
:32;
1232 /// All bit fields as a 32-bit value
1236 /// All bit fields as a 64-bit value
1239 } MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER
;
1243 Package. Uncore fixed counter.
1245 @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTR (0x00000395)
1246 @param EAX Lower 32-bits of MSR value.
1247 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.
1248 @param EDX Upper 32-bits of MSR value.
1249 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.
1251 <b>Example usage</b>
1253 MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER Msr;
1255 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR);
1256 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR, Msr.Uint64);
1258 @note MSR_HASWELL_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.
1260 #define MSR_HASWELL_UNC_PERF_FIXED_CTR 0x00000395
1263 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTR
1267 /// Individual bit fields
1271 /// [Bits 31:0] Current count.
1273 UINT32 CurrentCount
:32;
1275 /// [Bits 47:32] Current count.
1277 UINT32 CurrentCountHi
:16;
1281 /// All bit fields as a 64-bit value
1284 } MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER
;
1288 Package. Uncore C-Box configuration information (R/O).
1290 @param ECX MSR_HASWELL_UNC_CBO_CONFIG (0x00000396)
1291 @param EAX Lower 32-bits of MSR value.
1292 Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.
1293 @param EDX Upper 32-bits of MSR value.
1294 Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.
1296 <b>Example usage</b>
1298 MSR_HASWELL_UNC_CBO_CONFIG_REGISTER Msr;
1300 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_CONFIG);
1302 @note MSR_HASWELL_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.
1304 #define MSR_HASWELL_UNC_CBO_CONFIG 0x00000396
1307 MSR information returned for MSR index #MSR_HASWELL_UNC_CBO_CONFIG
1311 /// Individual bit fields
1315 /// [Bits 3:0] Encoded number of C-Box, derive value by "-1".
1318 UINT32 Reserved1
:28;
1319 UINT32 Reserved2
:32;
1322 /// All bit fields as a 32-bit value
1326 /// All bit fields as a 64-bit value
1329 } MSR_HASWELL_UNC_CBO_CONFIG_REGISTER
;
1333 Package. Uncore Arb unit, performance counter 0.
1335 @param ECX MSR_HASWELL_UNC_ARB_PERFCTR0 (0x000003B0)
1336 @param EAX Lower 32-bits of MSR value.
1337 @param EDX Upper 32-bits of MSR value.
1339 <b>Example usage</b>
1343 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0);
1344 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0, Msr);
1346 @note MSR_HASWELL_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.
1348 #define MSR_HASWELL_UNC_ARB_PERFCTR0 0x000003B0
1352 Package. Uncore Arb unit, performance counter 1.
1354 @param ECX MSR_HASWELL_UNC_ARB_PERFCTR1 (0x000003B1)
1355 @param EAX Lower 32-bits of MSR value.
1356 @param EDX Upper 32-bits of MSR value.
1358 <b>Example usage</b>
1362 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1);
1363 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1, Msr);
1365 @note MSR_HASWELL_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.
1367 #define MSR_HASWELL_UNC_ARB_PERFCTR1 0x000003B1
1371 Package. Uncore Arb unit, counter 0 event select MSR.
1373 @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL0 (0x000003B2)
1374 @param EAX Lower 32-bits of MSR value.
1375 @param EDX Upper 32-bits of MSR value.
1377 <b>Example usage</b>
1381 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0);
1382 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0, Msr);
1384 @note MSR_HASWELL_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.
1386 #define MSR_HASWELL_UNC_ARB_PERFEVTSEL0 0x000003B2
1390 Package. Uncore Arb unit, counter 1 event select MSR.
1392 @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL1 (0x000003B3)
1393 @param EAX Lower 32-bits of MSR value.
1394 @param EDX Upper 32-bits of MSR value.
1396 <b>Example usage</b>
1400 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1);
1401 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1, Msr);
1403 @note MSR_HASWELL_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.
1405 #define MSR_HASWELL_UNC_ARB_PERFEVTSEL1 0x000003B3
1409 Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability
1410 Enhancement. Accessible only while in SMM.
1412 @param ECX MSR_HASWELL_SMM_FEATURE_CONTROL (0x000004E0)
1413 @param EAX Lower 32-bits of MSR value.
1414 Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.
1415 @param EDX Upper 32-bits of MSR value.
1416 Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.
1418 <b>Example usage</b>
1420 MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER Msr;
1422 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL);
1423 AsmWriteMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL, Msr.Uint64);
1425 @note MSR_HASWELL_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.
1427 #define MSR_HASWELL_SMM_FEATURE_CONTROL 0x000004E0
1430 MSR information returned for MSR index #MSR_HASWELL_SMM_FEATURE_CONTROL
1434 /// Individual bit fields
1438 /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from
1439 /// further changes.
1444 /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if
1445 /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the
1446 /// logical processors are prevented from executing SMM code outside the
1447 /// ranges defined by the SMRR. When set to '1' any logical processor in
1448 /// the package that attempts to execute SMM code not within the ranges
1449 /// defined by the SMRR will assert an unrecoverable MCE.
1451 UINT32 SMM_Code_Chk_En
:1;
1452 UINT32 Reserved2
:29;
1453 UINT32 Reserved3
:32;
1456 /// All bit fields as a 32-bit value
1460 /// All bit fields as a 64-bit value
1463 } MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER
;
1467 Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical
1468 processors in the package. Available only while in SMM and
1469 MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.
1471 [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
1472 processor of its state in a long flow of internal operation which
1473 delays servicing an interrupt. The corresponding bit will be set at
1474 the start of long events such as: Microcode Update Load, C6, WBINVD,
1475 Ratio Change, Throttle. The bit is automatically cleared at the end of
1476 each long event. The reset value of this field is 0. Only bit
1477 positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be
1480 [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
1481 processor of its state in a long flow of internal operation which
1482 delays servicing an interrupt. The corresponding bit will be set at
1483 the start of long events such as: Microcode Update Load, C6, WBINVD,
1484 Ratio Change, Throttle. The bit is automatically cleared at the end of
1485 each long event. The reset value of this field is 0. Only bit
1486 positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be
1489 @param ECX MSR_HASWELL_SMM_DELAYED (0x000004E2)
1490 @param EAX Lower 32-bits of MSR value.
1491 @param EDX Upper 32-bits of MSR value.
1493 <b>Example usage</b>
1497 Msr = AsmReadMsr64 (MSR_HASWELL_SMM_DELAYED);
1499 @note MSR_HASWELL_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.
1501 #define MSR_HASWELL_SMM_DELAYED 0x000004E2
1505 Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical
1506 processors in the package. Available only while in SMM.
1508 [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
1509 processor of its blocked state to service an SMI. The corresponding
1510 bit will be set if the logical processor is in one of the following
1511 states: Wait For SIPI or SENTER Sleep. The reset value of this field
1512 is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,
1513 ECX=PKG_LVL):EBX[15:0] can be updated.
1516 [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
1517 processor of its blocked state to service an SMI. The corresponding
1518 bit will be set if the logical processor is in one of the following
1519 states: Wait For SIPI or SENTER Sleep. The reset value of this field
1520 is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,
1521 ECX=PKG_LVL):EBX[15:0] can be updated.
1523 @param ECX MSR_HASWELL_SMM_BLOCKED (0x000004E3)
1524 @param EAX Lower 32-bits of MSR value.
1525 @param EDX Upper 32-bits of MSR value.
1527 <b>Example usage</b>
1531 Msr = AsmReadMsr64 (MSR_HASWELL_SMM_BLOCKED);
1533 @note MSR_HASWELL_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.
1535 #define MSR_HASWELL_SMM_BLOCKED 0x000004E3
1539 Package. Unit Multipliers used in RAPL Interfaces (R/O).
1541 @param ECX MSR_HASWELL_RAPL_POWER_UNIT (0x00000606)
1542 @param EAX Lower 32-bits of MSR value.
1543 Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.
1544 @param EDX Upper 32-bits of MSR value.
1545 Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.
1547 <b>Example usage</b>
1549 MSR_HASWELL_RAPL_POWER_UNIT_REGISTER Msr;
1551 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RAPL_POWER_UNIT);
1553 @note MSR_HASWELL_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
1555 #define MSR_HASWELL_RAPL_POWER_UNIT 0x00000606
1558 MSR information returned for MSR index #MSR_HASWELL_RAPL_POWER_UNIT
1562 /// Individual bit fields
1566 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
1568 UINT32 PowerUnits
:4;
1571 /// [Bits 12:8] Package. Energy Status Units Energy related information
1572 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
1573 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
1576 UINT32 EnergyStatusUnits
:5;
1579 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
1583 UINT32 Reserved3
:12;
1584 UINT32 Reserved4
:32;
1587 /// All bit fields as a 32-bit value
1591 /// All bit fields as a 64-bit value
1594 } MSR_HASWELL_RAPL_POWER_UNIT_REGISTER
;
1598 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1601 @param ECX MSR_HASWELL_PP0_ENERGY_STATUS (0x00000639)
1602 @param EAX Lower 32-bits of MSR value.
1603 @param EDX Upper 32-bits of MSR value.
1605 <b>Example usage</b>
1609 Msr = AsmReadMsr64 (MSR_HASWELL_PP0_ENERGY_STATUS);
1611 @note MSR_HASWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
1613 #define MSR_HASWELL_PP0_ENERGY_STATUS 0x00000639
1617 Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
1620 @param ECX MSR_HASWELL_PP1_POWER_LIMIT (0x00000640)
1621 @param EAX Lower 32-bits of MSR value.
1622 @param EDX Upper 32-bits of MSR value.
1624 <b>Example usage</b>
1628 Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POWER_LIMIT);
1629 AsmWriteMsr64 (MSR_HASWELL_PP1_POWER_LIMIT, Msr);
1631 @note MSR_HASWELL_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.
1633 #define MSR_HASWELL_PP1_POWER_LIMIT 0x00000640
1637 Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1640 @param ECX MSR_HASWELL_PP1_ENERGY_STATUS (0x00000641)
1641 @param EAX Lower 32-bits of MSR value.
1642 @param EDX Upper 32-bits of MSR value.
1644 <b>Example usage</b>
1648 Msr = AsmReadMsr64 (MSR_HASWELL_PP1_ENERGY_STATUS);
1650 @note MSR_HASWELL_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.
1652 #define MSR_HASWELL_PP1_ENERGY_STATUS 0x00000641
1656 Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
1659 @param ECX MSR_HASWELL_PP1_POLICY (0x00000642)
1660 @param EAX Lower 32-bits of MSR value.
1661 @param EDX Upper 32-bits of MSR value.
1663 <b>Example usage</b>
1667 Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POLICY);
1668 AsmWriteMsr64 (MSR_HASWELL_PP1_POLICY, Msr);
1670 @note MSR_HASWELL_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.
1672 #define MSR_HASWELL_PP1_POLICY 0x00000642
1676 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
1677 refers to processor core frequency).
1679 @param ECX MSR_HASWELL_CORE_PERF_LIMIT_REASONS (0x00000690)
1680 @param EAX Lower 32-bits of MSR value.
1681 Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.
1682 @param EDX Upper 32-bits of MSR value.
1683 Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.
1685 <b>Example usage</b>
1687 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
1689 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS);
1690 AsmWriteMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
1692 @note MSR_HASWELL_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
1694 #define MSR_HASWELL_CORE_PERF_LIMIT_REASONS 0x00000690
1697 MSR information returned for MSR index #MSR_HASWELL_CORE_PERF_LIMIT_REASONS
1701 /// Individual bit fields
1705 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
1706 /// reduced below the operating system request due to assertion of
1707 /// external PROCHOT.
1709 UINT32 PROCHOT_Status
:1;
1711 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
1712 /// operating system request due to a thermal event.
1714 UINT32 ThermalStatus
:1;
1717 /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced
1718 /// below the operating system request due to Processor Graphics driver
1721 UINT32 GraphicsDriverStatus
:1;
1723 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
1724 /// When set, frequency is reduced below the operating system request
1725 /// because the processor has detected that utilization is low.
1727 UINT32 AutonomousUtilizationBasedFrequencyControlStatus
:1;
1729 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
1730 /// below the operating system request due to a thermal alert from the
1731 /// Voltage Regulator.
1733 UINT32 VRThermAlertStatus
:1;
1736 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
1737 /// reduced below the operating system request due to electrical design
1738 /// point constraints (e.g. maximum electrical current consumption).
1740 UINT32 ElectricalDesignPointStatus
:1;
1742 /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced
1743 /// below the operating system request due to domain-level power limiting.
1747 /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,
1748 /// frequency is reduced below the operating system request due to
1749 /// package-level power limiting PL1.
1753 /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,
1754 /// frequency is reduced below the operating system request due to
1755 /// package-level power limiting PL2.
1759 /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced
1760 /// below the operating system request due to multi-core turbo limits.
1762 UINT32 MaxTurboLimitStatus
:1;
1764 /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency
1765 /// is reduced below the operating system request due to Turbo transition
1766 /// attenuation. This prevents performance degradation due to frequent
1767 /// operating ratio changes.
1769 UINT32 TurboTransitionAttenuationStatus
:1;
1772 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
1773 /// has asserted since the log bit was last cleared. This log bit will
1774 /// remain set until cleared by software writing 0.
1776 UINT32 PROCHOT_Log
:1;
1778 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
1779 /// has asserted since the log bit was last cleared. This log bit will
1780 /// remain set until cleared by software writing 0.
1782 UINT32 ThermalLog
:1;
1785 /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics
1786 /// Driver Status bit has asserted since the log bit was last cleared.
1787 /// This log bit will remain set until cleared by software writing 0.
1789 UINT32 GraphicsDriverLog
:1;
1791 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
1792 /// indicates that the Autonomous Utilization-Based Frequency Control
1793 /// Status bit has asserted since the log bit was last cleared. This log
1794 /// bit will remain set until cleared by software writing 0.
1796 UINT32 AutonomousUtilizationBasedFrequencyControlLog
:1;
1798 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
1799 /// Alert Status bit has asserted since the log bit was last cleared. This
1800 /// log bit will remain set until cleared by software writing 0.
1802 UINT32 VRThermAlertLog
:1;
1805 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
1806 /// Status bit has asserted since the log bit was last cleared. This log
1807 /// bit will remain set until cleared by software writing 0.
1809 UINT32 ElectricalDesignPointLog
:1;
1811 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core
1812 /// Power Limiting Status bit has asserted since the log bit was last
1813 /// cleared. This log bit will remain set until cleared by software
1818 /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates
1819 /// that the Package Level PL1 Power Limiting Status bit has asserted
1820 /// since the log bit was last cleared. This log bit will remain set until
1821 /// cleared by software writing 0.
1825 /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that
1826 /// the Package Level PL2 Power Limiting Status bit has asserted since the
1827 /// log bit was last cleared. This log bit will remain set until cleared
1828 /// by software writing 0.
1832 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
1833 /// Limit Status bit has asserted since the log bit was last cleared. This
1834 /// log bit will remain set until cleared by software writing 0.
1836 UINT32 MaxTurboLimitLog
:1;
1838 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
1839 /// Turbo Transition Attenuation Status bit has asserted since the log bit
1840 /// was last cleared. This log bit will remain set until cleared by
1841 /// software writing 0.
1843 UINT32 TurboTransitionAttenuationLog
:1;
1845 UINT32 Reserved7
:32;
1848 /// All bit fields as a 32-bit value
1852 /// All bit fields as a 64-bit value
1855 } MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER
;
1859 Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)
1860 (frequency refers to processor graphics frequency).
1862 @param ECX MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)
1863 @param EAX Lower 32-bits of MSR value.
1864 Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
1865 @param EDX Upper 32-bits of MSR value.
1866 Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
1868 <b>Example usage</b>
1870 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr;
1872 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS);
1873 AsmWriteMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);
1875 @note MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.
1877 #define MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0
1880 MSR information returned for MSR index
1881 #MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS
1885 /// Individual bit fields
1889 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the
1890 /// operating system request due to assertion of external PROCHOT.
1892 UINT32 PROCHOT_Status
:1;
1894 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
1895 /// operating system request due to a thermal event.
1897 UINT32 ThermalStatus
:1;
1900 /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced
1901 /// below the operating system request due to Processor Graphics driver
1904 UINT32 GraphicsDriverStatus
:1;
1906 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
1907 /// When set, frequency is reduced below the operating system request
1908 /// because the processor has detected that utilization is low.
1910 UINT32 AutonomousUtilizationBasedFrequencyControlStatus
:1;
1912 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
1913 /// below the operating system request due to a thermal alert from the
1914 /// Voltage Regulator.
1916 UINT32 VRThermAlertStatus
:1;
1919 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
1920 /// reduced below the operating system request due to electrical design
1921 /// point constraints (e.g. maximum electrical current consumption).
1923 UINT32 ElectricalDesignPointStatus
:1;
1925 /// [Bit 9] Graphics Power Limiting Status (R0) When set, frequency is
1926 /// reduced below the operating system request due to domain-level power
1929 UINT32 GraphicsPowerLimitingStatus
:1;
1931 /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,
1932 /// frequency is reduced below the operating system request due to
1933 /// package-level power limiting PL1.
1937 /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,
1938 /// frequency is reduced below the operating system request due to
1939 /// package-level power limiting PL2.
1944 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
1945 /// has asserted since the log bit was last cleared. This log bit will
1946 /// remain set until cleared by software writing 0.
1948 UINT32 PROCHOT_Log
:1;
1950 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
1951 /// has asserted since the log bit was last cleared. This log bit will
1952 /// remain set until cleared by software writing 0.
1954 UINT32 ThermalLog
:1;
1957 /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics
1958 /// Driver Status bit has asserted since the log bit was last cleared.
1959 /// This log bit will remain set until cleared by software writing 0.
1961 UINT32 GraphicsDriverLog
:1;
1963 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
1964 /// indicates that the Autonomous Utilization-Based Frequency Control
1965 /// Status bit has asserted since the log bit was last cleared. This log
1966 /// bit will remain set until cleared by software writing 0.
1968 UINT32 AutonomousUtilizationBasedFrequencyControlLog
:1;
1970 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
1971 /// Alert Status bit has asserted since the log bit was last cleared. This
1972 /// log bit will remain set until cleared by software writing 0.
1974 UINT32 VRThermAlertLog
:1;
1977 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
1978 /// Status bit has asserted since the log bit was last cleared. This log
1979 /// bit will remain set until cleared by software writing 0.
1981 UINT32 ElectricalDesignPointLog
:1;
1983 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core
1984 /// Power Limiting Status bit has asserted since the log bit was last
1985 /// cleared. This log bit will remain set until cleared by software
1988 UINT32 CorePowerLimitingLog
:1;
1990 /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates
1991 /// that the Package Level PL1 Power Limiting Status bit has asserted
1992 /// since the log bit was last cleared. This log bit will remain set until
1993 /// cleared by software writing 0.
1997 /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that
1998 /// the Package Level PL2 Power Limiting Status bit has asserted since the
1999 /// log bit was last cleared. This log bit will remain set until cleared
2000 /// by software writing 0.
2004 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
2005 /// Limit Status bit has asserted since the log bit was last cleared. This
2006 /// log bit will remain set until cleared by software writing 0.
2008 UINT32 MaxTurboLimitLog
:1;
2010 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
2011 /// Turbo Transition Attenuation Status bit has asserted since the log bit
2012 /// was last cleared. This log bit will remain set until cleared by
2013 /// software writing 0.
2015 UINT32 TurboTransitionAttenuationLog
:1;
2017 UINT32 Reserved7
:32;
2020 /// All bit fields as a 32-bit value
2024 /// All bit fields as a 64-bit value
2027 } MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER
;
2031 Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)
2032 (frequency refers to ring interconnect in the uncore).
2034 @param ECX MSR_HASWELL_RING_PERF_LIMIT_REASONS (0x000006B1)
2035 @param EAX Lower 32-bits of MSR value.
2036 Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.
2037 @param EDX Upper 32-bits of MSR value.
2038 Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.
2040 <b>Example usage</b>
2042 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER Msr;
2044 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS);
2045 AsmWriteMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS, Msr.Uint64);
2047 @note MSR_HASWELL_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.
2049 #define MSR_HASWELL_RING_PERF_LIMIT_REASONS 0x000006B1
2052 MSR information returned for MSR index #MSR_HASWELL_RING_PERF_LIMIT_REASONS
2056 /// Individual bit fields
2060 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the
2061 /// operating system request due to assertion of external PROCHOT.
2063 UINT32 PROCHOT_Status
:1;
2065 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
2066 /// operating system request due to a thermal event.
2068 UINT32 ThermalStatus
:1;
2071 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
2072 /// below the operating system request due to a thermal alert from the
2073 /// Voltage Regulator.
2075 UINT32 VRThermAlertStatus
:1;
2078 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
2079 /// reduced below the operating system request due to electrical design
2080 /// point constraints (e.g. maximum electrical current consumption).
2082 UINT32 ElectricalDesignPointStatus
:1;
2085 /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,
2086 /// frequency is reduced below the operating system request due to
2087 /// package-level power limiting PL1.
2091 /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,
2092 /// frequency is reduced below the operating system request due to
2093 /// package-level power limiting PL2.
2098 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
2099 /// has asserted since the log bit was last cleared. This log bit will
2100 /// remain set until cleared by software writing 0.
2102 UINT32 PROCHOT_Log
:1;
2104 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
2105 /// has asserted since the log bit was last cleared. This log bit will
2106 /// remain set until cleared by software writing 0.
2108 UINT32 ThermalLog
:1;
2111 /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics
2112 /// Driver Status bit has asserted since the log bit was last cleared.
2113 /// This log bit will remain set until cleared by software writing 0.
2115 UINT32 GraphicsDriverLog
:1;
2117 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
2118 /// indicates that the Autonomous Utilization-Based Frequency Control
2119 /// Status bit has asserted since the log bit was last cleared. This log
2120 /// bit will remain set until cleared by software writing 0.
2122 UINT32 AutonomousUtilizationBasedFrequencyControlLog
:1;
2124 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
2125 /// Alert Status bit has asserted since the log bit was last cleared. This
2126 /// log bit will remain set until cleared by software writing 0.
2128 UINT32 VRThermAlertLog
:1;
2131 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
2132 /// Status bit has asserted since the log bit was last cleared. This log
2133 /// bit will remain set until cleared by software writing 0.
2135 UINT32 ElectricalDesignPointLog
:1;
2137 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core
2138 /// Power Limiting Status bit has asserted since the log bit was last
2139 /// cleared. This log bit will remain set until cleared by software
2142 UINT32 CorePowerLimitingLog
:1;
2144 /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates
2145 /// that the Package Level PL1 Power Limiting Status bit has asserted
2146 /// since the log bit was last cleared. This log bit will remain set until
2147 /// cleared by software writing 0.
2151 /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that
2152 /// the Package Level PL2 Power Limiting Status bit has asserted since the
2153 /// log bit was last cleared. This log bit will remain set until cleared
2154 /// by software writing 0.
2158 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
2159 /// Limit Status bit has asserted since the log bit was last cleared. This
2160 /// log bit will remain set until cleared by software writing 0.
2162 UINT32 MaxTurboLimitLog
:1;
2164 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
2165 /// Turbo Transition Attenuation Status bit has asserted since the log bit
2166 /// was last cleared. This log bit will remain set until cleared by
2167 /// software writing 0.
2169 UINT32 TurboTransitionAttenuationLog
:1;
2171 UINT32 Reserved8
:32;
2174 /// All bit fields as a 32-bit value
2178 /// All bit fields as a 64-bit value
2181 } MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER
;
2185 Package. Uncore C-Box 0, counter 0 event select MSR.
2187 @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 (0x00000700)
2188 @param EAX Lower 32-bits of MSR value.
2189 @param EDX Upper 32-bits of MSR value.
2191 <b>Example usage</b>
2195 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0);
2196 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0, Msr);
2198 @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.
2200 #define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 0x00000700
2204 Package. Uncore C-Box 0, counter 1 event select MSR.
2206 @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 (0x00000701)
2207 @param EAX Lower 32-bits of MSR value.
2208 @param EDX Upper 32-bits of MSR value.
2210 <b>Example usage</b>
2214 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1);
2215 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1, Msr);
2217 @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.
2219 #define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 0x00000701
2223 Package. Uncore C-Box 0, performance counter 0.
2225 @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR0 (0x00000706)
2226 @param EAX Lower 32-bits of MSR value.
2227 @param EDX Upper 32-bits of MSR value.
2229 <b>Example usage</b>
2233 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0);
2234 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0, Msr);
2236 @note MSR_HASWELL_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.
2238 #define MSR_HASWELL_UNC_CBO_0_PERFCTR0 0x00000706
2242 Package. Uncore C-Box 0, performance counter 1.
2244 @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR1 (0x00000707)
2245 @param EAX Lower 32-bits of MSR value.
2246 @param EDX Upper 32-bits of MSR value.
2248 <b>Example usage</b>
2252 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1);
2253 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1, Msr);
2255 @note MSR_HASWELL_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.
2257 #define MSR_HASWELL_UNC_CBO_0_PERFCTR1 0x00000707
2261 Package. Uncore C-Box 1, counter 0 event select MSR.
2263 @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 (0x00000710)
2264 @param EAX Lower 32-bits of MSR value.
2265 @param EDX Upper 32-bits of MSR value.
2267 <b>Example usage</b>
2271 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0);
2272 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0, Msr);
2274 @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.
2276 #define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 0x00000710
2280 Package. Uncore C-Box 1, counter 1 event select MSR.
2282 @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 (0x00000711)
2283 @param EAX Lower 32-bits of MSR value.
2284 @param EDX Upper 32-bits of MSR value.
2286 <b>Example usage</b>
2290 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1);
2291 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1, Msr);
2293 @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.
2295 #define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 0x00000711
2299 Package. Uncore C-Box 1, performance counter 0.
2301 @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR0 (0x00000716)
2302 @param EAX Lower 32-bits of MSR value.
2303 @param EDX Upper 32-bits of MSR value.
2305 <b>Example usage</b>
2309 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0);
2310 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0, Msr);
2312 @note MSR_HASWELL_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.
2314 #define MSR_HASWELL_UNC_CBO_1_PERFCTR0 0x00000716
2318 Package. Uncore C-Box 1, performance counter 1.
2320 @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR1 (0x00000717)
2321 @param EAX Lower 32-bits of MSR value.
2322 @param EDX Upper 32-bits of MSR value.
2324 <b>Example usage</b>
2328 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1);
2329 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1, Msr);
2331 @note MSR_HASWELL_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.
2333 #define MSR_HASWELL_UNC_CBO_1_PERFCTR1 0x00000717
2337 Package. Uncore C-Box 2, counter 0 event select MSR.
2339 @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 (0x00000720)
2340 @param EAX Lower 32-bits of MSR value.
2341 @param EDX Upper 32-bits of MSR value.
2343 <b>Example usage</b>
2347 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0);
2348 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0, Msr);
2350 @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.
2352 #define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 0x00000720
2356 Package. Uncore C-Box 2, counter 1 event select MSR.
2358 @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 (0x00000721)
2359 @param EAX Lower 32-bits of MSR value.
2360 @param EDX Upper 32-bits of MSR value.
2362 <b>Example usage</b>
2366 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1);
2367 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1, Msr);
2369 @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.
2371 #define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 0x00000721
2375 Package. Uncore C-Box 2, performance counter 0.
2377 @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR0 (0x00000726)
2378 @param EAX Lower 32-bits of MSR value.
2379 @param EDX Upper 32-bits of MSR value.
2381 <b>Example usage</b>
2385 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0);
2386 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0, Msr);
2388 @note MSR_HASWELL_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.
2390 #define MSR_HASWELL_UNC_CBO_2_PERFCTR0 0x00000726
2394 Package. Uncore C-Box 2, performance counter 1.
2396 @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR1 (0x00000727)
2397 @param EAX Lower 32-bits of MSR value.
2398 @param EDX Upper 32-bits of MSR value.
2400 <b>Example usage</b>
2404 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1);
2405 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1, Msr);
2407 @note MSR_HASWELL_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.
2409 #define MSR_HASWELL_UNC_CBO_2_PERFCTR1 0x00000727
2413 Package. Uncore C-Box 3, counter 0 event select MSR.
2415 @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 (0x00000730)
2416 @param EAX Lower 32-bits of MSR value.
2417 @param EDX Upper 32-bits of MSR value.
2419 <b>Example usage</b>
2423 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0);
2424 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0, Msr);
2426 @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.
2428 #define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 0x00000730
2432 Package. Uncore C-Box 3, counter 1 event select MSR.
2434 @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 (0x00000731)
2435 @param EAX Lower 32-bits of MSR value.
2436 @param EDX Upper 32-bits of MSR value.
2438 <b>Example usage</b>
2442 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1);
2443 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1, Msr);
2445 @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.
2447 #define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 0x00000731
2451 Package. Uncore C-Box 3, performance counter 0.
2453 @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR0 (0x00000736)
2454 @param EAX Lower 32-bits of MSR value.
2455 @param EDX Upper 32-bits of MSR value.
2457 <b>Example usage</b>
2461 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0);
2462 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0, Msr);
2464 @note MSR_HASWELL_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.
2466 #define MSR_HASWELL_UNC_CBO_3_PERFCTR0 0x00000736
2470 Package. Uncore C-Box 3, performance counter 1.
2472 @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR1 (0x00000737)
2473 @param EAX Lower 32-bits of MSR value.
2474 @param EDX Upper 32-bits of MSR value.
2476 <b>Example usage</b>
2480 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1);
2481 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1, Msr);
2483 @note MSR_HASWELL_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.
2485 #define MSR_HASWELL_UNC_CBO_3_PERFCTR1 0x00000737
2489 Package. Note: C-state values are processor specific C-state code names,
2490 unrelated to MWAIT extension C-state parameters or ACPI C-States.
2492 @param ECX MSR_HASWELL_PKG_C8_RESIDENCY (0x00000630)
2493 @param EAX Lower 32-bits of MSR value.
2494 Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.
2495 @param EDX Upper 32-bits of MSR value.
2496 Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.
2498 <b>Example usage</b>
2500 MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER Msr;
2502 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY);
2503 AsmWriteMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY, Msr.Uint64);
2505 @note MSR_HASWELL_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM.
2507 #define MSR_HASWELL_PKG_C8_RESIDENCY 0x00000630
2510 MSR information returned for MSR index #MSR_HASWELL_PKG_C8_RESIDENCY
2514 /// Individual bit fields
2518 /// [Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset
2519 /// that this package is in processor-specific C8 states. Count at the
2520 /// same frequency as the TSC.
2522 UINT32 C8ResidencyCounter
:32;
2524 /// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last
2525 /// reset that this package is in processor-specific C8 states. Count at
2526 /// the same frequency as the TSC.
2528 UINT32 C8ResidencyCounterHi
:28;
2532 /// All bit fields as a 64-bit value
2535 } MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER
;
2539 Package. Note: C-state values are processor specific C-state code names,
2540 unrelated to MWAIT extension C-state parameters or ACPI C-States.
2542 @param ECX MSR_HASWELL_PKG_C9_RESIDENCY (0x00000631)
2543 @param EAX Lower 32-bits of MSR value.
2544 Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.
2545 @param EDX Upper 32-bits of MSR value.
2546 Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.
2548 <b>Example usage</b>
2550 MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER Msr;
2552 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY);
2553 AsmWriteMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY, Msr.Uint64);
2555 @note MSR_HASWELL_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM.
2557 #define MSR_HASWELL_PKG_C9_RESIDENCY 0x00000631
2560 MSR information returned for MSR index #MSR_HASWELL_PKG_C9_RESIDENCY
2564 /// Individual bit fields
2568 /// [Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset
2569 /// that this package is in processor-specific C9 states. Count at the
2570 /// same frequency as the TSC.
2572 UINT32 C9ResidencyCounter
:32;
2574 /// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last
2575 /// reset that this package is in processor-specific C9 states. Count at
2576 /// the same frequency as the TSC.
2578 UINT32 C9ResidencyCounterHi
:28;
2582 /// All bit fields as a 64-bit value
2585 } MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER
;
2589 Package. Note: C-state values are processor specific C-state code names,
2590 unrelated to MWAIT extension C-state parameters or ACPI C-States.
2592 @param ECX MSR_HASWELL_PKG_C10_RESIDENCY (0x00000632)
2593 @param EAX Lower 32-bits of MSR value.
2594 Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.
2595 @param EDX Upper 32-bits of MSR value.
2596 Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.
2598 <b>Example usage</b>
2600 MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER Msr;
2602 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY);
2603 AsmWriteMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY, Msr.Uint64);
2605 @note MSR_HASWELL_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.
2607 #define MSR_HASWELL_PKG_C10_RESIDENCY 0x00000632
2610 MSR information returned for MSR index #MSR_HASWELL_PKG_C10_RESIDENCY
2614 /// Individual bit fields
2618 /// [Bits 31:0] Package C10 Residency Counter. (R/O) Value since last
2619 /// reset that this package is in processor-specific C10 states. Count at
2620 /// the same frequency as the TSC.
2622 UINT32 C10ResidencyCounter
:32;
2624 /// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last
2625 /// reset that this package is in processor-specific C10 states. Count at
2626 /// the same frequency as the TSC.
2628 UINT32 C10ResidencyCounterHi
:28;
2632 /// All bit fields as a 64-bit value
2635 } MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER
;