2 MSR Definitions for Intel processors based on the Haswell microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.11.
24 #ifndef __HASWELL_MSR_H__
25 #define __HASWELL_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
32 @param ECX MSR_HASWELL_PLATFORM_INFO (0x000000CE)
33 @param EAX Lower 32-bits of MSR value.
34 Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.
35 @param EDX Upper 32-bits of MSR value.
36 Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.
40 MSR_HASWELL_PLATFORM_INFO_REGISTER Msr;
42 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PLATFORM_INFO);
43 AsmWriteMsr64 (MSR_HASWELL_PLATFORM_INFO, Msr.Uint64);
45 @note MSR_HASWELL_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
47 #define MSR_HASWELL_PLATFORM_INFO 0x000000CE
50 MSR information returned for MSR index #MSR_HASWELL_PLATFORM_INFO
54 /// Individual bit fields
59 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
60 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
63 UINT32 MaximumNonTurboRatio
:8;
66 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
67 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
68 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
69 /// Turbo mode is disabled.
73 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
74 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
75 /// and when set to 0, indicates TDP Limit for Turbo mode is not
81 /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,
82 /// indicates that LPM is supported, and when set to 0, indicates LPM is
85 UINT32 LowPowerModeSupport
:1;
87 /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base
88 /// TDP level available. 01: One additional TDP level available. 02: Two
89 /// additional TDP level available. 11: Reserved.
91 UINT32 ConfigTDPLevels
:2;
94 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
95 /// minimum ratio (maximum efficiency) that the processor can operates, in
98 UINT32 MaximumEfficiencyRatio
:8;
100 /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the
101 /// minimum supported operating ratio in units of 100 MHz.
103 UINT32 MinimumOperatingRatio
:8;
107 /// All bit fields as a 64-bit value
110 } MSR_HASWELL_PLATFORM_INFO_REGISTER
;
114 THREAD. Performance Event Select for Counter n (R/W) Supports all fields
115 described inTable 35-2 and the fields below.
117 @param ECX MSR_HASWELL_IA32_PERFEVTSELn
118 @param EAX Lower 32-bits of MSR value.
119 Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.
120 @param EDX Upper 32-bits of MSR value.
121 Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.
125 MSR_HASWELL_IA32_PERFEVTSEL_REGISTER Msr;
127 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0);
128 AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0, Msr.Uint64);
130 @note MSR_HASWELL_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.
131 MSR_HASWELL_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.
132 MSR_HASWELL_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.
135 #define MSR_HASWELL_IA32_PERFEVTSEL0 0x00000186
136 #define MSR_HASWELL_IA32_PERFEVTSEL1 0x00000187
137 #define MSR_HASWELL_IA32_PERFEVTSEL3 0x00000189
141 MSR information returned for MSR indexes #MSR_HASWELL_IA32_PERFEVTSEL0,
142 #MSR_HASWELL_IA32_PERFEVTSEL1, and #MSR_HASWELL_IA32_PERFEVTSEL3.
146 /// Individual bit fields
150 /// [Bits 7:0] Event Select: Selects a performance event logic unit.
152 UINT32 EventSelect
:8;
154 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
155 /// detect on the selected event logic.
159 /// [Bit 16] USR: Counts while in privilege level is not ring 0.
163 /// [Bit 17] OS: Counts while in privilege level is ring 0.
167 /// [Bit 18] Edge: Enables edge detection if set.
171 /// [Bit 19] PC: enables pin control.
175 /// [Bit 20] INT: enables interrupt on counter overflow.
179 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
180 /// event conditions occurring across all logical processors sharing a
181 /// processor core. When set to 0, the counter only increments the
182 /// associated event conditions occurring in the logical processor which
183 /// programmed the MSR.
187 /// [Bit 22] EN: enables the corresponding performance counter to commence
188 /// counting when this bit is set.
192 /// [Bit 23] INV: invert the CMASK.
196 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
197 /// performance counter increments each cycle if the event count is
198 /// greater than or equal to the CMASK.
203 /// [Bit 32] IN_TX: see Section 18.11.5.1 When IN_TX (bit 32) is set,
204 /// AnyThread (bit 21) should be cleared to prevent incorrect results.
210 /// All bit fields as a 64-bit value
213 } MSR_HASWELL_IA32_PERFEVTSEL_REGISTER
;
217 THREAD. Performance Event Select for Counter 2 (R/W) Supports all fields
218 described inTable 35-2 and the fields below.
220 @param ECX MSR_HASWELL_IA32_PERFEVTSEL2 (0x00000188)
221 @param EAX Lower 32-bits of MSR value.
222 Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.
223 @param EDX Upper 32-bits of MSR value.
224 Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.
228 MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER Msr;
230 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2);
231 AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2, Msr.Uint64);
233 @note MSR_HASWELL_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.
235 #define MSR_HASWELL_IA32_PERFEVTSEL2 0x00000188
238 MSR information returned for MSR index #MSR_HASWELL_IA32_PERFEVTSEL2
242 /// Individual bit fields
246 /// [Bits 7:0] Event Select: Selects a performance event logic unit.
248 UINT32 EventSelect
:8;
250 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
251 /// detect on the selected event logic.
255 /// [Bit 16] USR: Counts while in privilege level is not ring 0.
259 /// [Bit 17] OS: Counts while in privilege level is ring 0.
263 /// [Bit 18] Edge: Enables edge detection if set.
267 /// [Bit 19] PC: enables pin control.
271 /// [Bit 20] INT: enables interrupt on counter overflow.
275 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
276 /// event conditions occurring across all logical processors sharing a
277 /// processor core. When set to 0, the counter only increments the
278 /// associated event conditions occurring in the logical processor which
279 /// programmed the MSR.
283 /// [Bit 22] EN: enables the corresponding performance counter to commence
284 /// counting when this bit is set.
288 /// [Bit 23] INV: invert the CMASK.
292 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
293 /// performance counter increments each cycle if the event count is
294 /// greater than or equal to the CMASK.
299 /// [Bit 32] IN_TX: see Section 18.11.5.1 When IN_TX (bit 32) is set,
300 /// AnyThread (bit 21) should be cleared to prevent incorrect results.
304 /// [Bit 33] IN_TXCP: see Section 18.11.5.1 When IN_TXCP=1 & IN_TX=1 and
305 /// in sampling, spurious PMI may occur and transactions may continuously
306 /// abort near overflow conditions. Software should favor using IN_TXCP
307 /// for counting over sampling. If sampling, software should use large
308 /// "sample-after" value after clearing the counter configured to use
309 /// IN_TXCP and also always reset the counter even when no overflow
310 /// condition was reported.
316 /// All bit fields as a 64-bit value
319 } MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER
;
323 Thread. Last Branch Record Filtering Select Register (R/W).
325 @param ECX MSR_HASWELL_LBR_SELECT (0x000001C8)
326 @param EAX Lower 32-bits of MSR value.
327 Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.
328 @param EDX Upper 32-bits of MSR value.
329 Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.
333 MSR_HASWELL_LBR_SELECT_REGISTER Msr;
335 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_LBR_SELECT);
336 AsmWriteMsr64 (MSR_HASWELL_LBR_SELECT, Msr.Uint64);
338 @note MSR_HASWELL_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
340 #define MSR_HASWELL_LBR_SELECT 0x000001C8
343 MSR information returned for MSR index #MSR_HASWELL_LBR_SELECT
347 /// Individual bit fields
351 /// [Bit 0] CPL_EQ_0.
355 /// [Bit 1] CPL_NEQ_0.
363 /// [Bit 3] NEAR_REL_CALL.
365 UINT32 NEAR_REL_CALL
:1;
367 /// [Bit 4] NEAR_IND_CALL.
369 UINT32 NEAR_IND_CALL
:1;
371 /// [Bit 5] NEAR_RET.
375 /// [Bit 6] NEAR_IND_JMP.
377 UINT32 NEAR_IND_JMP
:1;
379 /// [Bit 7] NEAR_REL_JMP.
381 UINT32 NEAR_REL_JMP
:1;
383 /// [Bit 8] FAR_BRANCH.
387 /// [Bit 9] EN_CALL_STACK.
389 UINT32 EN_CALL_STACK
:1;
394 /// All bit fields as a 32-bit value
398 /// All bit fields as a 64-bit value
401 } MSR_HASWELL_LBR_SELECT_REGISTER
;
405 Package. Package C6/C7 Interrupt Response Limit 1 (R/W) This MSR defines
406 the interrupt response time limit used by the processor to manage transition
407 to package C6 or C7 state. The latency programmed in this register is for
408 the shorter-latency sub C-states used by an MWAIT hint to C6 or C7 state.
409 Note: C-state values are processor specific C-state code names, unrelated to
410 MWAIT extension C-state parameters or ACPI C-States.
412 @param ECX MSR_HASWELL_PKGC_IRTL1 (0x0000060B)
413 @param EAX Lower 32-bits of MSR value.
414 Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.
415 @param EDX Upper 32-bits of MSR value.
416 Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.
420 MSR_HASWELL_PKGC_IRTL1_REGISTER Msr;
422 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL1);
423 AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL1, Msr.Uint64);
425 @note MSR_HASWELL_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.
427 #define MSR_HASWELL_PKGC_IRTL1 0x0000060B
430 MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL1
434 /// Individual bit fields
438 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
439 /// that should be used to decide if the package should be put into a
440 /// package C6 or C7 state.
442 UINT32 InterruptResponseTimeLimit
:10;
444 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
445 /// unit of the interrupt response time limit. See Table 35-18 for
446 /// supported time unit encodings.
451 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
452 /// valid and can be used by the processor for package C-sate management.
459 /// All bit fields as a 32-bit value
463 /// All bit fields as a 64-bit value
466 } MSR_HASWELL_PKGC_IRTL1_REGISTER
;
470 Package. Package C6/C7 Interrupt Response Limit 2 (R/W) This MSR defines
471 the interrupt response time limit used by the processor to manage transition
472 to package C6 or C7 state. The latency programmed in this register is for
473 the longer-latency sub Cstates used by an MWAIT hint to C6 or C7 state.
474 Note: C-state values are processor specific C-state code names, unrelated to
475 MWAIT extension C-state parameters or ACPI C-States.
477 @param ECX MSR_HASWELL_PKGC_IRTL2 (0x0000060C)
478 @param EAX Lower 32-bits of MSR value.
479 Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.
480 @param EDX Upper 32-bits of MSR value.
481 Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.
485 MSR_HASWELL_PKGC_IRTL2_REGISTER Msr;
487 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL2);
488 AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL2, Msr.Uint64);
490 @note MSR_HASWELL_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.
492 #define MSR_HASWELL_PKGC_IRTL2 0x0000060C
495 MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL2
499 /// Individual bit fields
503 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
504 /// that should be used to decide if the package should be put into a
505 /// package C6 or C7 state.
507 UINT32 InterruptResponseTimeLimit
:10;
509 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
510 /// unit of the interrupt response time limit. See Table 35-18 for
511 /// supported time unit encodings.
516 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
517 /// valid and can be used by the processor for package C-sate management.
524 /// All bit fields as a 32-bit value
528 /// All bit fields as a 64-bit value
531 } MSR_HASWELL_PKGC_IRTL2_REGISTER
;
535 Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
537 @param ECX MSR_HASWELL_PKG_PERF_STATUS (0x00000613)
538 @param EAX Lower 32-bits of MSR value.
539 @param EDX Upper 32-bits of MSR value.
545 Msr = AsmReadMsr64 (MSR_HASWELL_PKG_PERF_STATUS);
547 @note MSR_HASWELL_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
549 #define MSR_HASWELL_PKG_PERF_STATUS 0x00000613
553 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
555 @param ECX MSR_HASWELL_DRAM_ENERGY_STATUS (0x00000619)
556 @param EAX Lower 32-bits of MSR value.
557 @param EDX Upper 32-bits of MSR value.
563 Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_ENERGY_STATUS);
565 @note MSR_HASWELL_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
567 #define MSR_HASWELL_DRAM_ENERGY_STATUS 0x00000619
571 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
574 @param ECX MSR_HASWELL_DRAM_PERF_STATUS (0x0000061B)
575 @param EAX Lower 32-bits of MSR value.
576 @param EDX Upper 32-bits of MSR value.
582 Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_PERF_STATUS);
584 @note MSR_HASWELL_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
586 #define MSR_HASWELL_DRAM_PERF_STATUS 0x0000061B
590 Package. Base TDP Ratio (R/O).
592 @param ECX MSR_HASWELL_CONFIG_TDP_NOMINAL (0x00000648)
593 @param EAX Lower 32-bits of MSR value.
594 Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.
595 @param EDX Upper 32-bits of MSR value.
596 Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.
600 MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER Msr;
602 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_NOMINAL);
604 @note MSR_HASWELL_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
606 #define MSR_HASWELL_CONFIG_TDP_NOMINAL 0x00000648
609 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_NOMINAL
613 /// Individual bit fields
617 /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this
618 /// specific processor (in units of 100 MHz).
620 UINT32 Config_TDP_Base
:8;
625 /// All bit fields as a 32-bit value
629 /// All bit fields as a 64-bit value
632 } MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER
;
636 Package. ConfigTDP Level 1 ratio and power level (R/O).
638 @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL1 (0x00000649)
639 @param EAX Lower 32-bits of MSR value.
640 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.
641 @param EDX Upper 32-bits of MSR value.
642 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.
646 MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER Msr;
648 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL1);
650 @note MSR_HASWELL_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
652 #define MSR_HASWELL_CONFIG_TDP_LEVEL1 0x00000649
655 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL1
659 /// Individual bit fields
663 /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.
665 UINT32 PKG_TDP_LVL1
:15;
668 /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used
669 /// for this specific processor.
671 UINT32 Config_TDP_LVL1_Ratio
:8;
674 /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP
677 UINT32 PKG_MAX_PWR_LVL1
:15;
679 /// [Bits 62:47] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP
682 UINT32 PKG_MIN_PWR_LVL1
:16;
686 /// All bit fields as a 64-bit value
689 } MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER
;
693 Package. ConfigTDP Level 2 ratio and power level (R/O).
695 @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL2 (0x0000064A)
696 @param EAX Lower 32-bits of MSR value.
697 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.
698 @param EDX Upper 32-bits of MSR value.
699 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.
703 MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER Msr;
705 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL2);
707 @note MSR_HASWELL_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
709 #define MSR_HASWELL_CONFIG_TDP_LEVEL2 0x0000064A
712 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL2
716 /// Individual bit fields
720 /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.
722 UINT32 PKG_TDP_LVL2
:15;
725 /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used
726 /// for this specific processor.
728 UINT32 Config_TDP_LVL2_Ratio
:8;
731 /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP
734 UINT32 PKG_MAX_PWR_LVL2
:15;
736 /// [Bits 62:47] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP
739 UINT32 PKG_MIN_PWR_LVL2
:16;
743 /// All bit fields as a 64-bit value
746 } MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER
;
750 Package. ConfigTDP Control (R/W).
752 @param ECX MSR_HASWELL_CONFIG_TDP_CONTROL (0x0000064B)
753 @param EAX Lower 32-bits of MSR value.
754 Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.
755 @param EDX Upper 32-bits of MSR value.
756 Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.
760 MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER Msr;
762 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL);
763 AsmWriteMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL, Msr.Uint64);
765 @note MSR_HASWELL_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
767 #define MSR_HASWELL_CONFIG_TDP_CONTROL 0x0000064B
770 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_CONTROL
774 /// Individual bit fields
778 /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.
783 /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of
784 /// this register is locked until a reset.
786 UINT32 Config_TDP_Lock
:1;
790 /// All bit fields as a 32-bit value
794 /// All bit fields as a 64-bit value
797 } MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER
;
801 Package. ConfigTDP Control (R/W).
803 @param ECX MSR_HASWELL_TURBO_ACTIVATION_RATIO (0x0000064C)
804 @param EAX Lower 32-bits of MSR value.
805 Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.
806 @param EDX Upper 32-bits of MSR value.
807 Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.
811 MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER Msr;
813 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO);
814 AsmWriteMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO, Msr.Uint64);
816 @note MSR_HASWELL_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
818 #define MSR_HASWELL_TURBO_ACTIVATION_RATIO 0x0000064C
821 MSR information returned for MSR index #MSR_HASWELL_TURBO_ACTIVATION_RATIO
825 /// Individual bit fields
829 /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this
832 UINT32 MAX_NON_TURBO_RATIO
:8;
835 /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the
836 /// content of this register is locked until a reset.
838 UINT32 TURBO_ACTIVATION_RATIO_Lock
:1;
842 /// All bit fields as a 32-bit value
846 /// All bit fields as a 64-bit value
849 } MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER
;
853 Core. C-State Configuration Control (R/W) Note: C-state values are processor
854 specific C-state code names, unrelated to MWAIT extension C-state parameters
855 or ACPI Cstates. `See http://biosbits.org. <http://biosbits.org>`__.
857 @param ECX MSR_HASWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)
858 @param EAX Lower 32-bits of MSR value.
859 Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
860 @param EDX Upper 32-bits of MSR value.
861 Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
865 MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
867 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL);
868 AsmWriteMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
870 @note MSR_HASWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
872 #define MSR_HASWELL_PKG_CST_CONFIG_CONTROL 0x000000E2
875 MSR information returned for MSR index #MSR_HASWELL_PKG_CST_CONFIG_CONTROL
879 /// Individual bit fields
883 /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest
884 /// processor-specific C-state code name (consuming the least power) for
885 /// the package. The default is set as factory-configured package C-state
886 /// limit. The following C-state code name encodings are supported: 0000b:
887 /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6
888 /// 0100b: C7 0101b: C7s Package C states C7 are not available to
889 /// processor with signature 06_3CH.
894 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
899 /// [Bit 15] CFG Lock (R/WO).
904 /// [Bit 25] C3 State Auto Demotion Enable (R/W).
906 UINT32 C3AutoDemotion
:1;
908 /// [Bit 26] C1 State Auto Demotion Enable (R/W).
910 UINT32 C1AutoDemotion
:1;
912 /// [Bit 27] Enable C3 Undemotion (R/W).
914 UINT32 C3Undemotion
:1;
916 /// [Bit 28] Enable C1 Undemotion (R/W).
918 UINT32 C1Undemotion
:1;
923 /// All bit fields as a 32-bit value
927 /// All bit fields as a 64-bit value
930 } MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER
;
934 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
935 Enhancement. Accessible only while in SMM.
937 @param ECX MSR_HASWELL_SMM_MCA_CAP (0x0000017D)
938 @param EAX Lower 32-bits of MSR value.
939 Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.
940 @param EDX Upper 32-bits of MSR value.
941 Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.
945 MSR_HASWELL_SMM_MCA_CAP_REGISTER Msr;
947 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_MCA_CAP);
948 AsmWriteMsr64 (MSR_HASWELL_SMM_MCA_CAP, Msr.Uint64);
950 @note MSR_HASWELL_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
952 #define MSR_HASWELL_SMM_MCA_CAP 0x0000017D
955 MSR information returned for MSR index #MSR_HASWELL_SMM_MCA_CAP
959 /// Individual bit fields
965 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
966 /// SMM code access restriction is supported and the
967 /// MSR_SMM_FEATURE_CONTROL is supported.
969 UINT32 SMM_Code_Access_Chk
:1;
971 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
972 /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is
975 UINT32 Long_Flow_Indication
:1;
979 /// All bit fields as a 64-bit value
982 } MSR_HASWELL_SMM_MCA_CAP_REGISTER
;
986 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
987 RW if MSR_PLATFORM_INFO.[28] = 1.
989 @param ECX MSR_HASWELL_TURBO_RATIO_LIMIT (0x000001AD)
990 @param EAX Lower 32-bits of MSR value.
991 Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.
992 @param EDX Upper 32-bits of MSR value.
993 Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.
997 MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER Msr;
999 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_RATIO_LIMIT);
1001 @note MSR_HASWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
1003 #define MSR_HASWELL_TURBO_RATIO_LIMIT 0x000001AD
1006 MSR information returned for MSR index #MSR_HASWELL_TURBO_RATIO_LIMIT
1010 /// Individual bit fields
1014 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
1015 /// limit of 1 core active.
1019 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
1020 /// limit of 2 core active.
1024 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
1025 /// limit of 3 core active.
1029 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
1030 /// limit of 4 core active.
1036 /// All bit fields as a 32-bit value
1040 /// All bit fields as a 64-bit value
1043 } MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER
;
1047 Package. Uncore PMU global control.
1049 @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_CTRL (0x00000391)
1050 @param EAX Lower 32-bits of MSR value.
1051 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.
1052 @param EDX Upper 32-bits of MSR value.
1053 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.
1055 <b>Example usage</b>
1057 MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;
1059 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL);
1060 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);
1062 @note MSR_HASWELL_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.
1064 #define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL 0x00000391
1067 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_CTRL
1071 /// Individual bit fields
1075 /// [Bit 0] Core 0 select.
1077 UINT32 PMI_Sel_Core0
:1;
1079 /// [Bit 1] Core 1 select.
1081 UINT32 PMI_Sel_Core1
:1;
1083 /// [Bit 2] Core 2 select.
1085 UINT32 PMI_Sel_Core2
:1;
1087 /// [Bit 3] Core 3 select.
1089 UINT32 PMI_Sel_Core3
:1;
1090 UINT32 Reserved1
:15;
1091 UINT32 Reserved2
:10;
1093 /// [Bit 29] Enable all uncore counters.
1097 /// [Bit 30] Enable wake on PMI.
1101 /// [Bit 31] Enable Freezing counter when overflow.
1104 UINT32 Reserved3
:32;
1107 /// All bit fields as a 32-bit value
1111 /// All bit fields as a 64-bit value
1114 } MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER
;
1118 Package. Uncore PMU main status.
1120 @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_STATUS (0x00000392)
1121 @param EAX Lower 32-bits of MSR value.
1122 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.
1123 @param EDX Upper 32-bits of MSR value.
1124 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.
1126 <b>Example usage</b>
1128 MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;
1130 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS);
1131 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);
1133 @note MSR_HASWELL_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.
1135 #define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS 0x00000392
1138 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_STATUS
1142 /// Individual bit fields
1146 /// [Bit 0] Fixed counter overflowed.
1150 /// [Bit 1] An ARB counter overflowed.
1155 /// [Bit 3] A CBox counter overflowed (on any slice).
1158 UINT32 Reserved2
:28;
1159 UINT32 Reserved3
:32;
1162 /// All bit fields as a 32-bit value
1166 /// All bit fields as a 64-bit value
1169 } MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER
;
1173 Package. Uncore fixed counter control (R/W).
1175 @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTRL (0x00000394)
1176 @param EAX Lower 32-bits of MSR value.
1177 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.
1178 @param EDX Upper 32-bits of MSR value.
1179 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.
1181 <b>Example usage</b>
1183 MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER Msr;
1185 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL);
1186 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL, Msr.Uint64);
1188 @note MSR_HASWELL_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.
1190 #define MSR_HASWELL_UNC_PERF_FIXED_CTRL 0x00000394
1193 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTRL
1197 /// Individual bit fields
1200 UINT32 Reserved1
:20;
1202 /// [Bit 20] Enable overflow propagation.
1204 UINT32 EnableOverflow
:1;
1207 /// [Bit 22] Enable counting.
1209 UINT32 EnableCounting
:1;
1211 UINT32 Reserved4
:32;
1214 /// All bit fields as a 32-bit value
1218 /// All bit fields as a 64-bit value
1221 } MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER
;
1225 Package. Uncore fixed counter.
1227 @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTR (0x00000395)
1228 @param EAX Lower 32-bits of MSR value.
1229 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.
1230 @param EDX Upper 32-bits of MSR value.
1231 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.
1233 <b>Example usage</b>
1235 MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER Msr;
1237 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR);
1238 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR, Msr.Uint64);
1240 @note MSR_HASWELL_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.
1242 #define MSR_HASWELL_UNC_PERF_FIXED_CTR 0x00000395
1245 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTR
1249 /// Individual bit fields
1253 /// [Bits 31:0] Current count.
1255 UINT32 CurrentCount
:32;
1257 /// [Bits 47:32] Current count.
1259 UINT32 CurrentCountHi
:16;
1263 /// All bit fields as a 64-bit value
1266 } MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER
;
1270 Package. Uncore C-Box configuration information (R/O).
1272 @param ECX MSR_HASWELL_UNC_CBO_CONFIG (0x00000396)
1273 @param EAX Lower 32-bits of MSR value.
1274 Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.
1275 @param EDX Upper 32-bits of MSR value.
1276 Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.
1278 <b>Example usage</b>
1280 MSR_HASWELL_UNC_CBO_CONFIG_REGISTER Msr;
1282 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_CONFIG);
1284 @note MSR_HASWELL_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.
1286 #define MSR_HASWELL_UNC_CBO_CONFIG 0x00000396
1289 MSR information returned for MSR index #MSR_HASWELL_UNC_CBO_CONFIG
1293 /// Individual bit fields
1297 /// [Bits 3:0] Encoded number of C-Box, derive value by "-1".
1300 UINT32 Reserved1
:28;
1301 UINT32 Reserved2
:32;
1304 /// All bit fields as a 32-bit value
1308 /// All bit fields as a 64-bit value
1311 } MSR_HASWELL_UNC_CBO_CONFIG_REGISTER
;
1315 Package. Uncore Arb unit, performance counter 0.
1317 @param ECX MSR_HASWELL_UNC_ARB_PERFCTR0 (0x000003B0)
1318 @param EAX Lower 32-bits of MSR value.
1319 @param EDX Upper 32-bits of MSR value.
1321 <b>Example usage</b>
1325 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0);
1326 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0, Msr);
1328 @note MSR_HASWELL_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.
1330 #define MSR_HASWELL_UNC_ARB_PERFCTR0 0x000003B0
1334 Package. Uncore Arb unit, performance counter 1.
1336 @param ECX MSR_HASWELL_UNC_ARB_PERFCTR1 (0x000003B1)
1337 @param EAX Lower 32-bits of MSR value.
1338 @param EDX Upper 32-bits of MSR value.
1340 <b>Example usage</b>
1344 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1);
1345 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1, Msr);
1347 @note MSR_HASWELL_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.
1349 #define MSR_HASWELL_UNC_ARB_PERFCTR1 0x000003B1
1353 Package. Uncore Arb unit, counter 0 event select MSR.
1355 @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL0 (0x000003B2)
1356 @param EAX Lower 32-bits of MSR value.
1357 @param EDX Upper 32-bits of MSR value.
1359 <b>Example usage</b>
1363 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0);
1364 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0, Msr);
1366 @note MSR_HASWELL_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.
1368 #define MSR_HASWELL_UNC_ARB_PERFEVTSEL0 0x000003B2
1372 Package. Uncore Arb unit, counter 1 event select MSR.
1374 @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL1 (0x000003B3)
1375 @param EAX Lower 32-bits of MSR value.
1376 @param EDX Upper 32-bits of MSR value.
1378 <b>Example usage</b>
1382 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1);
1383 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1, Msr);
1385 @note MSR_HASWELL_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.
1387 #define MSR_HASWELL_UNC_ARB_PERFEVTSEL1 0x000003B3
1391 Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability
1392 Enhancement. Accessible only while in SMM.
1394 @param ECX MSR_HASWELL_SMM_FEATURE_CONTROL (0x000004E0)
1395 @param EAX Lower 32-bits of MSR value.
1396 Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.
1397 @param EDX Upper 32-bits of MSR value.
1398 Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.
1400 <b>Example usage</b>
1402 MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER Msr;
1404 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL);
1405 AsmWriteMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL, Msr.Uint64);
1407 @note MSR_HASWELL_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.
1409 #define MSR_HASWELL_SMM_FEATURE_CONTROL 0x000004E0
1412 MSR information returned for MSR index #MSR_HASWELL_SMM_FEATURE_CONTROL
1416 /// Individual bit fields
1420 /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from
1421 /// further changes.
1426 /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if
1427 /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the
1428 /// logical processors are prevented from executing SMM code outside the
1429 /// ranges defined by the SMRR. When set to '1' any logical processor in
1430 /// the package that attempts to execute SMM code not within the ranges
1431 /// defined by the SMRR will assert an unrecoverable MCE.
1433 UINT32 SMM_Code_Chk_En
:1;
1434 UINT32 Reserved2
:29;
1435 UINT32 Reserved3
:32;
1438 /// All bit fields as a 32-bit value
1442 /// All bit fields as a 64-bit value
1445 } MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER
;
1449 Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical
1450 processors in the package. Available only while in SMM and
1451 MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.
1453 [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
1454 processor of its state in a long flow of internal operation which
1455 delays servicing an interrupt. The corresponding bit will be set at
1456 the start of long events such as: Microcode Update Load, C6, WBINVD,
1457 Ratio Change, Throttle. The bit is automatically cleared at the end of
1458 each long event. The reset value of this field is 0. Only bit
1459 positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be
1462 [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
1463 processor of its state in a long flow of internal operation which
1464 delays servicing an interrupt. The corresponding bit will be set at
1465 the start of long events such as: Microcode Update Load, C6, WBINVD,
1466 Ratio Change, Throttle. The bit is automatically cleared at the end of
1467 each long event. The reset value of this field is 0. Only bit
1468 positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be
1471 @param ECX MSR_HASWELL_SMM_DELAYED (0x000004E2)
1472 @param EAX Lower 32-bits of MSR value.
1473 @param EDX Upper 32-bits of MSR value.
1475 <b>Example usage</b>
1479 Msr = AsmReadMsr64 (MSR_HASWELL_SMM_DELAYED);
1481 @note MSR_HASWELL_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.
1483 #define MSR_HASWELL_SMM_DELAYED 0x000004E2
1487 Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical
1488 processors in the package. Available only while in SMM.
1490 [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
1491 processor of its blocked state to service an SMI. The corresponding
1492 bit will be set if the logical processor is in one of the following
1493 states: Wait For SIPI or SENTER Sleep. The reset value of this field
1494 is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,
1495 ECX=PKG_LVL):EBX[15:0] can be updated.
1498 [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
1499 processor of its blocked state to service an SMI. The corresponding
1500 bit will be set if the logical processor is in one of the following
1501 states: Wait For SIPI or SENTER Sleep. The reset value of this field
1502 is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,
1503 ECX=PKG_LVL):EBX[15:0] can be updated.
1505 @param ECX MSR_HASWELL_SMM_BLOCKED (0x000004E3)
1506 @param EAX Lower 32-bits of MSR value.
1507 @param EDX Upper 32-bits of MSR value.
1509 <b>Example usage</b>
1513 Msr = AsmReadMsr64 (MSR_HASWELL_SMM_BLOCKED);
1515 @note MSR_HASWELL_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.
1517 #define MSR_HASWELL_SMM_BLOCKED 0x000004E3
1521 Package. Unit Multipliers used in RAPL Interfaces (R/O).
1523 @param ECX MSR_HASWELL_RAPL_POWER_UNIT (0x00000606)
1524 @param EAX Lower 32-bits of MSR value.
1525 Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.
1526 @param EDX Upper 32-bits of MSR value.
1527 Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.
1529 <b>Example usage</b>
1531 MSR_HASWELL_RAPL_POWER_UNIT_REGISTER Msr;
1533 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RAPL_POWER_UNIT);
1535 @note MSR_HASWELL_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
1537 #define MSR_HASWELL_RAPL_POWER_UNIT 0x00000606
1540 MSR information returned for MSR index #MSR_HASWELL_RAPL_POWER_UNIT
1544 /// Individual bit fields
1548 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
1550 UINT32 PowerUnits
:4;
1553 /// [Bits 12:8] Package. Energy Status Units Energy related information
1554 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
1555 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
1558 UINT32 EnergyStatusUnits
:5;
1561 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
1565 UINT32 Reserved3
:12;
1566 UINT32 Reserved4
:32;
1569 /// All bit fields as a 32-bit value
1573 /// All bit fields as a 64-bit value
1576 } MSR_HASWELL_RAPL_POWER_UNIT_REGISTER
;
1580 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1583 @param ECX MSR_HASWELL_PP0_ENERGY_STATUS (0x00000639)
1584 @param EAX Lower 32-bits of MSR value.
1585 @param EDX Upper 32-bits of MSR value.
1587 <b>Example usage</b>
1591 Msr = AsmReadMsr64 (MSR_HASWELL_PP0_ENERGY_STATUS);
1593 @note MSR_HASWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
1595 #define MSR_HASWELL_PP0_ENERGY_STATUS 0x00000639
1599 Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
1602 @param ECX MSR_HASWELL_PP1_POWER_LIMIT (0x00000640)
1603 @param EAX Lower 32-bits of MSR value.
1604 @param EDX Upper 32-bits of MSR value.
1606 <b>Example usage</b>
1610 Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POWER_LIMIT);
1611 AsmWriteMsr64 (MSR_HASWELL_PP1_POWER_LIMIT, Msr);
1613 @note MSR_HASWELL_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.
1615 #define MSR_HASWELL_PP1_POWER_LIMIT 0x00000640
1619 Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1622 @param ECX MSR_HASWELL_PP1_ENERGY_STATUS (0x00000641)
1623 @param EAX Lower 32-bits of MSR value.
1624 @param EDX Upper 32-bits of MSR value.
1626 <b>Example usage</b>
1630 Msr = AsmReadMsr64 (MSR_HASWELL_PP1_ENERGY_STATUS);
1632 @note MSR_HASWELL_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.
1634 #define MSR_HASWELL_PP1_ENERGY_STATUS 0x00000641
1638 Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
1641 @param ECX MSR_HASWELL_PP1_POLICY (0x00000642)
1642 @param EAX Lower 32-bits of MSR value.
1643 @param EDX Upper 32-bits of MSR value.
1645 <b>Example usage</b>
1649 Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POLICY);
1650 AsmWriteMsr64 (MSR_HASWELL_PP1_POLICY, Msr);
1652 @note MSR_HASWELL_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.
1654 #define MSR_HASWELL_PP1_POLICY 0x00000642
1658 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
1659 refers to processor core frequency).
1661 @param ECX MSR_HASWELL_CORE_PERF_LIMIT_REASONS (0x00000690)
1662 @param EAX Lower 32-bits of MSR value.
1663 Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.
1664 @param EDX Upper 32-bits of MSR value.
1665 Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.
1667 <b>Example usage</b>
1669 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
1671 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS);
1672 AsmWriteMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
1674 @note MSR_HASWELL_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
1676 #define MSR_HASWELL_CORE_PERF_LIMIT_REASONS 0x00000690
1679 MSR information returned for MSR index #MSR_HASWELL_CORE_PERF_LIMIT_REASONS
1683 /// Individual bit fields
1687 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
1688 /// reduced below the operating system request due to assertion of
1689 /// external PROCHOT.
1691 UINT32 PROCHOT_Status
:1;
1693 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
1694 /// operating system request due to a thermal event.
1696 UINT32 ThermalStatus
:1;
1699 /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced
1700 /// below the operating system request due to Processor Graphics driver
1703 UINT32 GraphicsDriverStatus
:1;
1705 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
1706 /// When set, frequency is reduced below the operating system request
1707 /// because the processor has detected that utilization is low.
1709 UINT32 AutonomousUtilizationBasedFrequencyControlStatus
:1;
1711 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
1712 /// below the operating system request due to a thermal alert from the
1713 /// Voltage Regulator.
1715 UINT32 VRThermAlertStatus
:1;
1718 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
1719 /// reduced below the operating system request due to electrical design
1720 /// point constraints (e.g. maximum electrical current consumption).
1722 UINT32 ElectricalDesignPointStatus
:1;
1724 /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced
1725 /// below the operating system request due to domain-level power limiting.
1729 /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,
1730 /// frequency is reduced below the operating system request due to
1731 /// package-level power limiting PL1.
1735 /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,
1736 /// frequency is reduced below the operating system request due to
1737 /// package-level power limiting PL2.
1741 /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced
1742 /// below the operating system request due to multi-core turbo limits.
1744 UINT32 MaxTurboLimitStatus
:1;
1746 /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency
1747 /// is reduced below the operating system request due to Turbo transition
1748 /// attenuation. This prevents performance degradation due to frequent
1749 /// operating ratio changes.
1751 UINT32 TurboTransitionAttenuationStatus
:1;
1754 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
1755 /// has asserted since the log bit was last cleared. This log bit will
1756 /// remain set until cleared by software writing 0.
1758 UINT32 PROCHOT_Log
:1;
1760 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
1761 /// has asserted since the log bit was last cleared. This log bit will
1762 /// remain set until cleared by software writing 0.
1764 UINT32 ThermalLog
:1;
1767 /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics
1768 /// Driver Status bit has asserted since the log bit was last cleared.
1769 /// This log bit will remain set until cleared by software writing 0.
1771 UINT32 GraphicsDriverLog
:1;
1773 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
1774 /// indicates that the Autonomous Utilization-Based Frequency Control
1775 /// Status bit has asserted since the log bit was last cleared. This log
1776 /// bit will remain set until cleared by software writing 0.
1778 UINT32 AutonomousUtilizationBasedFrequencyControlLog
:1;
1780 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
1781 /// Alert Status bit has asserted since the log bit was last cleared. This
1782 /// log bit will remain set until cleared by software writing 0.
1784 UINT32 VRThermAlertLog
:1;
1787 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
1788 /// Status bit has asserted since the log bit was last cleared. This log
1789 /// bit will remain set until cleared by software writing 0.
1791 UINT32 ElectricalDesignPointLog
:1;
1793 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core
1794 /// Power Limiting Status bit has asserted since the log bit was last
1795 /// cleared. This log bit will remain set until cleared by software
1800 /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates
1801 /// that the Package Level PL1 Power Limiting Status bit has asserted
1802 /// since the log bit was last cleared. This log bit will remain set until
1803 /// cleared by software writing 0.
1807 /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that
1808 /// the Package Level PL2 Power Limiting Status bit has asserted since the
1809 /// log bit was last cleared. This log bit will remain set until cleared
1810 /// by software writing 0.
1814 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
1815 /// Limit Status bit has asserted since the log bit was last cleared. This
1816 /// log bit will remain set until cleared by software writing 0.
1818 UINT32 MaxTurboLimitLog
:1;
1820 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
1821 /// Turbo Transition Attenuation Status bit has asserted since the log bit
1822 /// was last cleared. This log bit will remain set until cleared by
1823 /// software writing 0.
1825 UINT32 TurboTransitionAttenuationLog
:1;
1827 UINT32 Reserved7
:32;
1830 /// All bit fields as a 32-bit value
1834 /// All bit fields as a 64-bit value
1837 } MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER
;
1841 Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)
1842 (frequency refers to processor graphics frequency).
1844 @param ECX MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)
1845 @param EAX Lower 32-bits of MSR value.
1846 Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
1847 @param EDX Upper 32-bits of MSR value.
1848 Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
1850 <b>Example usage</b>
1852 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr;
1854 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS);
1855 AsmWriteMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);
1857 @note MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.
1859 #define MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0
1862 MSR information returned for MSR index
1863 #MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS
1867 /// Individual bit fields
1871 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the
1872 /// operating system request due to assertion of external PROCHOT.
1874 UINT32 PROCHOT_Status
:1;
1876 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
1877 /// operating system request due to a thermal event.
1879 UINT32 ThermalStatus
:1;
1882 /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced
1883 /// below the operating system request due to Processor Graphics driver
1886 UINT32 GraphicsDriverStatus
:1;
1888 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
1889 /// When set, frequency is reduced below the operating system request
1890 /// because the processor has detected that utilization is low.
1892 UINT32 AutonomousUtilizationBasedFrequencyControlStatus
:1;
1894 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
1895 /// below the operating system request due to a thermal alert from the
1896 /// Voltage Regulator.
1898 UINT32 VRThermAlertStatus
:1;
1901 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
1902 /// reduced below the operating system request due to electrical design
1903 /// point constraints (e.g. maximum electrical current consumption).
1905 UINT32 ElectricalDesignPointStatus
:1;
1907 /// [Bit 9] Graphics Power Limiting Status (R0) When set, frequency is
1908 /// reduced below the operating system request due to domain-level power
1911 UINT32 GraphicsPowerLimitingStatus
:1;
1913 /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,
1914 /// frequency is reduced below the operating system request due to
1915 /// package-level power limiting PL1.
1919 /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,
1920 /// frequency is reduced below the operating system request due to
1921 /// package-level power limiting PL2.
1926 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
1927 /// has asserted since the log bit was last cleared. This log bit will
1928 /// remain set until cleared by software writing 0.
1930 UINT32 PROCHOT_Log
:1;
1932 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
1933 /// has asserted since the log bit was last cleared. This log bit will
1934 /// remain set until cleared by software writing 0.
1936 UINT32 ThermalLog
:1;
1939 /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics
1940 /// Driver Status bit has asserted since the log bit was last cleared.
1941 /// This log bit will remain set until cleared by software writing 0.
1943 UINT32 GraphicsDriverLog
:1;
1945 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
1946 /// indicates that the Autonomous Utilization-Based Frequency Control
1947 /// Status bit has asserted since the log bit was last cleared. This log
1948 /// bit will remain set until cleared by software writing 0.
1950 UINT32 AutonomousUtilizationBasedFrequencyControlLog
:1;
1952 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
1953 /// Alert Status bit has asserted since the log bit was last cleared. This
1954 /// log bit will remain set until cleared by software writing 0.
1956 UINT32 VRThermAlertLog
:1;
1959 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
1960 /// Status bit has asserted since the log bit was last cleared. This log
1961 /// bit will remain set until cleared by software writing 0.
1963 UINT32 ElectricalDesignPointLog
:1;
1965 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core
1966 /// Power Limiting Status bit has asserted since the log bit was last
1967 /// cleared. This log bit will remain set until cleared by software
1970 UINT32 CorePowerLimitingLog
:1;
1972 /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates
1973 /// that the Package Level PL1 Power Limiting Status bit has asserted
1974 /// since the log bit was last cleared. This log bit will remain set until
1975 /// cleared by software writing 0.
1979 /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that
1980 /// the Package Level PL2 Power Limiting Status bit has asserted since the
1981 /// log bit was last cleared. This log bit will remain set until cleared
1982 /// by software writing 0.
1986 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
1987 /// Limit Status bit has asserted since the log bit was last cleared. This
1988 /// log bit will remain set until cleared by software writing 0.
1990 UINT32 MaxTurboLimitLog
:1;
1992 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
1993 /// Turbo Transition Attenuation Status bit has asserted since the log bit
1994 /// was last cleared. This log bit will remain set until cleared by
1995 /// software writing 0.
1997 UINT32 TurboTransitionAttenuationLog
:1;
1999 UINT32 Reserved7
:32;
2002 /// All bit fields as a 32-bit value
2006 /// All bit fields as a 64-bit value
2009 } MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER
;
2013 Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)
2014 (frequency refers to ring interconnect in the uncore).
2016 @param ECX MSR_HASWELL_RING_PERF_LIMIT_REASONS (0x000006B1)
2017 @param EAX Lower 32-bits of MSR value.
2018 Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.
2019 @param EDX Upper 32-bits of MSR value.
2020 Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.
2022 <b>Example usage</b>
2024 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER Msr;
2026 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS);
2027 AsmWriteMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS, Msr.Uint64);
2029 @note MSR_HASWELL_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.
2031 #define MSR_HASWELL_RING_PERF_LIMIT_REASONS 0x000006B1
2034 MSR information returned for MSR index #MSR_HASWELL_RING_PERF_LIMIT_REASONS
2038 /// Individual bit fields
2042 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the
2043 /// operating system request due to assertion of external PROCHOT.
2045 UINT32 PROCHOT_Status
:1;
2047 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
2048 /// operating system request due to a thermal event.
2050 UINT32 ThermalStatus
:1;
2053 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
2054 /// below the operating system request due to a thermal alert from the
2055 /// Voltage Regulator.
2057 UINT32 VRThermAlertStatus
:1;
2060 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
2061 /// reduced below the operating system request due to electrical design
2062 /// point constraints (e.g. maximum electrical current consumption).
2064 UINT32 ElectricalDesignPointStatus
:1;
2067 /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,
2068 /// frequency is reduced below the operating system request due to
2069 /// package-level power limiting PL1.
2073 /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,
2074 /// frequency is reduced below the operating system request due to
2075 /// package-level power limiting PL2.
2080 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
2081 /// has asserted since the log bit was last cleared. This log bit will
2082 /// remain set until cleared by software writing 0.
2084 UINT32 PROCHOT_Log
:1;
2086 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
2087 /// has asserted since the log bit was last cleared. This log bit will
2088 /// remain set until cleared by software writing 0.
2090 UINT32 ThermalLog
:1;
2093 /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics
2094 /// Driver Status bit has asserted since the log bit was last cleared.
2095 /// This log bit will remain set until cleared by software writing 0.
2097 UINT32 GraphicsDriverLog
:1;
2099 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
2100 /// indicates that the Autonomous Utilization-Based Frequency Control
2101 /// Status bit has asserted since the log bit was last cleared. This log
2102 /// bit will remain set until cleared by software writing 0.
2104 UINT32 AutonomousUtilizationBasedFrequencyControlLog
:1;
2106 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
2107 /// Alert Status bit has asserted since the log bit was last cleared. This
2108 /// log bit will remain set until cleared by software writing 0.
2110 UINT32 VRThermAlertLog
:1;
2113 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
2114 /// Status bit has asserted since the log bit was last cleared. This log
2115 /// bit will remain set until cleared by software writing 0.
2117 UINT32 ElectricalDesignPointLog
:1;
2119 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core
2120 /// Power Limiting Status bit has asserted since the log bit was last
2121 /// cleared. This log bit will remain set until cleared by software
2124 UINT32 CorePowerLimitingLog
:1;
2126 /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates
2127 /// that the Package Level PL1 Power Limiting Status bit has asserted
2128 /// since the log bit was last cleared. This log bit will remain set until
2129 /// cleared by software writing 0.
2133 /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that
2134 /// the Package Level PL2 Power Limiting Status bit has asserted since the
2135 /// log bit was last cleared. This log bit will remain set until cleared
2136 /// by software writing 0.
2140 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
2141 /// Limit Status bit has asserted since the log bit was last cleared. This
2142 /// log bit will remain set until cleared by software writing 0.
2144 UINT32 MaxTurboLimitLog
:1;
2146 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
2147 /// Turbo Transition Attenuation Status bit has asserted since the log bit
2148 /// was last cleared. This log bit will remain set until cleared by
2149 /// software writing 0.
2151 UINT32 TurboTransitionAttenuationLog
:1;
2153 UINT32 Reserved8
:32;
2156 /// All bit fields as a 32-bit value
2160 /// All bit fields as a 64-bit value
2163 } MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER
;
2167 Package. Uncore C-Box 0, counter 0 event select MSR.
2169 @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 (0x00000700)
2170 @param EAX Lower 32-bits of MSR value.
2171 @param EDX Upper 32-bits of MSR value.
2173 <b>Example usage</b>
2177 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0);
2178 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0, Msr);
2180 @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.
2182 #define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 0x00000700
2186 Package. Uncore C-Box 0, counter 1 event select MSR.
2188 @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 (0x00000701)
2189 @param EAX Lower 32-bits of MSR value.
2190 @param EDX Upper 32-bits of MSR value.
2192 <b>Example usage</b>
2196 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1);
2197 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1, Msr);
2199 @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.
2201 #define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 0x00000701
2205 Package. Uncore C-Box 0, performance counter 0.
2207 @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR0 (0x00000706)
2208 @param EAX Lower 32-bits of MSR value.
2209 @param EDX Upper 32-bits of MSR value.
2211 <b>Example usage</b>
2215 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0);
2216 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0, Msr);
2218 @note MSR_HASWELL_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.
2220 #define MSR_HASWELL_UNC_CBO_0_PERFCTR0 0x00000706
2224 Package. Uncore C-Box 0, performance counter 1.
2226 @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR1 (0x00000707)
2227 @param EAX Lower 32-bits of MSR value.
2228 @param EDX Upper 32-bits of MSR value.
2230 <b>Example usage</b>
2234 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1);
2235 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1, Msr);
2237 @note MSR_HASWELL_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.
2239 #define MSR_HASWELL_UNC_CBO_0_PERFCTR1 0x00000707
2243 Package. Uncore C-Box 1, counter 0 event select MSR.
2245 @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 (0x00000710)
2246 @param EAX Lower 32-bits of MSR value.
2247 @param EDX Upper 32-bits of MSR value.
2249 <b>Example usage</b>
2253 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0);
2254 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0, Msr);
2256 @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.
2258 #define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 0x00000710
2262 Package. Uncore C-Box 1, counter 1 event select MSR.
2264 @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 (0x00000711)
2265 @param EAX Lower 32-bits of MSR value.
2266 @param EDX Upper 32-bits of MSR value.
2268 <b>Example usage</b>
2272 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1);
2273 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1, Msr);
2275 @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.
2277 #define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 0x00000711
2281 Package. Uncore C-Box 1, performance counter 0.
2283 @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR0 (0x00000716)
2284 @param EAX Lower 32-bits of MSR value.
2285 @param EDX Upper 32-bits of MSR value.
2287 <b>Example usage</b>
2291 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0);
2292 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0, Msr);
2294 @note MSR_HASWELL_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.
2296 #define MSR_HASWELL_UNC_CBO_1_PERFCTR0 0x00000716
2300 Package. Uncore C-Box 1, performance counter 1.
2302 @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR1 (0x00000717)
2303 @param EAX Lower 32-bits of MSR value.
2304 @param EDX Upper 32-bits of MSR value.
2306 <b>Example usage</b>
2310 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1);
2311 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1, Msr);
2313 @note MSR_HASWELL_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.
2315 #define MSR_HASWELL_UNC_CBO_1_PERFCTR1 0x00000717
2319 Package. Uncore C-Box 2, counter 0 event select MSR.
2321 @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 (0x00000720)
2322 @param EAX Lower 32-bits of MSR value.
2323 @param EDX Upper 32-bits of MSR value.
2325 <b>Example usage</b>
2329 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0);
2330 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0, Msr);
2332 @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.
2334 #define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 0x00000720
2338 Package. Uncore C-Box 2, counter 1 event select MSR.
2340 @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 (0x00000721)
2341 @param EAX Lower 32-bits of MSR value.
2342 @param EDX Upper 32-bits of MSR value.
2344 <b>Example usage</b>
2348 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1);
2349 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1, Msr);
2351 @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.
2353 #define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 0x00000721
2357 Package. Uncore C-Box 2, performance counter 0.
2359 @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR0 (0x00000726)
2360 @param EAX Lower 32-bits of MSR value.
2361 @param EDX Upper 32-bits of MSR value.
2363 <b>Example usage</b>
2367 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0);
2368 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0, Msr);
2370 @note MSR_HASWELL_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.
2372 #define MSR_HASWELL_UNC_CBO_2_PERFCTR0 0x00000726
2376 Package. Uncore C-Box 2, performance counter 1.
2378 @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR1 (0x00000727)
2379 @param EAX Lower 32-bits of MSR value.
2380 @param EDX Upper 32-bits of MSR value.
2382 <b>Example usage</b>
2386 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1);
2387 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1, Msr);
2389 @note MSR_HASWELL_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.
2391 #define MSR_HASWELL_UNC_CBO_2_PERFCTR1 0x00000727
2395 Package. Uncore C-Box 3, counter 0 event select MSR.
2397 @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 (0x00000730)
2398 @param EAX Lower 32-bits of MSR value.
2399 @param EDX Upper 32-bits of MSR value.
2401 <b>Example usage</b>
2405 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0);
2406 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0, Msr);
2408 @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.
2410 #define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 0x00000730
2414 Package. Uncore C-Box 3, counter 1 event select MSR.
2416 @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 (0x00000731)
2417 @param EAX Lower 32-bits of MSR value.
2418 @param EDX Upper 32-bits of MSR value.
2420 <b>Example usage</b>
2424 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1);
2425 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1, Msr);
2427 @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.
2429 #define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 0x00000731
2433 Package. Uncore C-Box 3, performance counter 0.
2435 @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR0 (0x00000736)
2436 @param EAX Lower 32-bits of MSR value.
2437 @param EDX Upper 32-bits of MSR value.
2439 <b>Example usage</b>
2443 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0);
2444 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0, Msr);
2446 @note MSR_HASWELL_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.
2448 #define MSR_HASWELL_UNC_CBO_3_PERFCTR0 0x00000736
2452 Package. Uncore C-Box 3, performance counter 1.
2454 @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR1 (0x00000737)
2455 @param EAX Lower 32-bits of MSR value.
2456 @param EDX Upper 32-bits of MSR value.
2458 <b>Example usage</b>
2462 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1);
2463 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1, Msr);
2465 @note MSR_HASWELL_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.
2467 #define MSR_HASWELL_UNC_CBO_3_PERFCTR1 0x00000737
2471 Package. Note: C-state values are processor specific C-state code names,
2472 unrelated to MWAIT extension C-state parameters or ACPI C-States.
2474 @param ECX MSR_HASWELL_PKG_C8_RESIDENCY (0x00000630)
2475 @param EAX Lower 32-bits of MSR value.
2476 Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.
2477 @param EDX Upper 32-bits of MSR value.
2478 Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.
2480 <b>Example usage</b>
2482 MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER Msr;
2484 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY);
2485 AsmWriteMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY, Msr.Uint64);
2487 @note MSR_HASWELL_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM.
2489 #define MSR_HASWELL_PKG_C8_RESIDENCY 0x00000630
2492 MSR information returned for MSR index #MSR_HASWELL_PKG_C8_RESIDENCY
2496 /// Individual bit fields
2500 /// [Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset
2501 /// that this package is in processor-specific C8 states. Count at the
2502 /// same frequency as the TSC.
2504 UINT32 C8ResidencyCounter
:32;
2506 /// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last
2507 /// reset that this package is in processor-specific C8 states. Count at
2508 /// the same frequency as the TSC.
2510 UINT32 C8ResidencyCounterHi
:28;
2514 /// All bit fields as a 64-bit value
2517 } MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER
;
2521 Package. Note: C-state values are processor specific C-state code names,
2522 unrelated to MWAIT extension C-state parameters or ACPI C-States.
2524 @param ECX MSR_HASWELL_PKG_C9_RESIDENCY (0x00000631)
2525 @param EAX Lower 32-bits of MSR value.
2526 Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.
2527 @param EDX Upper 32-bits of MSR value.
2528 Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.
2530 <b>Example usage</b>
2532 MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER Msr;
2534 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY);
2535 AsmWriteMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY, Msr.Uint64);
2537 @note MSR_HASWELL_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM.
2539 #define MSR_HASWELL_PKG_C9_RESIDENCY 0x00000631
2542 MSR information returned for MSR index #MSR_HASWELL_PKG_C9_RESIDENCY
2546 /// Individual bit fields
2550 /// [Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset
2551 /// that this package is in processor-specific C9 states. Count at the
2552 /// same frequency as the TSC.
2554 UINT32 C9ResidencyCounter
:32;
2556 /// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last
2557 /// reset that this package is in processor-specific C9 states. Count at
2558 /// the same frequency as the TSC.
2560 UINT32 C9ResidencyCounterHi
:28;
2564 /// All bit fields as a 64-bit value
2567 } MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER
;
2571 Package. Note: C-state values are processor specific C-state code names,
2572 unrelated to MWAIT extension C-state parameters or ACPI C-States.
2574 @param ECX MSR_HASWELL_PKG_C10_RESIDENCY (0x00000632)
2575 @param EAX Lower 32-bits of MSR value.
2576 Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.
2577 @param EDX Upper 32-bits of MSR value.
2578 Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.
2580 <b>Example usage</b>
2582 MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER Msr;
2584 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY);
2585 AsmWriteMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY, Msr.Uint64);
2587 @note MSR_HASWELL_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.
2589 #define MSR_HASWELL_PKG_C10_RESIDENCY 0x00000632
2592 MSR information returned for MSR index #MSR_HASWELL_PKG_C10_RESIDENCY
2596 /// Individual bit fields
2600 /// [Bits 31:0] Package C10 Residency Counter. (R/O) Value since last
2601 /// reset that this package is in processor-specific C10 states. Count at
2602 /// the same frequency as the TSC.
2604 UINT32 C10ResidencyCounter
:32;
2606 /// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last
2607 /// reset that this package is in processor-specific C10 states. Count at
2608 /// the same frequency as the TSC.
2610 UINT32 C10ResidencyCounterHi
:28;
2614 /// All bit fields as a 64-bit value
2617 } MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER
;