UefiCpuPkg/Include/Register/Msr/P6Msr.h

   1 /** @file
   2   MSR Definitions for P6 Family Processors.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
  10   This program and the accompanying materials
  11   are licensed and made available under the terms and conditions of the BSD License
  12   which accompanies this distribution.  The full text of the license may be found at
  13   http://opensource.org/licenses/bsd-license.php
  14
  15   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17
  18   @par Specification Reference:
  19   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
  20   December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-19.
  21
  22 **/
  23
  24 #ifndef __P6_MSR_H__
  25 #define __P6_MSR_H__
  26
  27 #include <Register/ArchitecturalMsr.h>
  28
  29 /**
  30   See Section 35.20, "MSRs in Pentium Processors.".
  31
  32   @param  ECX  MSR_P6_P5_MC_ADDR (0x00000000)
  33   @param  EAX  Lower 32-bits of MSR value.
  34   @param  EDX  Upper 32-bits of MSR value.
  35
  36   <b>Example usage</b>
  37   @code
  38   UINT64  Msr;
  39
  40   Msr = AsmReadMsr64 (MSR_P6_P5_MC_ADDR);
  41   AsmWriteMsr64 (MSR_P6_P5_MC_ADDR, Msr);
  42   @endcode
  43 **/
  44 #define MSR_P6_P5_MC_ADDR                        0x00000000
  45
  46
  47 /**
  48   See Section 35.20, "MSRs in Pentium Processors.".
  49
  50   @param  ECX  MSR_P6_P5_MC_TYPE (0x00000001)
  51   @param  EAX  Lower 32-bits of MSR value.
  52   @param  EDX  Upper 32-bits of MSR value.
  53
  54   <b>Example usage</b>
  55   @code
  56   UINT64  Msr;
  57
  58   Msr = AsmReadMsr64 (MSR_P6_P5_MC_TYPE);
  59   AsmWriteMsr64 (MSR_P6_P5_MC_TYPE, Msr);
  60   @endcode
  61 **/
  62 #define MSR_P6_P5_MC_TYPE                        0x00000001
  63
  64
  65 /**
  66   See Section 17.14, "Time-Stamp Counter.".
  67
  68   @param  ECX  MSR_P6_TSC (0x00000010)
  69   @param  EAX  Lower 32-bits of MSR value.
  70   @param  EDX  Upper 32-bits of MSR value.
  71
  72   <b>Example usage</b>
  73   @code
  74   UINT64  Msr;
  75
  76   Msr = AsmReadMsr64 (MSR_P6_TSC);
  77   AsmWriteMsr64 (MSR_P6_TSC, Msr);
  78   @endcode
  79 **/
  80 #define MSR_P6_TSC                               0x00000010
  81
  82
  83 /**
  84   Platform ID (R)  The operating system can use this MSR to determine "slot"
  85   information for the processor and the proper microcode update to load.
  86
  87   @param  ECX  MSR_P6_IA32_PLATFORM_ID (0x00000017)
  88   @param  EAX  Lower 32-bits of MSR value.
  89                Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.
  90   @param  EDX  Upper 32-bits of MSR value.
  91                Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.
  92
  93   <b>Example usage</b>
  94   @code
  95   MSR_P6_IA32_PLATFORM_ID_REGISTER  Msr;
  96
  97   Msr.Uint64 = AsmReadMsr64 (MSR_P6_IA32_PLATFORM_ID);
  98   @endcode
  99 **/
 100 #define MSR_P6_IA32_PLATFORM_ID                  0x00000017
 101
 102 /**
 103   MSR information returned for MSR index #MSR_P6_IA32_PLATFORM_ID
 104 **/
 105 typedef union {
 106   ///
 107   /// Individual bit fields
 108   ///
 109   struct {
 110     UINT32  Reserved1:32;
 111     UINT32  Reserved2:18;
 112     ///
 113     /// [Bits 52:50] Platform Id (R) Contains information concerning the
 114     /// intended platform for the processor.
 115     ///
 116     ///  52 51 50
 117     ///   0  0  0  Processor Flag 0.
 118     ///   0  0  1  Processor Flag 1
 119     ///   0  1  0  Processor Flag 2
 120     ///   0  1  1  Processor Flag 3
 121     ///   1  0  0  Processor Flag 4
 122     ///   1  0  1  Processor Flag 5
 123     ///   1  1  0  Processor Flag 6
 124     ///   1  1  1  Processor Flag 7
 125     ///
 126     UINT32  PlatformId:3;
 127     ///
 128     /// [Bits 56:53] L2 Cache Latency Read.
 129     ///
 130     UINT32  L2CacheLatencyRead:4;
 131     UINT32  Reserved3:3;
 132     ///
 133     /// [Bit 60] Clock Frequency Ratio Read.
 134     ///
 135     UINT32  ClockFrequencyRatioRead:1;
 136     UINT32  Reserved4:3;
 137   } Bits;
 138   ///
 139   /// All bit fields as a 64-bit value
 140   ///
 141   UINT64  Uint64;
 142 } MSR_P6_IA32_PLATFORM_ID_REGISTER;
 143
 144
 145 /**
 146   Section 10.4.4, "Local APIC Status and Location.".
 147
 148   @param  ECX  MSR_P6_APIC_BASE (0x0000001B)
 149   @param  EAX  Lower 32-bits of MSR value.
 150                Described by the type MSR_P6_APIC_BASE_REGISTER.
 151   @param  EDX  Upper 32-bits of MSR value.
 152                Described by the type MSR_P6_APIC_BASE_REGISTER.
 153
 154   <b>Example usage</b>
 155   @code
 156   MSR_P6_APIC_BASE_REGISTER  Msr;
 157
 158   Msr.Uint64 = AsmReadMsr64 (MSR_P6_APIC_BASE);
 159   AsmWriteMsr64 (MSR_P6_APIC_BASE, Msr.Uint64);
 160   @endcode
 161 **/
 162 #define MSR_P6_APIC_BASE                         0x0000001B
 163
 164 /**
 165   MSR information returned for MSR index #MSR_P6_APIC_BASE
 166 **/
 167 typedef union {
 168   ///
 169   /// Individual bit fields
 170   ///
 171   struct {
 172     UINT32  Reserved1:8;
 173     ///
 174     /// [Bit 8] Boot Strap Processor indicator Bit 1 = BSP.
 175     ///
 176     UINT32  BSP:1;
 177     UINT32  Reserved2:2;
 178     ///
 179     /// [Bit 11] APIC Global Enable Bit - Permanent till reset 1 = Enabled 0 =
 180     /// Disabled.
 181     ///
 182     UINT32  EN:1;
 183     ///
 184     /// [Bits 31:12] APIC Base Address.
 185     ///
 186     UINT32  ApicBase:20;
 187     UINT32  Reserved3:32;
 188   } Bits;
 189   ///
 190   /// All bit fields as a 32-bit value
 191   ///
 192   UINT32  Uint32;
 193   ///
 194   /// All bit fields as a 64-bit value
 195   ///
 196   UINT64  Uint64;
 197 } MSR_P6_APIC_BASE_REGISTER;
 198
 199
 200 /**
 201   Processor Hard Power-On Configuration (R/W) Enables and disables processor
 202   features; (R) indicates current processor configuration.
 203
 204   @param  ECX  MSR_P6_EBL_CR_POWERON (0x0000002A)
 205   @param  EAX  Lower 32-bits of MSR value.
 206                Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.
 207   @param  EDX  Upper 32-bits of MSR value.
 208                Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.
 209
 210   <b>Example usage</b>
 211   @code
 212   MSR_P6_EBL_CR_POWERON_REGISTER  Msr;
 213
 214   Msr.Uint64 = AsmReadMsr64 (MSR_P6_EBL_CR_POWERON);
 215   AsmWriteMsr64 (MSR_P6_EBL_CR_POWERON, Msr.Uint64);
 216   @endcode
 217 **/
 218 #define MSR_P6_EBL_CR_POWERON                    0x0000002A
 219
 220 /**
 221   MSR information returned for MSR index #MSR_P6_EBL_CR_POWERON
 222 **/
 223 typedef union {
 224   ///
 225   /// Individual bit fields
 226   ///
 227   struct {
 228     UINT32  Reserved1:1;
 229     ///
 230     /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled 0 = Disabled.
 231     ///
 232     UINT32  DataErrorCheckingEnable:1;
 233     ///
 234     /// [Bit 2] Response Error Checking Enable FRCERR Observation Enable (R/W)
 235     /// 1 = Enabled 0 = Disabled.
 236     ///
 237     UINT32  ResponseErrorCheckingEnable:1;
 238     ///
 239     /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled 0 = Disabled.
 240     ///
 241     UINT32  AERR_DriveEnable:1;
 242     ///
 243     /// [Bit 4] BERR# Enable for Initiator Bus Requests (R/W) 1 = Enabled 0 =
 244     /// Disabled.
 245     ///
 246     UINT32  BERR_Enable:1;
 247     UINT32  Reserved2:1;
 248     ///
 249     /// [Bit 6] BERR# Driver Enable for Initiator Internal Errors (R/W) 1 =
 250     /// Enabled 0 = Disabled.
 251     ///
 252     UINT32  BERR_DriverEnable:1;
 253     ///
 254     /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled 0 = Disabled.
 255     ///
 256     UINT32  BINIT_DriverEnable:1;
 257     ///
 258     /// [Bit 8] Output Tri-state Enabled (R) 1 = Enabled 0 = Disabled.
 259     ///
 260     UINT32  OutputTriStateEnable:1;
 261     ///
 262     /// [Bit 9] Execute BIST (R) 1 = Enabled 0 = Disabled.
 263     ///
 264     UINT32  ExecuteBIST:1;
 265     ///
 266     /// [Bit 10] AERR# Observation Enabled (R) 1 = Enabled 0 = Disabled.
 267     ///
 268     UINT32  AERR_ObservationEnabled:1;
 269     UINT32  Reserved3:1;
 270     ///
 271     /// [Bit 12] BINIT# Observation Enabled (R) 1 = Enabled 0 = Disabled.
 272     ///
 273     UINT32  BINIT_ObservationEnabled:1;
 274     ///
 275     /// [Bit 13] In Order Queue Depth (R) 1 = 1 0 = 8.
 276     ///
 277     UINT32  InOrderQueueDepth:1;
 278     ///
 279     /// [Bit 14] 1-MByte Power on Reset Vector (R) 1 = 1MByte 0 = 4GBytes.
 280     ///
 281     UINT32  ResetVector:1;
 282     ///
 283     /// [Bit 15] FRC Mode Enable (R) 1 = Enabled 0 = Disabled.
 284     ///
 285     UINT32  FRCModeEnable:1;
 286     ///
 287     /// [Bits 17:16] APIC Cluster ID (R).
 288     ///
 289     UINT32  APICClusterID:2;
 290     ///
 291     /// [Bits 19:18] System Bus Frequency (R) 00 = 66MHz 10 = 100Mhz 01 =
 292     /// 133MHz 11 = Reserved.
 293     ///
 294     UINT32  SystemBusFrequency:2;
 295     ///
 296     /// [Bits 21:20] Symmetric Arbitration ID (R).
 297     ///
 298     UINT32  SymmetricArbitrationID:2;
 299     ///
 300     /// [Bits 25:22] Clock Frequency Ratio (R).
 301     ///
 302     UINT32  ClockFrequencyRatio:4;
 303     ///
 304     /// [Bit 26] Low Power Mode Enable (R/W).
 305     ///
 306     UINT32  LowPowerModeEnable:1;
 307     ///
 308     /// [Bit 27] Clock Frequency Ratio.
 309     ///
 310     UINT32  ClockFrequencyRatio1:1;
 311     UINT32  Reserved4:4;
 312     UINT32  Reserved5:32;
 313   } Bits;
 314   ///
 315   /// All bit fields as a 32-bit value
 316   ///
 317   UINT32  Uint32;
 318   ///
 319   /// All bit fields as a 64-bit value
 320   ///
 321   UINT64  Uint64;
 322 } MSR_P6_EBL_CR_POWERON_REGISTER;
 323
 324
 325 /**
 326   Test Control Register.
 327
 328   @param  ECX  MSR_P6_TEST_CTL (0x00000033)
 329   @param  EAX  Lower 32-bits of MSR value.
 330                Described by the type MSR_P6_TEST_CTL_REGISTER.
 331   @param  EDX  Upper 32-bits of MSR value.
 332                Described by the type MSR_P6_TEST_CTL_REGISTER.
 333
 334   <b>Example usage</b>
 335   @code
 336   MSR_P6_TEST_CTL_REGISTER  Msr;
 337
 338   Msr.Uint64 = AsmReadMsr64 (MSR_P6_TEST_CTL);
 339   AsmWriteMsr64 (MSR_P6_TEST_CTL, Msr.Uint64);
 340   @endcode
 341 **/
 342 #define MSR_P6_TEST_CTL                          0x00000033
 343
 344 /**
 345   MSR information returned for MSR index #MSR_P6_TEST_CTL
 346 **/
 347 typedef union {
 348   ///
 349   /// Individual bit fields
 350   ///
 351   struct {
 352     UINT32  Reserved1:30;
 353     ///
 354     /// [Bit 30] Streaming Buffer Disable.
 355     ///
 356     UINT32  StreamingBufferDisable:1;
 357     ///
 358     /// [Bit 31] Disable LOCK# Assertion for split locked access.
 359     ///
 360     UINT32  Disable_LOCK:1;
 361     UINT32  Reserved2:32;
 362   } Bits;
 363   ///
 364   /// All bit fields as a 32-bit value
 365   ///
 366   UINT32  Uint32;
 367   ///
 368   /// All bit fields as a 64-bit value
 369   ///
 370   UINT64  Uint64;
 371 } MSR_P6_TEST_CTL_REGISTER;
 372
 373
 374 /**
 375   BIOS Update Trigger Register.
 376
 377   @param  ECX  MSR_P6_BIOS_UPDT_TRIG (0x00000079)
 378   @param  EAX  Lower 32-bits of MSR value.
 379   @param  EDX  Upper 32-bits of MSR value.
 380
 381   <b>Example usage</b>
 382   @code
 383   UINT64  Msr;
 384
 385   Msr = AsmReadMsr64 (MSR_P6_BIOS_UPDT_TRIG);
 386   AsmWriteMsr64 (MSR_P6_BIOS_UPDT_TRIG, Msr);
 387   @endcode
 388 **/
 389 #define MSR_P6_BIOS_UPDT_TRIG                    0x00000079
 390
 391
 392 /**
 393   Chunk n data register D[63:0]: used to write to and read from the L2.
 394
 395   @param  ECX  MSR_P6_BBL_CR_Dn
 396   @param  EAX  Lower 32-bits of MSR value.
 397   @param  EDX  Upper 32-bits of MSR value.
 398
 399   <b>Example usage</b>
 400   @code
 401   UINT64  Msr;
 402
 403   Msr = AsmReadMsr64 (MSR_P6_BBL_CR_D0);
 404   AsmWriteMsr64 (MSR_P6_BBL_CR_D0, Msr);
 405   @endcode
 406   @{
 407 **/
 408 #define MSR_P6_BBL_CR_D0                         0x00000088
 409 #define MSR_P6_BBL_CR_D1                         0x00000089
 410 #define MSR_P6_BBL_CR_D2                         0x0000008A
 411 /// @}
 412
 413
 414 /**
 415   BIOS Update Signature Register or Chunk 3 data register D[63:0] Used to
 416   write to and read from the L2 depending on the usage model.
 417
 418   @param  ECX  MSR_P6_BIOS_SIGN (0x0000008B)
 419   @param  EAX  Lower 32-bits of MSR value.
 420   @param  EDX  Upper 32-bits of MSR value.
 421
 422   <b>Example usage</b>
 423   @code
 424   UINT64  Msr;
 425
 426   Msr = AsmReadMsr64 (MSR_P6_BIOS_SIGN);
 427   AsmWriteMsr64 (MSR_P6_BIOS_SIGN, Msr);
 428   @endcode
 429 **/
 430 #define MSR_P6_BIOS_SIGN                         0x0000008B
 431
 432
 433 /**
 434
 435
 436   @param  ECX  MSR_P6_PERFCTR0 (0x000000C1)
 437   @param  EAX  Lower 32-bits of MSR value.
 438   @param  EDX  Upper 32-bits of MSR value.
 439
 440   <b>Example usage</b>
 441   @code
 442   UINT64  Msr;
 443
 444   Msr = AsmReadMsr64 (MSR_P6_PERFCTR0);
 445   AsmWriteMsr64 (MSR_P6_PERFCTR0, Msr);
 446   @endcode
 447   @{
 448 **/
 449 #define MSR_P6_PERFCTR0                          0x000000C1
 450 #define MSR_P6_PERFCTR1                          0x000000C2
 451 /// @}
 452
 453
 454 /**
 455
 456
 457   @param  ECX  MSR_P6_MTRRCAP (0x000000FE)
 458   @param  EAX  Lower 32-bits of MSR value.
 459   @param  EDX  Upper 32-bits of MSR value.
 460
 461   <b>Example usage</b>
 462   @code
 463   UINT64  Msr;
 464
 465   Msr = AsmReadMsr64 (MSR_P6_MTRRCAP);
 466   AsmWriteMsr64 (MSR_P6_MTRRCAP, Msr);
 467   @endcode
 468 **/
 469 #define MSR_P6_MTRRCAP                           0x000000FE
 470
 471
 472 /**
 473   Address register: used to send specified address (A31-A3) to L2 during cache
 474   initialization accesses.
 475
 476   @param  ECX  MSR_P6_BBL_CR_ADDR (0x00000116)
 477   @param  EAX  Lower 32-bits of MSR value.
 478                Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.
 479   @param  EDX  Upper 32-bits of MSR value.
 480                Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.
 481
 482   <b>Example usage</b>
 483   @code
 484   MSR_P6_BBL_CR_ADDR_REGISTER  Msr;
 485
 486   Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_ADDR);
 487   AsmWriteMsr64 (MSR_P6_BBL_CR_ADDR, Msr.Uint64);
 488   @endcode
 489 **/
 490 #define MSR_P6_BBL_CR_ADDR                       0x00000116
 491
 492 /**
 493   MSR information returned for MSR index #MSR_P6_BBL_CR_ADDR
 494 **/
 495 typedef union {
 496   ///
 497   /// Individual bit fields
 498   ///
 499   struct {
 500     UINT32  Reserved1:3;
 501     ///
 502     /// [Bits 31:3] Address bits
 503     ///
 504     UINT32  Address:29;
 505     UINT32  Reserved2:32;
 506   } Bits;
 507   ///
 508   /// All bit fields as a 32-bit value
 509   ///
 510   UINT32  Uint32;
 511   ///
 512   /// All bit fields as a 64-bit value
 513   ///
 514   UINT64  Uint64;
 515 } MSR_P6_BBL_CR_ADDR_REGISTER;
 516
 517
 518 /**
 519   Data ECC register D[7:0]: used to write ECC and read ECC to/from L2.
 520
 521   @param  ECX  MSR_P6_BBL_CR_DECC (0x00000118)
 522   @param  EAX  Lower 32-bits of MSR value.
 523   @param  EDX  Upper 32-bits of MSR value.
 524
 525   <b>Example usage</b>
 526   @code
 527   UINT64  Msr;
 528
 529   Msr = AsmReadMsr64 (MSR_P6_BBL_CR_DECC);
 530   AsmWriteMsr64 (MSR_P6_BBL_CR_DECC, Msr);
 531   @endcode
 532 **/
 533 #define MSR_P6_BBL_CR_DECC                       0x00000118
 534
 535
 536 /**
 537   Control register: used to program L2 commands to be issued via cache
 538   configuration accesses mechanism. Also receives L2 lookup response.
 539
 540   @param  ECX  MSR_P6_BBL_CR_CTL (0x00000119)
 541   @param  EAX  Lower 32-bits of MSR value.
 542                Described by the type MSR_P6_BBL_CR_CTL_REGISTER.
 543   @param  EDX  Upper 32-bits of MSR value.
 544                Described by the type MSR_P6_BBL_CR_CTL_REGISTER.
 545
 546   <b>Example usage</b>
 547   @code
 548   MSR_P6_BBL_CR_CTL_REGISTER  Msr;
 549
 550   Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL);
 551   AsmWriteMsr64 (MSR_P6_BBL_CR_CTL, Msr.Uint64);
 552   @endcode
 553 **/
 554 #define MSR_P6_BBL_CR_CTL                        0x00000119
 555
 556 /**
 557   MSR information returned for MSR index #MSR_P6_BBL_CR_CTL
 558 **/
 559 typedef union {
 560   ///
 561   /// Individual bit fields
 562   ///
 563   struct {
 564     ///
 565     /// [Bits 4:0] L2 Command
 566     ///   Data Read w/ LRU update (RLU)
 567     ///   Tag Read w/ Data Read (TRR)
 568     ///   Tag Inquire (TI)
 569     ///   L2 Control Register Read (CR)
 570     ///   L2 Control Register Write (CW)
 571     ///   Tag Write w/ Data Read (TWR)
 572     ///   Tag Write w/ Data Write (TWW)
 573     ///   Tag Write (TW).
 574     ///
 575     UINT32  L2Command:5;
 576     ///
 577     /// [Bits 6:5] State to L2
 578     ///
 579     UINT32  StateToL2:2;
 580     UINT32  Reserved:1;
 581     ///
 582     /// [Bits 9:8] Way to L2.
 583     ///
 584     UINT32  WayToL2:2;
 585     ///
 586     /// [Bits 11:10] Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11.
 587     ///
 588     UINT32  Way:2;
 589     ///
 590     /// [Bits 13:12] Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00.
 591     ///
 592     UINT32  MESI:2;
 593     ///
 594     /// [Bits 15:14] State from L2.
 595     ///
 596     UINT32  StateFromL2:2;
 597     UINT32  Reserved2:1;
 598     ///
 599     /// [Bit 17] L2 Hit.
 600     ///
 601     UINT32  L2Hit:1;
 602     UINT32  Reserved3:1;
 603     ///
 604     /// [Bits 20:19] User supplied ECC.
 605     ///
 606     UINT32  UserEcc:2;
 607     ///
 608     /// [Bit 21] Processor number Disable = 1 Enable = 0 Reserved.
 609     ///
 610     UINT32  ProcessorNumber:1;
 611     UINT32  Reserved4:10;
 612     UINT32  Reserved5:32;
 613   } Bits;
 614   ///
 615   /// All bit fields as a 32-bit value
 616   ///
 617   UINT32  Uint32;
 618   ///
 619   /// All bit fields as a 64-bit value
 620   ///
 621   UINT64  Uint64;
 622 } MSR_P6_BBL_CR_CTL_REGISTER;
 623
 624
 625 /**
 626   Trigger register: used to initiate a cache configuration accesses access,
 627   Write only with Data = 0.
 628
 629   @param  ECX  MSR_P6_BBL_CR_TRIG (0x0000011A)
 630   @param  EAX  Lower 32-bits of MSR value.
 631   @param  EDX  Upper 32-bits of MSR value.
 632
 633   <b>Example usage</b>
 634   @code
 635   UINT64  Msr;
 636
 637   Msr = AsmReadMsr64 (MSR_P6_BBL_CR_TRIG);
 638   AsmWriteMsr64 (MSR_P6_BBL_CR_TRIG, Msr);
 639   @endcode
 640 **/
 641 #define MSR_P6_BBL_CR_TRIG                       0x0000011A
 642
 643
 644 /**
 645   Busy register: indicates when a cache configuration accesses L2 command is
 646   in progress. D[0] = 1 = BUSY.
 647
 648   @param  ECX  MSR_P6_BBL_CR_BUSY (0x0000011B)
 649   @param  EAX  Lower 32-bits of MSR value.
 650   @param  EDX  Upper 32-bits of MSR value.
 651
 652   <b>Example usage</b>
 653   @code
 654   UINT64  Msr;
 655
 656   Msr = AsmReadMsr64 (MSR_P6_BBL_CR_BUSY);
 657   AsmWriteMsr64 (MSR_P6_BBL_CR_BUSY, Msr);
 658   @endcode
 659 **/
 660 #define MSR_P6_BBL_CR_BUSY                       0x0000011B
 661
 662
 663 /**
 664   Control register 3: used to configure the L2 Cache.
 665
 666   @param  ECX  MSR_P6_BBL_CR_CTL3 (0x0000011E)
 667   @param  EAX  Lower 32-bits of MSR value.
 668                Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.
 669   @param  EDX  Upper 32-bits of MSR value.
 670                Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.
 671
 672   <b>Example usage</b>
 673   @code
 674   MSR_P6_BBL_CR_CTL3_REGISTER  Msr;
 675
 676   Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL3);
 677   AsmWriteMsr64 (MSR_P6_BBL_CR_CTL3, Msr.Uint64);
 678   @endcode
 679 **/
 680 #define MSR_P6_BBL_CR_CTL3                       0x0000011E
 681
 682 /**
 683   MSR information returned for MSR index #MSR_P6_BBL_CR_CTL3
 684 **/
 685 typedef union {
 686   ///
 687   /// Individual bit fields
 688   ///
 689   struct {
 690     ///
 691     /// [Bit 0] L2 Configured (read/write ).
 692     ///
 693     UINT32  L2Configured:1;
 694     ///
 695     /// [Bits 4:1] L2 Cache Latency (read/write).
 696     ///
 697     UINT32  L2CacheLatency:4;
 698     ///
 699     /// [Bit 5] ECC Check Enable (read/write).
 700     ///
 701     UINT32  ECCCheckEnable:1;
 702     ///
 703     /// [Bit 6] Address Parity Check Enable (read/write).
 704     ///
 705     UINT32  AddressParityCheckEnable:1;
 706     ///
 707     /// [Bit 7] CRTN Parity Check Enable (read/write).
 708     ///
 709     UINT32  CRTNParityCheckEnable:1;
 710     ///
 711     /// [Bit 8] L2 Enabled (read/write).
 712     ///
 713     UINT32  L2Enabled:1;
 714     ///
 715     /// [Bits 10:9] L2 Associativity (read only) Direct Mapped 2 Way 4 Way
 716     /// Reserved.
 717     ///
 718     UINT32  L2Associativity:2;
 719     ///
 720     /// [Bits 12:11] Number of L2 banks (read only).
 721     ///
 722     UINT32  L2Banks:2;
 723     ///
 724     /// [Bits 17:13] Cache size per bank (read/write) 256KBytes 512KBytes
 725     /// 1MByte 2MByte 4MBytes.
 726     ///
 727     UINT32  CacheSizePerBank:5;
 728     ///
 729     /// [Bit 18] Cache State error checking enable (read/write).
 730     ///
 731     UINT32  CacheStateErrorEnable:1;
 732     UINT32  Reserved1:1;
 733     ///
 734     /// [Bits 22:20] L2 Physical Address Range support 64GBytes 32GBytes
 735     /// 16GBytes 8GBytes 4GBytes 2GBytes 1GBytes 512MBytes.
 736     ///
 737     UINT32  L2AddressRange:3;
 738     ///
 739     /// [Bit 23] L2 Hardware Disable (read only).
 740     ///
 741     UINT32  L2HardwareDisable:1;
 742     UINT32  Reserved2:1;
 743     ///
 744     /// [Bit 25] Cache bus fraction (read only).
 745     ///
 746     UINT32  CacheBusFraction:1;
 747     UINT32  Reserved3:6;
 748     UINT32  Reserved4:32;
 749   } Bits;
 750   ///
 751   /// All bit fields as a 32-bit value
 752   ///
 753   UINT32  Uint32;
 754   ///
 755   /// All bit fields as a 64-bit value
 756   ///
 757   UINT64  Uint64;
 758 } MSR_P6_BBL_CR_CTL3_REGISTER;
 759
 760
 761 /**
 762   CS register target for CPL 0 code.
 763
 764   @param  ECX  MSR_P6_SYSENTER_CS_MSR (0x00000174)
 765   @param  EAX  Lower 32-bits of MSR value.
 766   @param  EDX  Upper 32-bits of MSR value.
 767
 768   <b>Example usage</b>
 769   @code
 770   UINT64  Msr;
 771
 772   Msr = AsmReadMsr64 (MSR_P6_SYSENTER_CS_MSR);
 773   AsmWriteMsr64 (MSR_P6_SYSENTER_CS_MSR, Msr);
 774   @endcode
 775 **/
 776 #define MSR_P6_SYSENTER_CS_MSR                   0x00000174
 777
 778
 779 /**
 780   Stack pointer for CPL 0 stack.
 781
 782   @param  ECX  MSR_P6_SYSENTER_ESP_MSR (0x00000175)
 783   @param  EAX  Lower 32-bits of MSR value.
 784   @param  EDX  Upper 32-bits of MSR value.
 785
 786   <b>Example usage</b>
 787   @code
 788   UINT64  Msr;
 789
 790   Msr = AsmReadMsr64 (MSR_P6_SYSENTER_ESP_MSR);
 791   AsmWriteMsr64 (MSR_P6_SYSENTER_ESP_MSR, Msr);
 792   @endcode
 793 **/
 794 #define MSR_P6_SYSENTER_ESP_MSR                  0x00000175
 795
 796
 797 /**
 798   CPL 0 code entry point.
 799
 800   @param  ECX  MSR_P6_SYSENTER_EIP_MSR (0x00000176)
 801   @param  EAX  Lower 32-bits of MSR value.
 802   @param  EDX  Upper 32-bits of MSR value.
 803
 804   <b>Example usage</b>
 805   @code
 806   UINT64  Msr;
 807
 808   Msr = AsmReadMsr64 (MSR_P6_SYSENTER_EIP_MSR);
 809   AsmWriteMsr64 (MSR_P6_SYSENTER_EIP_MSR, Msr);
 810   @endcode
 811 **/
 812 #define MSR_P6_SYSENTER_EIP_MSR                  0x00000176
 813
 814
 815 /**
 816
 817
 818   @param  ECX  MSR_P6_MCG_CAP (0x00000179)
 819   @param  EAX  Lower 32-bits of MSR value.
 820   @param  EDX  Upper 32-bits of MSR value.
 821
 822   <b>Example usage</b>
 823   @code
 824   UINT64  Msr;
 825
 826   Msr = AsmReadMsr64 (MSR_P6_MCG_CAP);
 827   AsmWriteMsr64 (MSR_P6_MCG_CAP, Msr);
 828   @endcode
 829 **/
 830 #define MSR_P6_MCG_CAP                           0x00000179
 831
 832
 833 /**
 834
 835
 836   @param  ECX  MSR_P6_MCG_STATUS (0x0000017A)
 837   @param  EAX  Lower 32-bits of MSR value.
 838   @param  EDX  Upper 32-bits of MSR value.
 839
 840   <b>Example usage</b>
 841   @code
 842   UINT64  Msr;
 843
 844   Msr = AsmReadMsr64 (MSR_P6_MCG_STATUS);
 845   AsmWriteMsr64 (MSR_P6_MCG_STATUS, Msr);
 846   @endcode
 847 **/
 848 #define MSR_P6_MCG_STATUS                        0x0000017A
 849
 850
 851 /**
 852
 853
 854   @param  ECX  MSR_P6_MCG_CTL (0x0000017B)
 855   @param  EAX  Lower 32-bits of MSR value.
 856   @param  EDX  Upper 32-bits of MSR value.
 857
 858   <b>Example usage</b>
 859   @code
 860   UINT64  Msr;
 861
 862   Msr = AsmReadMsr64 (MSR_P6_MCG_CTL);
 863   AsmWriteMsr64 (MSR_P6_MCG_CTL, Msr);
 864   @endcode
 865 **/
 866 #define MSR_P6_MCG_CTL                           0x0000017B
 867
 868
 869 /**
 870
 871
 872   @param  ECX  MSR_P6_PERFEVTSELn
 873   @param  EAX  Lower 32-bits of MSR value.
 874                Described by the type MSR_P6_PERFEVTSEL_REGISTER.
 875   @param  EDX  Upper 32-bits of MSR value.
 876                Described by the type MSR_P6_PERFEVTSEL_REGISTER.
 877
 878   <b>Example usage</b>
 879   @code
 880   MSR_P6_PERFEVTSEL_REGISTER  Msr;
 881
 882   Msr.Uint64 = AsmReadMsr64 (MSR_P6_PERFEVTSEL0);
 883   AsmWriteMsr64 (MSR_P6_PERFEVTSEL0, Msr.Uint64);
 884   @endcode
 885   @{
 886 **/
 887 #define MSR_P6_PERFEVTSEL0                       0x00000186
 888 #define MSR_P6_PERFEVTSEL1                       0x00000187
 889 /// @}
 890
 891 /**
 892   MSR information returned for MSR indexes #MSR_P6_PERFEVTSEL0 and
 893   #MSR_P6_PERFEVTSEL1.
 894 **/
 895 typedef union {
 896   ///
 897   /// Individual bit fields
 898   ///
 899   struct {
 900     ///
 901     /// [Bits 7:0] Event Select Refer to Performance Counter section for a
 902     /// list of event encodings.
 903     ///
 904     UINT32  EventSelect:8;
 905     ///
 906     /// [Bits 15:8] UMASK (Unit Mask) Unit mask register set to 0 to enable
 907     /// all count options.
 908     ///
 909     UINT32  UMASK:8;
 910     ///
 911     /// [Bit 16] USER Controls the counting of events at Privilege levels of
 912     /// 1, 2, and 3.
 913     ///
 914     UINT32  USR:1;
 915     ///
 916     /// [Bit 17] OS Controls the counting of events at Privilege level of 0.
 917     ///
 918     UINT32  OS:1;
 919     ///
 920     /// [Bit 18] E Occurrence/Duration Mode Select 1 = Occurrence 0 = Duration.
 921     ///
 922     UINT32  E:1;
 923     ///
 924     /// [Bit 19] PC Enabled the signaling of performance counter overflow via
 925     /// BP0 pin.
 926     ///
 927     UINT32  PC:1;
 928     ///
 929     /// [Bit 20] INT Enables the signaling of counter overflow via input to
 930     /// APIC 1 = Enable 0 = Disable.
 931     ///
 932     UINT32  INT:1;
 933     UINT32  Reserved1:1;
 934     ///
 935     /// [Bit 22] ENABLE Enables the counting of performance events in both
 936     /// counters 1 = Enable 0 = Disable.
 937     ///
 938     UINT32  EN:1;
 939     ///
 940     /// [Bit 23] INV Inverts the result of the CMASK condition 1 = Inverted 0
 941     /// = Non-Inverted.
 942     ///
 943     UINT32  INV:1;
 944     ///
 945     /// [Bits 31:24] CMASK (Counter Mask).
 946     ///
 947     UINT32  CMASK:8;
 948     UINT32  Reserved2:32;
 949   } Bits;
 950   ///
 951   /// All bit fields as a 32-bit value
 952   ///
 953   UINT32  Uint32;
 954   ///
 955   /// All bit fields as a 64-bit value
 956   ///
 957   UINT64  Uint64;
 958 } MSR_P6_PERFEVTSEL_REGISTER;
 959
 960
 961 /**
 962
 963
 964   @param  ECX  MSR_P6_DEBUGCTLMSR (0x000001D9)
 965   @param  EAX  Lower 32-bits of MSR value.
 966                Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.
 967   @param  EDX  Upper 32-bits of MSR value.
 968                Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.
 969
 970   <b>Example usage</b>
 971   @code
 972   MSR_P6_DEBUGCTLMSR_REGISTER  Msr;
 973
 974   Msr.Uint64 = AsmReadMsr64 (MSR_P6_DEBUGCTLMSR);
 975   AsmWriteMsr64 (MSR_P6_DEBUGCTLMSR, Msr.Uint64);
 976   @endcode
 977 **/
 978 #define MSR_P6_DEBUGCTLMSR                       0x000001D9
 979
 980 /**
 981   MSR information returned for MSR index #MSR_P6_DEBUGCTLMSR
 982 **/
 983 typedef union {
 984   ///
 985   /// Individual bit fields
 986   ///
 987   struct {
 988     ///
 989     /// [Bit 0] Enable/Disable Last Branch Records.
 990     ///
 991     UINT32  LBR:1;
 992     ///
 993     /// [Bit 1] Branch Trap Flag.
 994     ///
 995     UINT32  BTF:1;
 996     ///
 997     /// [Bit 2] Performance Monitoring/Break Point Pins.
 998     ///
 999     UINT32  PB0:1;
1000     ///
1001     /// [Bit 3] Performance Monitoring/Break Point Pins.
1002     ///
1003     UINT32  PB1:1;
1004     ///
1005     /// [Bit 4] Performance Monitoring/Break Point Pins.
1006     ///
1007     UINT32  PB2:1;
1008     ///
1009     /// [Bit 5] Performance Monitoring/Break Point Pins.
1010     ///
1011     UINT32  PB3:1;
1012     ///
1013     /// [Bit 6] Enable/Disable Execution Trace Messages.
1014     ///
1015     UINT32  TR:1;
1016     UINT32  Reserved1:25;
1017     UINT32  Reserved2:32;
1018   } Bits;
1019   ///
1020   /// All bit fields as a 32-bit value
1021   ///
1022   UINT32  Uint32;
1023   ///
1024   /// All bit fields as a 64-bit value
1025   ///
1026   UINT64  Uint64;
1027 } MSR_P6_DEBUGCTLMSR_REGISTER;
1028
1029
1030 /**
1031
1032
1033   @param  ECX  MSR_P6_LASTBRANCHFROMIP (0x000001DB)
1034   @param  EAX  Lower 32-bits of MSR value.
1035   @param  EDX  Upper 32-bits of MSR value.
1036
1037   <b>Example usage</b>
1038   @code
1039   UINT64  Msr;
1040
1041   Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHFROMIP);
1042   AsmWriteMsr64 (MSR_P6_LASTBRANCHFROMIP, Msr);
1043   @endcode
1044 **/
1045 #define MSR_P6_LASTBRANCHFROMIP                  0x000001DB
1046
1047
1048 /**
1049
1050
1051   @param  ECX  MSR_P6_LASTBRANCHTOIP (0x000001DC)
1052   @param  EAX  Lower 32-bits of MSR value.
1053   @param  EDX  Upper 32-bits of MSR value.
1054
1055   <b>Example usage</b>
1056   @code
1057   UINT64  Msr;
1058
1059   Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHTOIP);
1060   AsmWriteMsr64 (MSR_P6_LASTBRANCHTOIP, Msr);
1061   @endcode
1062 **/
1063 #define MSR_P6_LASTBRANCHTOIP                    0x000001DC
1064
1065
1066 /**
1067
1068
1069   @param  ECX  MSR_P6_LASTINTFROMIP (0x000001DD)
1070   @param  EAX  Lower 32-bits of MSR value.
1071   @param  EDX  Upper 32-bits of MSR value.
1072
1073   <b>Example usage</b>
1074   @code
1075   UINT64  Msr;
1076
1077   Msr = AsmReadMsr64 (MSR_P6_LASTINTFROMIP);
1078   AsmWriteMsr64 (MSR_P6_LASTINTFROMIP, Msr);
1079   @endcode
1080 **/
1081 #define MSR_P6_LASTINTFROMIP                     0x000001DD
1082
1083
1084 /**
1085
1086
1087   @param  ECX  MSR_P6_LASTINTTOIP (0x000001DE)
1088   @param  EAX  Lower 32-bits of MSR value.
1089   @param  EDX  Upper 32-bits of MSR value.
1090
1091   <b>Example usage</b>
1092   @code
1093   UINT64  Msr;
1094
1095   Msr = AsmReadMsr64 (MSR_P6_LASTINTTOIP);
1096   AsmWriteMsr64 (MSR_P6_LASTINTTOIP, Msr);
1097   @endcode
1098 **/
1099 #define MSR_P6_LASTINTTOIP                       0x000001DE
1100
1101
1102 /**
1103
1104
1105   @param  ECX  MSR_P6_ROB_CR_BKUPTMPDR6 (0x000001E0)
1106   @param  EAX  Lower 32-bits of MSR value.
1107                Described by the type MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER.
1108   @param  EDX  Upper 32-bits of MSR value.
1109                Described by the type MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER.
1110
1111   <b>Example usage</b>
1112   @code
1113   MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER  Msr;
1114
1115   Msr.Uint64 = AsmReadMsr64 (MSR_P6_ROB_CR_BKUPTMPDR6);
1116   AsmWriteMsr64 (MSR_P6_ROB_CR_BKUPTMPDR6, Msr.Uint64);
1117   @endcode
1118 **/
1119 #define MSR_P6_ROB_CR_BKUPTMPDR6                 0x000001E0
1120
1121 /**
1122   MSR information returned for MSR index #MSR_P6_ROB_CR_BKUPTMPDR6
1123 **/
1124 typedef union {
1125   ///
1126   /// Individual bit fields
1127   ///
1128   struct {
1129     UINT32  Reserved1:2;
1130     ///
1131     /// [Bit 2] Fast Strings Enable bit. Default is enabled.
1132     ///
1133     UINT32  FastStrings:1;
1134     UINT32  Reserved2:29;
1135     UINT32  Reserved3:32;
1136   } Bits;
1137   ///
1138   /// All bit fields as a 32-bit value
1139   ///
1140   UINT32  Uint32;
1141   ///
1142   /// All bit fields as a 64-bit value
1143   ///
1144   UINT64  Uint64;
1145 } MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER;
1146
1147
1148 /**
1149
1150
1151   @param  ECX  MSR_P6_MTRRPHYSBASEn
1152   @param  EAX  Lower 32-bits of MSR value.
1153   @param  EDX  Upper 32-bits of MSR value.
1154
1155   <b>Example usage</b>
1156   @code
1157   UINT64  Msr;
1158
1159   Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0);
1160   AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr);
1161   @endcode
1162   @{
1163 **/
1164 #define MSR_P6_MTRRPHYSBASE0                     0x00000200
1165 #define MSR_P6_MTRRPHYSBASE1                     0x00000202
1166 #define MSR_P6_MTRRPHYSBASE2                     0x00000204
1167 #define MSR_P6_MTRRPHYSBASE3                     0x00000206
1168 #define MSR_P6_MTRRPHYSBASE4                     0x00000208
1169 #define MSR_P6_MTRRPHYSBASE5                     0x0000020A
1170 #define MSR_P6_MTRRPHYSBASE6                     0x0000020C
1171 #define MSR_P6_MTRRPHYSBASE7                     0x0000020E
1172 /// @}
1173
1174
1175 /**
1176
1177
1178   @param  ECX  MSR_P6_MTRRPHYSMASKn
1179   @param  EAX  Lower 32-bits of MSR value.
1180   @param  EDX  Upper 32-bits of MSR value.
1181
1182   <b>Example usage</b>
1183   @code
1184   UINT64  Msr;
1185
1186   Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0);
1187   AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr);
1188   @endcode
1189   @{
1190 **/
1191 #define MSR_P6_MTRRPHYSMASK0                     0x00000201
1192 #define MSR_P6_MTRRPHYSMASK1                     0x00000203
1193 #define MSR_P6_MTRRPHYSMASK2                     0x00000205
1194 #define MSR_P6_MTRRPHYSMASK3                     0x00000207
1195 #define MSR_P6_MTRRPHYSMASK4                     0x00000209
1196 #define MSR_P6_MTRRPHYSMASK5                     0x0000020B
1197 #define MSR_P6_MTRRPHYSMASK6                     0x0000020D
1198 #define MSR_P6_MTRRPHYSMASK7                     0x0000020F
1199 /// @}
1200
1201
1202 /**
1203
1204
1205   @param  ECX  MSR_P6_MTRRFIX64K_00000 (0x00000250)
1206   @param  EAX  Lower 32-bits of MSR value.
1207   @param  EDX  Upper 32-bits of MSR value.
1208
1209   <b>Example usage</b>
1210   @code
1211   UINT64  Msr;
1212
1213   Msr = AsmReadMsr64 (MSR_P6_MTRRFIX64K_00000);
1214   AsmWriteMsr64 (MSR_P6_MTRRFIX64K_00000, Msr);
1215   @endcode
1216 **/
1217 #define MSR_P6_MTRRFIX64K_00000                  0x00000250
1218
1219
1220 /**
1221
1222
1223   @param  ECX  MSR_P6_MTRRFIX16K_80000 (0x00000258)
1224   @param  EAX  Lower 32-bits of MSR value.
1225   @param  EDX  Upper 32-bits of MSR value.
1226
1227   <b>Example usage</b>
1228   @code
1229   UINT64  Msr;
1230
1231   Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_80000);
1232   AsmWriteMsr64 (MSR_P6_MTRRFIX16K_80000, Msr);
1233   @endcode
1234 **/
1235 #define MSR_P6_MTRRFIX16K_80000                  0x00000258
1236
1237
1238 /**
1239
1240
1241   @param  ECX  MSR_P6_MTRRFIX16K_A0000 (0x00000259)
1242   @param  EAX  Lower 32-bits of MSR value.
1243   @param  EDX  Upper 32-bits of MSR value.
1244
1245   <b>Example usage</b>
1246   @code
1247   UINT64  Msr;
1248
1249   Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_A0000);
1250   AsmWriteMsr64 (MSR_P6_MTRRFIX16K_A0000, Msr);
1251   @endcode
1252 **/
1253 #define MSR_P6_MTRRFIX16K_A0000                  0x00000259
1254
1255
1256 /**
1257
1258
1259   @param  ECX  MSR_P6_MTRRFIX4K_C0000 (0x00000268)
1260   @param  EAX  Lower 32-bits of MSR value.
1261   @param  EDX  Upper 32-bits of MSR value.
1262
1263   <b>Example usage</b>
1264   @code
1265   UINT64  Msr;
1266
1267   Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C0000);
1268   AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C0000, Msr);
1269   @endcode
1270 **/
1271 #define MSR_P6_MTRRFIX4K_C0000                   0x00000268
1272
1273
1274 /**
1275
1276
1277   @param  ECX  MSR_P6_MTRRFIX4K_C8000 (0x00000269)
1278   @param  EAX  Lower 32-bits of MSR value.
1279   @param  EDX  Upper 32-bits of MSR value.
1280
1281   <b>Example usage</b>
1282   @code
1283   UINT64  Msr;
1284
1285   Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C8000);
1286   AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C8000, Msr);
1287   @endcode
1288 **/
1289 #define MSR_P6_MTRRFIX4K_C8000                   0x00000269
1290
1291
1292 /**
1293
1294
1295   @param  ECX  MSR_P6_MTRRFIX4K_D0000 (0x0000026A)
1296   @param  EAX  Lower 32-bits of MSR value.
1297   @param  EDX  Upper 32-bits of MSR value.
1298
1299   <b>Example usage</b>
1300   @code
1301   UINT64  Msr;
1302
1303   Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D0000);
1304   AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D0000, Msr);
1305   @endcode
1306 **/
1307 #define MSR_P6_MTRRFIX4K_D0000                   0x0000026A
1308
1309
1310 /**
1311
1312
1313   @param  ECX  MSR_P6_MTRRFIX4K_D8000 (0x0000026B)
1314   @param  EAX  Lower 32-bits of MSR value.
1315   @param  EDX  Upper 32-bits of MSR value.
1316
1317   <b>Example usage</b>
1318   @code
1319   UINT64  Msr;
1320
1321   Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D8000);
1322   AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D8000, Msr);
1323   @endcode
1324 **/
1325 #define MSR_P6_MTRRFIX4K_D8000                   0x0000026B
1326
1327
1328 /**
1329
1330
1331   @param  ECX  MSR_P6_MTRRFIX4K_E0000 (0x0000026C)
1332   @param  EAX  Lower 32-bits of MSR value.
1333   @param  EDX  Upper 32-bits of MSR value.
1334
1335   <b>Example usage</b>
1336   @code
1337   UINT64  Msr;
1338
1339   Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E0000);
1340   AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E0000, Msr);
1341   @endcode
1342 **/
1343 #define MSR_P6_MTRRFIX4K_E0000                   0x0000026C
1344
1345
1346 /**
1347
1348
1349   @param  ECX  MSR_P6_MTRRFIX4K_E8000 (0x0000026D)
1350   @param  EAX  Lower 32-bits of MSR value.
1351   @param  EDX  Upper 32-bits of MSR value.
1352
1353   <b>Example usage</b>
1354   @code
1355   UINT64  Msr;
1356
1357   Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E8000);
1358   AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E8000, Msr);
1359   @endcode
1360 **/
1361 #define MSR_P6_MTRRFIX4K_E8000                   0x0000026D
1362
1363
1364 /**
1365
1366
1367   @param  ECX  MSR_P6_MTRRFIX4K_F0000 (0x0000026E)
1368   @param  EAX  Lower 32-bits of MSR value.
1369   @param  EDX  Upper 32-bits of MSR value.
1370
1371   <b>Example usage</b>
1372   @code
1373   UINT64  Msr;
1374
1375   Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F0000);
1376   AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F0000, Msr);
1377   @endcode
1378 **/
1379 #define MSR_P6_MTRRFIX4K_F0000                   0x0000026E
1380
1381
1382 /**
1383
1384
1385   @param  ECX  MSR_P6_MTRRFIX4K_F8000 (0x0000026F)
1386   @param  EAX  Lower 32-bits of MSR value.
1387   @param  EDX  Upper 32-bits of MSR value.
1388
1389   <b>Example usage</b>
1390   @code
1391   UINT64  Msr;
1392
1393   Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F8000);
1394   AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F8000, Msr);
1395   @endcode
1396 **/
1397 #define MSR_P6_MTRRFIX4K_F8000                   0x0000026F
1398
1399
1400 /**
1401
1402
1403   @param  ECX  MSR_P6_MTRRDEFTYPE (0x000002FF)
1404   @param  EAX  Lower 32-bits of MSR value.
1405                Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.
1406   @param  EDX  Upper 32-bits of MSR value.
1407                Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.
1408
1409   <b>Example usage</b>
1410   @code
1411   MSR_P6_MTRRDEFTYPE_REGISTER  Msr;
1412
1413   Msr.Uint64 = AsmReadMsr64 (MSR_P6_MTRRDEFTYPE);
1414   AsmWriteMsr64 (MSR_P6_MTRRDEFTYPE, Msr.Uint64);
1415   @endcode
1416 **/
1417 #define MSR_P6_MTRRDEFTYPE                       0x000002FF
1418
1419 /**
1420   MSR information returned for MSR index #MSR_P6_MTRRDEFTYPE
1421 **/
1422 typedef union {
1423   ///
1424   /// Individual bit fields
1425   ///
1426   struct {
1427     ///
1428     /// [Bits 2:0] Default memory type.
1429     ///
1430     UINT32  Type:3;
1431     UINT32  Reserved1:7;
1432     ///
1433     /// [Bit 10] Fixed MTRR enable.
1434     ///
1435     UINT32  FE:1;
1436     ///
1437     /// [Bit 11] MTRR Enable.
1438     ///
1439     UINT32  E:1;
1440     UINT32  Reserved2:20;
1441     UINT32  Reserved3:32;
1442   } Bits;
1443   ///
1444   /// All bit fields as a 32-bit value
1445   ///
1446   UINT32  Uint32;
1447   ///
1448   /// All bit fields as a 64-bit value
1449   ///
1450   UINT64  Uint64;
1451 } MSR_P6_MTRRDEFTYPE_REGISTER;
1452
1453
1454 /**
1455
1456
1457   @param  ECX  MSR_P6_MC0_CTL (0x00000400)
1458   @param  EAX  Lower 32-bits of MSR value.
1459   @param  EDX  Upper 32-bits of MSR value.
1460
1461   <b>Example usage</b>
1462   @code
1463   UINT64  Msr;
1464
1465   Msr = AsmReadMsr64 (MSR_P6_MC0_CTL);
1466   AsmWriteMsr64 (MSR_P6_MC0_CTL, Msr);
1467   @endcode
1468   @{
1469 **/
1470 #define MSR_P6_MC0_CTL                           0x00000400
1471 #define MSR_P6_MC1_CTL                           0x00000404
1472 #define MSR_P6_MC2_CTL                           0x00000408
1473 #define MSR_P6_MC3_CTL                           0x00000410
1474 #define MSR_P6_MC4_CTL                           0x0000040C
1475 /// @}
1476
1477
1478 /**
1479
1480   Bit definitions for MSR_P6_MC4_STATUS are the same as MSR_P6_MC0_STATUS,
1481   except bits 0, 4, 57, and 61 are hardcoded to 1.
1482
1483   @param  ECX  MSR_P6_MCn_STATUS
1484   @param  EAX  Lower 32-bits of MSR value.
1485                Described by the type MSR_P6_MC_STATUS_REGISTER.
1486   @param  EDX  Upper 32-bits of MSR value.
1487                Described by the type MSR_P6_MC_STATUS_REGISTER.
1488
1489   <b>Example usage</b>
1490   @code
1491   MSR_P6_MC_STATUS_REGISTER  Msr;
1492
1493   Msr.Uint64 = AsmReadMsr64 (MSR_P6_MC0_STATUS);
1494   AsmWriteMsr64 (MSR_P6_MC0_STATUS, Msr.Uint64);
1495   @endcode
1496   @{
1497 **/
1498 #define MSR_P6_MC0_STATUS                        0x00000401
1499 #define MSR_P6_MC1_STATUS                        0x00000405
1500 #define MSR_P6_MC2_STATUS                        0x00000409
1501 #define MSR_P6_MC3_STATUS                        0x00000411
1502 #define MSR_P6_MC4_STATUS                        0x0000040D
1503 /// @}
1504
1505 /**
1506   MSR information returned for MSR index #MSR_P6_MC0_STATUS to
1507   #MSR_P6_MC4_STATUS
1508 **/
1509 typedef union {
1510   ///
1511   /// Individual bit fields
1512   ///
1513   struct {
1514     ///
1515     /// [Bits 15:0] MC_STATUS_MCACOD.
1516     ///
1517     UINT32  MC_STATUS_MCACOD:16;
1518     ///
1519     /// [Bits 31:16] MC_STATUS_MSCOD.
1520     ///
1521     UINT32  MC_STATUS_MSCOD:16;
1522     UINT32  Reserved:25;
1523     ///
1524     /// [Bit 57] MC_STATUS_DAM.
1525     ///
1526     UINT32  MC_STATUS_DAM:1;
1527     ///
1528     /// [Bit 58] MC_STATUS_ADDRV.
1529     ///
1530     UINT32  MC_STATUS_ADDRV:1;
1531     ///
1532     /// [Bit 59] MC_STATUS_MISCV.
1533     ///
1534     UINT32  MC_STATUS_MISCV:1;
1535     ///
1536     /// [Bit 60] MC_STATUS_EN. (Note: For MC0_STATUS only, this bit is
1537     /// hardcoded to 1.).
1538     ///
1539     UINT32  MC_STATUS_EN:1;
1540     ///
1541     /// [Bit 61] MC_STATUS_UC.
1542     ///
1543     UINT32  MC_STATUS_UC:1;
1544     ///
1545     /// [Bit 62] MC_STATUS_O.
1546     ///
1547     UINT32  MC_STATUS_O:1;
1548     ///
1549     /// [Bit 63] MC_STATUS_V.
1550     ///
1551     UINT32  MC_STATUS_V:1;
1552   } Bits;
1553   ///
1554   /// All bit fields as a 64-bit value
1555   ///
1556   UINT64  Uint64;
1557 } MSR_P6_MC_STATUS_REGISTER;
1558
1559
1560 /**
1561
1562   MSR_P6_MC4_ADDR is defined in MCA architecture but not implemented in P6 Family processors.
1563
1564   @param  ECX  MSR_P6_MC0_ADDR (0x00000402)
1565   @param  EAX  Lower 32-bits of MSR value.
1566   @param  EDX  Upper 32-bits of MSR value.
1567
1568   <b>Example usage</b>
1569   @code
1570   UINT64  Msr;
1571
1572   Msr = AsmReadMsr64 (MSR_P6_MC0_ADDR);
1573   AsmWriteMsr64 (MSR_P6_MC0_ADDR, Msr);
1574   @endcode
1575   @{
1576 **/
1577 #define MSR_P6_MC0_ADDR                          0x00000402
1578 #define MSR_P6_MC1_ADDR                          0x00000406
1579 #define MSR_P6_MC2_ADDR                          0x0000040A
1580 #define MSR_P6_MC3_ADDR                          0x00000412
1581 #define MSR_P6_MC4_ADDR                          0x0000040E
1582 /// @}
1583
1584
1585 /**
1586   Defined in MCA architecture but not implemented in the P6 family processors.
1587
1588   @param  ECX  MSR_P6_MC0_MISC (0x00000403)
1589   @param  EAX  Lower 32-bits of MSR value.
1590   @param  EDX  Upper 32-bits of MSR value.
1591
1592   <b>Example usage</b>
1593   @code
1594   UINT64  Msr;
1595
1596   Msr = AsmReadMsr64 (MSR_P6_MC0_MISC);
1597   AsmWriteMsr64 (MSR_P6_MC0_MISC, Msr);
1598   @endcode
1599   @{
1600 **/
1601 #define MSR_P6_MC0_MISC                          0x00000403
1602 #define MSR_P6_MC1_MISC                          0x00000407
1603 #define MSR_P6_MC2_MISC                          0x0000040B
1604 #define MSR_P6_MC3_MISC                          0x00000413
1605 #define MSR_P6_MC4_MISC                          0x0000040F
1606 /// @}
1607
1608 #endif