2 MSR Definitions for Pentium M Processors.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.20.
24 #ifndef __PENTIUM_M_MSR_H__
25 #define __PENTIUM_M_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 See Section 35.22, "MSRs in Pentium Processors.".
32 @param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)
33 @param EAX Lower 32-bits of MSR value.
34 @param EDX Upper 32-bits of MSR value.
40 Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);
41 AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);
43 @note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
45 #define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000
49 See Section 35.22, "MSRs in Pentium Processors.".
51 @param ECX MSR_PENTIUM_M_P5_MC_TYPE (0x00000001)
52 @param EAX Lower 32-bits of MSR value.
53 @param EDX Upper 32-bits of MSR value.
59 Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);
60 AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);
62 @note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
64 #define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001
68 Processor Hard Power-On Configuration (R/W) Enables and disables processor
69 features. (R) Indicates current processor configuration.
71 @param ECX MSR_PENTIUM_M_EBL_CR_POWERON (0x0000002A)
72 @param EAX Lower 32-bits of MSR value.
73 Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
74 @param EDX Upper 32-bits of MSR value.
75 Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
79 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER Msr;
81 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);
82 AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);
84 @note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
86 #define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A
89 MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON
93 /// Individual bit fields
98 /// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the
99 /// Pentium M processor.
101 UINT32 DataErrorCheckingEnable
:1;
103 /// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on
104 /// the Pentium M processor.
106 UINT32 ResponseErrorCheckingEnable
:1;
108 /// [Bit 3] MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium
111 UINT32 MCERR_DriveEnable
:1;
113 /// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium
116 UINT32 AddressParityEnable
:1;
119 /// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on
120 /// the Pentium M processor.
122 UINT32 BINIT_DriverEnable
:1;
124 /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
126 UINT32 OutputTriStateEnable
:1;
128 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
130 UINT32 ExecuteBIST
:1;
132 /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
133 /// Always 0 on the Pentium M processor.
135 UINT32 MCERR_ObservationEnabled
:1;
138 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
139 /// Always 0 on the Pentium M processor.
141 UINT32 BINIT_ObservationEnabled
:1;
144 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes
145 /// Always 0 on the Pentium M processor.
147 UINT32 ResetVector
:1;
150 /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M
153 UINT32 APICClusterID
:2;
155 /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always
156 /// 0 on the Pentium M processor.
158 UINT32 SystemBusFrequency
:1;
161 /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium
164 UINT32 SymmetricArbitrationID
:2;
166 /// [Bits 26:22] Clock Frequency Ratio (R/O).
168 UINT32 ClockFrequencyRatio
:5;
173 /// All bit fields as a 32-bit value
177 /// All bit fields as a 64-bit value
180 } MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
;
184 Last Branch Record n (R/W) One of 8 last branch record registers on the last
185 branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold
186 the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section
187 17.13, "Last Branch, Interrupt, and Exception Recording (Pentium M
190 @param ECX MSR_PENTIUM_M_LASTBRANCH_n
191 @param EAX Lower 32-bits of MSR value.
192 @param EDX Upper 32-bits of MSR value.
198 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);
199 AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);
201 @note MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
202 MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
203 MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
204 MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
205 MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.
206 MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.
207 MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.
208 MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.
211 #define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040
212 #define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041
213 #define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042
214 #define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043
215 #define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044
216 #define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045
217 #define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046
218 #define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047
225 @param ECX MSR_PENTIUM_M_BBL_CR_CTL (0x00000119)
226 @param EAX Lower 32-bits of MSR value.
227 @param EDX Upper 32-bits of MSR value.
233 Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL);
234 AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr);
236 @note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.
238 #define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119
244 @param ECX MSR_PENTIUM_M_BBL_CR_CTL3 (0x0000011E)
245 @param EAX Lower 32-bits of MSR value.
246 Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
247 @param EDX Upper 32-bits of MSR value.
248 Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
252 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER Msr;
254 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3);
255 AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64);
257 @note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
259 #define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E
262 MSR information returned for MSR index #MSR_PENTIUM_M_BBL_CR_CTL3
266 /// Individual bit fields
270 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
271 /// Indicates if the L2 is hardware-disabled.
273 UINT32 L2HardwareEnabled
:1;
276 /// [Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the
277 /// cache data bus. ECC is always generated on write cycles. 1. = Disabled
278 /// (default) 2. = Enabled For the Pentium M processor, ECC checking on
279 /// the cache data bus is always enabled.
281 UINT32 ECCCheckEnable
:1;
284 /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
285 /// Disabled (default) Until this bit is set the processor will not
286 /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
291 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
293 UINT32 L2NotPresent
:1;
298 /// All bit fields as a 32-bit value
302 /// All bit fields as a 64-bit value
305 } MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER
;
311 @param ECX MSR_PENTIUM_M_THERM2_CTL (0x0000019D)
312 @param EAX Lower 32-bits of MSR value.
313 Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
314 @param EDX Upper 32-bits of MSR value.
315 Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
319 MSR_PENTIUM_M_THERM2_CTL_REGISTER Msr;
321 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL);
322 AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64);
324 @note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
326 #define MSR_PENTIUM_M_THERM2_CTL 0x0000019D
329 MSR information returned for MSR index #MSR_PENTIUM_M_THERM2_CTL
333 /// Individual bit fields
338 /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
339 /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
340 /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
341 /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
342 /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
349 /// All bit fields as a 32-bit value
353 /// All bit fields as a 64-bit value
356 } MSR_PENTIUM_M_THERM2_CTL_REGISTER
;
360 Enable Miscellaneous Processor Features (R/W) Allows a variety of processor
361 functions to be enabled and disabled.
363 @param ECX MSR_PENTIUM_M_IA32_MISC_ENABLE (0x000001A0)
364 @param EAX Lower 32-bits of MSR value.
365 Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
366 @param EDX Upper 32-bits of MSR value.
367 Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
371 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER Msr;
373 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE);
374 AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64);
376 @note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
378 #define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0
381 MSR information returned for MSR index #MSR_PENTIUM_M_IA32_MISC_ENABLE
385 /// Individual bit fields
390 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting
391 /// this bit enables the thermal control circuit (TCC) portion of the
392 /// Intel Thermal Monitor feature. This allows processor clocks to be
393 /// automatically modulated based on the processor's thermal sensor
394 /// operation. 0 = Disabled (default). The automatic thermal control
395 /// circuit enable bit determines if the thermal control circuit (TCC)
396 /// will be activated when the processor's internal thermal sensor
397 /// determines the processor is about to exceed its maximum operating
398 /// temperature. When the TCC is activated and TM1 is enabled, the
399 /// processors clocks will be forced to a 50% duty cycle. BIOS must enable
400 /// this feature. The bit should not be confused with the on-demand
401 /// thermal control circuit enable bit.
403 UINT32 AutomaticThermalControlCircuit
:1;
406 /// [Bit 7] Performance Monitoring Available (R) 1 = Performance
407 /// monitoring enabled 0 = Performance monitoring disabled.
409 UINT32 PerformanceMonitoring
:1;
412 /// [Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the
413 /// processor to indicate a pending break event within the processor 0 =
414 /// Indicates compatible FERR# signaling behavior This bit must be set to
415 /// 1 to support XAPIC interrupt model usage.
416 /// **Branch Trace Storage Unavailable (RO)** 1 = Processor doesn't
417 /// support branch trace storage (BTS) 0 = BTS is supported
421 /// [Bit 11] Branch Trace Storage Unavailable (RO)
422 /// 1 = Processor doesn't support branch trace storage (BTS)
423 /// 0 = BTS is supported
427 /// [Bit 12] Processor Event Based Sampling Unavailable (RO) 1 =
428 /// Processor does not support processor event based sampling (PEBS); 0 =
429 /// PEBS is supported. The Pentium M processor does not support PEBS.
434 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 =
435 /// Enhanced Intel SpeedStep Technology enabled. On the Pentium M
436 /// processor, this bit may be configured to be read-only.
441 /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
442 /// disabled. xTPR messages are optional messages that allow the processor
443 /// to inform the chipset of its priority. The default is processor
446 UINT32 xTPR_Message_Disable
:1;
451 /// All bit fields as a 32-bit value
455 /// All bit fields as a 64-bit value
458 } MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER
;
462 Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points
463 to the MSR containing the most recent branch record. See also: -
464 MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.13, "Last Branch, Interrupt,
465 and Exception Recording (Pentium M Processors)".
467 @param ECX MSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9)
468 @param EAX Lower 32-bits of MSR value.
469 @param EDX Upper 32-bits of MSR value.
475 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS);
476 AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr);
478 @note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
480 #define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9
484 Debug Control (R/W) Controls how several debug features are used. Bit
485 definitions are discussed in the referenced section. See Section 17.13,
486 "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".
488 @param ECX MSR_PENTIUM_M_DEBUGCTLB (0x000001D9)
489 @param EAX Lower 32-bits of MSR value.
490 @param EDX Upper 32-bits of MSR value.
496 Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB);
497 AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr);
499 @note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.
501 #define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9
505 Last Exception Record To Linear IP (R) This area contains a pointer to the
506 target of the last branch instruction that the processor executed prior to
507 the last exception that was generated or the last interrupt that was
508 handled. See Section 17.13, "Last Branch, Interrupt, and Exception Recording
509 (Pentium M Processors)" and Section 17.14.2, "Last Branch and Last Exception
512 @param ECX MSR_PENTIUM_M_LER_TO_LIP (0x000001DD)
513 @param EAX Lower 32-bits of MSR value.
514 @param EDX Upper 32-bits of MSR value.
520 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP);
522 @note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
524 #define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD
528 Last Exception Record From Linear IP (R) Contains a pointer to the last
529 branch instruction that the processor executed prior to the last exception
530 that was generated or the last interrupt that was handled. See Section
531 17.13, "Last Branch, Interrupt, and Exception Recording (Pentium M
532 Processors)" and Section 17.14.2, "Last Branch and Last Exception MSRs.".
534 @param ECX MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)
535 @param EAX Lower 32-bits of MSR value.
536 @param EDX Upper 32-bits of MSR value.
542 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP);
544 @note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
546 #define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE
550 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
552 @param ECX MSR_PENTIUM_M_MC4_CTL (0x0000040C)
553 @param EAX Lower 32-bits of MSR value.
554 @param EDX Upper 32-bits of MSR value.
560 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL);
561 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr);
563 @note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.
565 #define MSR_PENTIUM_M_MC4_CTL 0x0000040C
569 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
571 @param ECX MSR_PENTIUM_M_MC4_STATUS (0x0000040D)
572 @param EAX Lower 32-bits of MSR value.
573 @param EDX Upper 32-bits of MSR value.
579 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS);
580 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr);
582 @note MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
584 #define MSR_PENTIUM_M_MC4_STATUS 0x0000040D
588 See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is
589 either not implemented or contains no address if the ADDRV flag in the
590 MSR_MC4_STATUS register is clear. When not implemented in the processor, all
591 reads and writes to this MSR will cause a general-protection exception.
593 @param ECX MSR_PENTIUM_M_MC4_ADDR (0x0000040E)
594 @param EAX Lower 32-bits of MSR value.
595 @param EDX Upper 32-bits of MSR value.
601 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR);
602 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr);
604 @note MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
606 #define MSR_PENTIUM_M_MC4_ADDR 0x0000040E
610 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
612 @param ECX MSR_PENTIUM_M_MC3_CTL (0x00000410)
613 @param EAX Lower 32-bits of MSR value.
614 @param EDX Upper 32-bits of MSR value.
620 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL);
621 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr);
623 @note MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM.
625 #define MSR_PENTIUM_M_MC3_CTL 0x00000410
629 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
631 @param ECX MSR_PENTIUM_M_MC3_STATUS (0x00000411)
632 @param EAX Lower 32-bits of MSR value.
633 @param EDX Upper 32-bits of MSR value.
639 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS);
640 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr);
642 @note MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
644 #define MSR_PENTIUM_M_MC3_STATUS 0x00000411
648 See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is
649 either not implemented or contains no address if the ADDRV flag in the
650 MSR_MC3_STATUS register is clear. When not implemented in the processor, all
651 reads and writes to this MSR will cause a general-protection exception.
653 @param ECX MSR_PENTIUM_M_MC3_ADDR (0x00000412)
654 @param EAX Lower 32-bits of MSR value.
655 @param EDX Upper 32-bits of MSR value.
661 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR);
662 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr);
664 @note MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
666 #define MSR_PENTIUM_M_MC3_ADDR 0x00000412