2 MSR Definitions for Pentium M Processors.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-18.
24 #ifndef __PENTIUM_M_MSR_H__
25 #define __PENTIUM_M_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 See Section 35.20, "MSRs in Pentium Processors.".
32 @param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)
33 @param EAX Lower 32-bits of MSR value.
34 @param EDX Upper 32-bits of MSR value.
40 Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);
41 AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);
44 #define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000
48 See Section 35.20, "MSRs in Pentium Processors.".
50 @param ECX MSR_PENTIUM_M_P5_MC_TYPE (0x00000001)
51 @param EAX Lower 32-bits of MSR value.
52 @param EDX Upper 32-bits of MSR value.
58 Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);
59 AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);
62 #define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001
66 Processor Hard Power-On Configuration (R/W) Enables and disables processor
67 features. (R) Indicates current processor configuration.
69 @param ECX MSR_PENTIUM_M_EBL_CR_POWERON (0x0000002A)
70 @param EAX Lower 32-bits of MSR value.
71 Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
72 @param EDX Upper 32-bits of MSR value.
73 Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
77 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER Msr;
79 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);
80 AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);
83 #define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A
86 MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON
90 /// Individual bit fields
95 /// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the
96 /// Pentium M processor.
98 UINT32 DataErrorCheckingEnable
:1;
100 /// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on
101 /// the Pentium M processor.
103 UINT32 ResponseErrorCheckingEnable
:1;
105 /// [Bit 3] MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium
108 UINT32 MCERR_DriveEnable
:1;
110 /// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium
113 UINT32 AddressParityEnable
:1;
116 /// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on
117 /// the Pentium M processor.
119 UINT32 BINIT_DriverEnable
:1;
121 /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
123 UINT32 OutputTriStateEnable
:1;
125 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
127 UINT32 ExecuteBIST
:1;
129 /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
130 /// Always 0 on the Pentium M processor.
132 UINT32 MCERR_ObservationEnabled
:1;
135 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
136 /// Always 0 on the Pentium M processor.
138 UINT32 BINIT_ObservationEnabled
:1;
141 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes
142 /// Always 0 on the Pentium M processor.
144 UINT32 ResetVector
:1;
147 /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M
150 UINT32 APICClusterID
:2;
152 /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always
153 /// 0 on the Pentium M processor.
155 UINT32 SystemBusFrequency
:1;
158 /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium
161 UINT32 SymmetricArbitrationID
:2;
163 /// [Bits 26:22] Clock Frequency Ratio (R/O).
165 UINT32 ClockFrequencyRatio
:5;
170 /// All bit fields as a 32-bit value
174 /// All bit fields as a 64-bit value
177 } MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
;
181 Last Branch Record n (R/W) One of 8 last branch record registers on the last
182 branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold
183 the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section
184 17.12, "Last Branch, Interrupt, and Exception Recording (Pentium M
187 @param ECX MSR_PENTIUM_M_LASTBRANCH_n
188 @param EAX Lower 32-bits of MSR value.
189 @param EDX Upper 32-bits of MSR value.
195 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);
196 AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);
200 #define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040
201 #define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041
202 #define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042
203 #define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043
204 #define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044
205 #define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045
206 #define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046
207 #define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047
214 @param ECX MSR_PENTIUM_M_BBL_CR_CTL (0x00000119)
215 @param EAX Lower 32-bits of MSR value.
216 @param EDX Upper 32-bits of MSR value.
222 Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL);
223 AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr);
226 #define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119
232 @param ECX MSR_PENTIUM_M_BBL_CR_CTL3 (0x0000011E)
233 @param EAX Lower 32-bits of MSR value.
234 Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
235 @param EDX Upper 32-bits of MSR value.
236 Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
240 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER Msr;
242 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3);
243 AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64);
246 #define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E
249 MSR information returned for MSR index #MSR_PENTIUM_M_BBL_CR_CTL3
253 /// Individual bit fields
257 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
258 /// Indicates if the L2 is hardware-disabled.
260 UINT32 L2HardwareEnabled
:1;
263 /// [Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the
264 /// cache data bus. ECC is always generated on write cycles. 1. = Disabled
265 /// (default) 2. = Enabled For the Pentium M processor, ECC checking on
266 /// the cache data bus is always enabled.
268 UINT32 ECCCheckEnable
:1;
271 /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
272 /// Disabled (default) Until this bit is set the processor will not
273 /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
278 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
280 UINT32 L2NotPresent
:1;
285 /// All bit fields as a 32-bit value
289 /// All bit fields as a 64-bit value
292 } MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER
;
298 @param ECX MSR_PENTIUM_M_THERM2_CTL (0x0000019D)
299 @param EAX Lower 32-bits of MSR value.
300 Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
301 @param EDX Upper 32-bits of MSR value.
302 Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
306 MSR_PENTIUM_M_THERM2_CTL_REGISTER Msr;
308 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL);
309 AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64);
312 #define MSR_PENTIUM_M_THERM2_CTL 0x0000019D
315 MSR information returned for MSR index #MSR_PENTIUM_M_THERM2_CTL
319 /// Individual bit fields
324 /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
325 /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
326 /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
327 /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
328 /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
335 /// All bit fields as a 32-bit value
339 /// All bit fields as a 64-bit value
342 } MSR_PENTIUM_M_THERM2_CTL_REGISTER
;
346 Enable Miscellaneous Processor Features (R/W) Allows a variety of processor
347 functions to be enabled and disabled.
349 @param ECX MSR_PENTIUM_M_IA32_MISC_ENABLE (0x000001A0)
350 @param EAX Lower 32-bits of MSR value.
351 Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
352 @param EDX Upper 32-bits of MSR value.
353 Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
357 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER Msr;
359 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE);
360 AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64);
363 #define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0
366 MSR information returned for MSR index #MSR_PENTIUM_M_IA32_MISC_ENABLE
370 /// Individual bit fields
375 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting
376 /// this bit enables the thermal control circuit (TCC) portion of the
377 /// Intel Thermal Monitor feature. This allows processor clocks to be
378 /// automatically modulated based on the processor's thermal sensor
379 /// operation. 0 = Disabled (default). The automatic thermal control
380 /// circuit enable bit determines if the thermal control circuit (TCC)
381 /// will be activated when the processor's internal thermal sensor
382 /// determines the processor is about to exceed its maximum operating
383 /// temperature. When the TCC is activated and TM1 is enabled, the
384 /// processors clocks will be forced to a 50% duty cycle. BIOS must enable
385 /// this feature. The bit should not be confused with the on-demand
386 /// thermal control circuit enable bit.
388 UINT32 AutomaticThermalControlCircuit
:1;
391 /// [Bit 7] Performance Monitoring Available (R) 1 = Performance
392 /// monitoring enabled 0 = Performance monitoring disabled.
394 UINT32 PerformanceMonitoring
:1;
397 /// [Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the
398 /// processor to indicate a pending break event within the processor 0 =
399 /// Indicates compatible FERR# signaling behavior This bit must be set to
400 /// 1 to support XAPIC interrupt model usage.
401 /// **Branch Trace Storage Unavailable (RO)** 1 = Processor doesn't
402 /// support branch trace storage (BTS) 0 = BTS is supported
406 /// [Bit 11] Branch Trace Storage Unavailable (RO)
407 /// 1 = Processor doesn't support branch trace storage (BTS)
408 /// 0 = BTS is supported
412 /// [Bit 12] Precise Event Based Sampling Unavailable (RO) 1 = Processor
413 /// does not support precise event-based sampling (PEBS); 0 = PEBS is
414 /// supported. The Pentium M processor does not support PEBS.
419 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 =
420 /// Enhanced Intel SpeedStep Technology enabled. On the Pentium M
421 /// processor, this bit may be configured to be read-only.
426 /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
427 /// disabled. xTPR messages are optional messages that allow the processor
428 /// to inform the chipset of its priority. The default is processor
431 UINT32 xTPR_Message_Disable
:1;
436 /// All bit fields as a 32-bit value
440 /// All bit fields as a 64-bit value
443 } MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER
;
447 Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points
448 to the MSR containing the most recent branch record. See also: -
449 MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.12, "Last Branch, Interrupt,
450 and Exception Recording (Pentium M Processors)".
452 @param ECX MSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9)
453 @param EAX Lower 32-bits of MSR value.
454 @param EDX Upper 32-bits of MSR value.
460 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS);
461 AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr);
464 #define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9
468 Debug Control (R/W) Controls how several debug features are used. Bit
469 definitions are discussed in the referenced section. See Section 17.12,
470 "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".
472 @param ECX MSR_PENTIUM_M_DEBUGCTLB (0x000001D9)
473 @param EAX Lower 32-bits of MSR value.
474 @param EDX Upper 32-bits of MSR value.
480 Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB);
481 AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr);
484 #define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9
488 Last Exception Record To Linear IP (R) This area contains a pointer to the
489 target of the last branch instruction that the processor executed prior to
490 the last exception that was generated or the last interrupt that was
491 handled. See Section 17.12, "Last Branch, Interrupt, and Exception Recording
492 (Pentium M Processors)" and Section 17.13.2, "Last Branch and Last Exception
495 @param ECX MSR_PENTIUM_M_LER_TO_LIP (0x000001DD)
496 @param EAX Lower 32-bits of MSR value.
497 @param EDX Upper 32-bits of MSR value.
503 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP);
506 #define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD
510 Last Exception Record From Linear IP (R) Contains a pointer to the last
511 branch instruction that the processor executed prior to the last exception
512 that was generated or the last interrupt that was handled. See Section
513 17.12, "Last Branch, Interrupt, and Exception Recording (Pentium M
514 Processors)" and Section 17.13.2, "Last Branch and Last Exception MSRs.".
516 @param ECX MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)
517 @param EAX Lower 32-bits of MSR value.
518 @param EDX Upper 32-bits of MSR value.
524 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP);
527 #define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE
531 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
533 @param ECX MSR_PENTIUM_M_MC4_CTL (0x0000040C)
534 @param EAX Lower 32-bits of MSR value.
535 @param EDX Upper 32-bits of MSR value.
541 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL);
542 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr);
545 #define MSR_PENTIUM_M_MC4_CTL 0x0000040C
549 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
551 @param ECX MSR_PENTIUM_M_MC4_STATUS (0x0000040D)
552 @param EAX Lower 32-bits of MSR value.
553 @param EDX Upper 32-bits of MSR value.
559 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS);
560 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr);
563 #define MSR_PENTIUM_M_MC4_STATUS 0x0000040D
567 See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is
568 either not implemented or contains no address if the ADDRV flag in the
569 MSR_MC4_STATUS register is clear. When not implemented in the processor, all
570 reads and writes to this MSR will cause a general-protection exception.
572 @param ECX MSR_PENTIUM_M_MC4_ADDR (0x0000040E)
573 @param EAX Lower 32-bits of MSR value.
574 @param EDX Upper 32-bits of MSR value.
580 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR);
581 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr);
584 #define MSR_PENTIUM_M_MC4_ADDR 0x0000040E
588 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
590 @param ECX MSR_PENTIUM_M_MC3_CTL (0x00000410)
591 @param EAX Lower 32-bits of MSR value.
592 @param EDX Upper 32-bits of MSR value.
598 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL);
599 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr);
602 #define MSR_PENTIUM_M_MC3_CTL 0x00000410
606 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
608 @param ECX MSR_PENTIUM_M_MC3_STATUS (0x00000411)
609 @param EAX Lower 32-bits of MSR value.
610 @param EDX Upper 32-bits of MSR value.
616 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS);
617 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr);
620 #define MSR_PENTIUM_M_MC3_STATUS 0x00000411
624 See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is
625 either not implemented or contains no address if the ADDRV flag in the
626 MSR_MC3_STATUS register is clear. When not implemented in the processor, all
627 reads and writes to this MSR will cause a general-protection exception.
629 @param ECX MSR_PENTIUM_M_MC3_ADDR (0x00000412)
630 @param EAX Lower 32-bits of MSR value.
631 @param EDX Upper 32-bits of MSR value.
637 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR);
638 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr);
641 #define MSR_PENTIUM_M_MC3_ADDR 0x00000412