UefiCpuPkg/Include/Register/Msr/PentiumMsr.h

   1 /** @file
   2   MSR Definitions for Pentium Processors.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
  10   This program and the accompanying materials
  11   are licensed and made available under the terms and conditions of the BSD License
  12   which accompanies this distribution.  The full text of the license may be found at
  13   http://opensource.org/licenses/bsd-license.php
  14
  15   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17
  18   @par Specification Reference:
  19   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
  20   December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-20.
  21
  22 **/
  23
  24 #ifndef __PENTIUM_MSR_H__
  25 #define __PENTIUM_MSR_H__
  26
  27 #include <Register/ArchitecturalMsr.h>
  28
  29 /**
  30   See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
  31
  32   @param  ECX  MSR_PENTIUM_P5_MC_ADDR (0x00000000)
  33   @param  EAX  Lower 32-bits of MSR value.
  34   @param  EDX  Upper 32-bits of MSR value.
  35
  36   <b>Example usage</b>
  37   @code
  38   UINT64  Msr;
  39
  40   Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR);
  41   AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr);
  42   @endcode
  43 **/
  44 #define MSR_PENTIUM_P5_MC_ADDR                   0x00000000
  45
  46
  47 /**
  48   See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
  49
  50   @param  ECX  MSR_PENTIUM_P5_MC_TYPE (0x00000001)
  51   @param  EAX  Lower 32-bits of MSR value.
  52   @param  EDX  Upper 32-bits of MSR value.
  53
  54   <b>Example usage</b>
  55   @code
  56   UINT64  Msr;
  57
  58   Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE);
  59   AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr);
  60   @endcode
  61 **/
  62 #define MSR_PENTIUM_P5_MC_TYPE                   0x00000001
  63
  64
  65 /**
  66   See Section 17.14, "Time-Stamp Counter.".
  67
  68   @param  ECX  MSR_PENTIUM_TSC (0x00000010)
  69   @param  EAX  Lower 32-bits of MSR value.
  70   @param  EDX  Upper 32-bits of MSR value.
  71
  72   <b>Example usage</b>
  73   @code
  74   UINT64  Msr;
  75
  76   Msr = AsmReadMsr64 (MSR_PENTIUM_TSC);
  77   AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr);
  78   @endcode
  79 **/
  80 #define MSR_PENTIUM_TSC                          0x00000010
  81
  82
  83 /**
  84   See Section 18.20.1, "Control and Event Select Register (CESR).".
  85
  86   @param  ECX  MSR_PENTIUM_CESR (0x00000011)
  87   @param  EAX  Lower 32-bits of MSR value.
  88   @param  EDX  Upper 32-bits of MSR value.
  89
  90   <b>Example usage</b>
  91   @code
  92   UINT64  Msr;
  93
  94   Msr = AsmReadMsr64 (MSR_PENTIUM_CESR);
  95   AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr);
  96   @endcode
  97 **/
  98 #define MSR_PENTIUM_CESR                         0x00000011
  99
 100
 101 /**
 102   Section 18.20.3, "Events Counted.".
 103
 104   @param  ECX  MSR_PENTIUM_CTRn
 105   @param  EAX  Lower 32-bits of MSR value.
 106   @param  EDX  Upper 32-bits of MSR value.
 107
 108   <b>Example usage</b>
 109   @code
 110   UINT64  Msr;
 111
 112   Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);
 113   AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);
 114   @endcode
 115   @{
 116 **/
 117 #define MSR_PENTIUM_CTR0                         0x00000012
 118 #define MSR_PENTIUM_CTR1                         0x00000013
 119 /// @}
 120
 121 #endif