2 MSR Definitions for Intel processors based on the Sandy Bridge microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
18 #ifndef __SANDY_BRIDGE_MSR_H__
19 #define __SANDY_BRIDGE_MSR_H__
21 #include <Register/ArchitecturalMsr.h>
24 Is Intel processors based on the Sandy Bridge microarchitecture?
26 @param DisplayFamily Display Family ID
27 @param DisplayModel Display Model ID
29 @retval TRUE Yes, it is.
30 @retval FALSE No, it isn't.
32 #define IS_SANDY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
35 DisplayModel == 0x2A || \
36 DisplayModel == 0x2D \
41 Thread. SMI Counter (R/O).
43 @param ECX MSR_SANDY_BRIDGE_SMI_COUNT (0x00000034)
44 @param EAX Lower 32-bits of MSR value.
45 Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.
46 @param EDX Upper 32-bits of MSR value.
47 Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.
51 MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER Msr;
53 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_SMI_COUNT);
55 @note MSR_SANDY_BRIDGE_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
57 #define MSR_SANDY_BRIDGE_SMI_COUNT 0x00000034
60 MSR information returned for MSR index #MSR_SANDY_BRIDGE_SMI_COUNT
64 /// Individual bit fields
68 /// [Bits 31:0] SMI Count (R/O) Count SMIs.
74 /// All bit fields as a 32-bit value
78 /// All bit fields as a 64-bit value
81 } MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER
;
85 Package. Platform Information Contains power management and other model
86 specific features enumeration. See http://biosbits.org.
88 @param ECX MSR_SANDY_BRIDGE_PLATFORM_INFO (0x000000CE)
89 @param EAX Lower 32-bits of MSR value.
90 Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.
91 @param EDX Upper 32-bits of MSR value.
92 Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.
96 MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER Msr;
98 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO);
99 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
101 @note MSR_SANDY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
103 #define MSR_SANDY_BRIDGE_PLATFORM_INFO 0x000000CE
106 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PLATFORM_INFO
110 /// Individual bit fields
115 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
116 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
119 UINT32 MaximumNonTurboRatio
:8;
122 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
123 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
124 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
125 /// Turbo mode is disabled.
129 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
130 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
131 /// and when set to 0, indicates TDP Limit for Turbo mode is not
138 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
139 /// minimum ratio (maximum efficiency) that the processor can operates, in
142 UINT32 MaximumEfficiencyRatio
:8;
146 /// All bit fields as a 64-bit value
149 } MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER
;
153 Core. C-State Configuration Control (R/W) Note: C-state values are
154 processor specific C-state code names, unrelated to MWAIT extension C-state
155 parameters or ACPI CStates. See http://biosbits.org.
157 @param ECX MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)
158 @param EAX Lower 32-bits of MSR value.
159 Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
160 @param EDX Upper 32-bits of MSR value.
161 Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
165 MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
167 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL);
168 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
170 @note MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
172 #define MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2
175 MSR information returned for MSR index
176 #MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL
180 /// Individual bit fields
184 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
185 /// processor-specific C-state code name (consuming the least power). for
186 /// the package. The default is set as factory-configured package C-state
187 /// limit. The following C-state code name encodings are supported: 000b:
188 /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:
189 /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:
190 /// This field cannot be used to limit package C-state to C3.
195 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
196 /// IO_read instructions sent to IO register specified by
197 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
202 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
203 /// until next reset.
208 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor
209 /// will conditionally demote C6/C7 requests to C3 based on uncore
210 /// auto-demote information.
212 UINT32 C3AutoDemotion
:1;
214 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor
215 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
216 /// auto-demote information.
218 UINT32 C1AutoDemotion
:1;
220 /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from
223 UINT32 C3Undemotion
:1;
225 /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from
228 UINT32 C1Undemotion
:1;
233 /// All bit fields as a 32-bit value
237 /// All bit fields as a 64-bit value
240 } MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER
;
244 Core. Power Management IO Redirection in C-state (R/W) See
247 @param ECX MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE (0x000000E4)
248 @param EAX Lower 32-bits of MSR value.
249 Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.
250 @param EDX Upper 32-bits of MSR value.
251 Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.
255 MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER Msr;
257 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE);
258 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE, Msr.Uint64);
260 @note MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
262 #define MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE 0x000000E4
265 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE
269 /// Individual bit fields
273 /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address
274 /// visible to software for IO redirection. If IO MWAIT Redirection is
275 /// enabled, reads to this address will be consumed by the power
276 /// management logic and decoded to MWAIT instructions. When IO port
277 /// address redirection is enabled, this is the IO port address reported
278 /// to the OS/software.
282 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
283 /// maximum C-State code name to be included when IO read to MWAIT
284 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3
285 /// is the max C-State to include 001b - C6 is the max C-State to include
286 /// 010b - C7 is the max C-State to include.
288 UINT32 CStateRange
:3;
293 /// All bit fields as a 32-bit value
297 /// All bit fields as a 64-bit value
300 } MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER
;
304 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
305 handler to handle unsuccessful read of this MSR.
307 @param ECX MSR_SANDY_BRIDGE_FEATURE_CONFIG (0x0000013C)
308 @param EAX Lower 32-bits of MSR value.
309 Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.
310 @param EDX Upper 32-bits of MSR value.
311 Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.
315 MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER Msr;
317 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);
318 AsmWriteMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG, Msr.Uint64);
320 @note MSR_SANDY_BRIDGE_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
322 #define MSR_SANDY_BRIDGE_FEATURE_CONFIG 0x0000013C
325 MSR information returned for MSR index #MSR_SANDY_BRIDGE_FEATURE_CONFIG
329 /// Individual bit fields
333 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
334 /// MSR, the configuration of AES instruction set availability is as
335 /// follows: 11b: AES instructions are not available until next RESET.
336 /// otherwise, AES instructions are available. Note, AES instruction set
337 /// is not available if read is unsuccessful. If the configuration is not
338 /// 01b, AES instruction can be mis-configured if a privileged agent
339 /// unintentionally writes 11b.
341 UINT32 AESConfiguration
:2;
346 /// All bit fields as a 32-bit value
350 /// All bit fields as a 64-bit value
353 } MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER
;
357 Core. See Table 2-2. If CPUID.0AH:EAX[15:8] = 8.
359 @param ECX MSR_SANDY_BRIDGE_IA32_PERFEVTSELn
360 @param EAX Lower 32-bits of MSR value.
361 @param EDX Upper 32-bits of MSR value.
367 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4);
368 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4, Msr);
370 @note MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 is defined as IA32_PERFEVTSEL4 in SDM.
371 MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 is defined as IA32_PERFEVTSEL5 in SDM.
372 MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 is defined as IA32_PERFEVTSEL6 in SDM.
373 MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 is defined as IA32_PERFEVTSEL7 in SDM.
376 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 0x0000018A
377 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 0x0000018B
378 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 0x0000018C
379 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 0x0000018D
386 @param ECX MSR_SANDY_BRIDGE_PERF_STATUS (0x00000198)
387 @param EAX Lower 32-bits of MSR value.
388 Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.
389 @param EDX Upper 32-bits of MSR value.
390 Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.
394 MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER Msr;
396 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS);
397 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS, Msr.Uint64);
399 @note MSR_SANDY_BRIDGE_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
401 #define MSR_SANDY_BRIDGE_PERF_STATUS 0x00000198
404 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PERF_STATUS
408 /// Individual bit fields
413 /// [Bits 47:32] Core Voltage (R/O) P-state core voltage can be computed
414 /// by MSR_PERF_STATUS[37:32] * (float) 1/(2^13).
416 UINT32 CoreVoltage
:16;
420 /// All bit fields as a 64-bit value
423 } MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER
;
427 Thread. Clock Modulation (R/W) See Table 2-2. IA32_CLOCK_MODULATION MSR was
428 originally named IA32_THERM_CONTROL MSR.
430 @param ECX MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION (0x0000019A)
431 @param EAX Lower 32-bits of MSR value.
432 Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.
433 @param EDX Upper 32-bits of MSR value.
434 Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.
438 MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER Msr;
440 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION);
441 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, Msr.Uint64);
443 @note MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.
445 #define MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION 0x0000019A
448 MSR information returned for MSR index
449 #MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION
453 /// Individual bit fields
457 /// [Bits 3:0] On demand Clock Modulation Duty Cycle (R/W) In 6.25%
460 UINT32 OnDemandClockModulationDutyCycle
:4;
462 /// [Bit 4] On demand Clock Modulation Enable (R/W).
464 UINT32 OnDemandClockModulationEnable
:1;
469 /// All bit fields as a 32-bit value
473 /// All bit fields as a 64-bit value
476 } MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER
;
480 Enable Misc. Processor Features (R/W) Allows a variety of processor
481 functions to be enabled and disabled.
483 @param ECX MSR_SANDY_BRIDGE_IA32_MISC_ENABLE (0x000001A0)
484 @param EAX Lower 32-bits of MSR value.
485 Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.
486 @param EDX Upper 32-bits of MSR value.
487 Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.
491 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER Msr;
493 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE);
494 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE, Msr.Uint64);
496 @note MSR_SANDY_BRIDGE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
498 #define MSR_SANDY_BRIDGE_IA32_MISC_ENABLE 0x000001A0
501 MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MISC_ENABLE
505 /// Individual bit fields
509 /// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.
511 UINT32 FastStrings
:1;
514 /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.
516 UINT32 PerformanceMonitoring
:1;
519 /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.
523 /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See
529 /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
535 /// [Bit 18] Thread. ENABLE MONITOR FSM (R/W) See Table 2-2.
540 /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.
542 UINT32 LimitCpuidMaxval
:1;
544 /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.
546 UINT32 xTPR_Message_Disable
:1;
550 /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.
555 /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors
556 /// that support Intel Turbo Boost Technology, the turbo mode feature is
557 /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
558 /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
559 /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
560 /// the power-on default value is used by BIOS to detect hardware support
561 /// of turbo mode. If power-on default value is 1, turbo mode is available
562 /// in the processor. If power-on default value is 0, turbo mode is not
565 UINT32 TurboModeDisable
:1;
569 /// All bit fields as a 64-bit value
572 } MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER
;
578 @param ECX MSR_SANDY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)
579 @param EAX Lower 32-bits of MSR value.
580 Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
581 @param EDX Upper 32-bits of MSR value.
582 Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
586 MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr;
588 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET);
589 AsmWriteMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);
591 @note MSR_SANDY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
593 #define MSR_SANDY_BRIDGE_TEMPERATURE_TARGET 0x000001A2
596 MSR information returned for MSR index #MSR_SANDY_BRIDGE_TEMPERATURE_TARGET
600 /// Individual bit fields
605 /// [Bits 23:16] Temperature Target (R) The minimum temperature at which
606 /// PROCHOT# will be asserted. The value is degree C.
608 UINT32 TemperatureTarget
:8;
613 /// All bit fields as a 32-bit value
617 /// All bit fields as a 64-bit value
620 } MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER
;
624 Miscellaneous Feature Control (R/W).
626 @param ECX MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL (0x000001A4)
627 @param EAX Lower 32-bits of MSR value.
628 Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.
629 @param EDX Upper 32-bits of MSR value.
630 Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.
634 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER Msr;
636 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL);
637 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL, Msr.Uint64);
639 @note MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
641 #define MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL 0x000001A4
644 MSR information returned for MSR index #MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL
648 /// Individual bit fields
652 /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
653 /// L2 hardware prefetcher, which fetches additional lines of code or data
654 /// into the L2 cache.
656 UINT32 L2HardwarePrefetcherDisable
:1;
658 /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,
659 /// disables the adjacent cache line prefetcher, which fetches the cache
660 /// line that comprises a cache line pair (128 bytes).
662 UINT32 L2AdjacentCacheLinePrefetcherDisable
:1;
664 /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables
665 /// the L1 data cache prefetcher, which fetches the next cache line into
668 UINT32 DCUHardwarePrefetcherDisable
:1;
670 /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1
671 /// data cache IP prefetcher, which uses sequential load history (based on
672 /// instruction Pointer of previous loads) to determine whether to
673 /// prefetch additional lines.
675 UINT32 DCUIPPrefetcherDisable
:1;
680 /// All bit fields as a 32-bit value
684 /// All bit fields as a 64-bit value
687 } MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER
;
691 Thread. Offcore Response Event Select Register (R/W).
693 @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_0 (0x000001A6)
694 @param EAX Lower 32-bits of MSR value.
695 @param EDX Upper 32-bits of MSR value.
701 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0);
702 AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0, Msr);
704 @note MSR_SANDY_BRIDGE_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
706 #define MSR_SANDY_BRIDGE_OFFCORE_RSP_0 0x000001A6
710 Thread. Offcore Response Event Select Register (R/W).
712 @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_1 (0x000001A7)
713 @param EAX Lower 32-bits of MSR value.
714 @param EDX Upper 32-bits of MSR value.
720 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1);
721 AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1, Msr);
723 @note MSR_SANDY_BRIDGE_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
725 #define MSR_SANDY_BRIDGE_OFFCORE_RSP_1 0x000001A7
729 See http://biosbits.org.
731 @param ECX MSR_SANDY_BRIDGE_MISC_PWR_MGMT (0x000001AA)
732 @param EAX Lower 32-bits of MSR value.
733 @param EDX Upper 32-bits of MSR value.
739 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT);
740 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT, Msr);
742 @note MSR_SANDY_BRIDGE_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.
744 #define MSR_SANDY_BRIDGE_MISC_PWR_MGMT 0x000001AA
748 Thread. Last Branch Record Filtering Select Register (R/W) See Section
749 17.9.2, "Filtering of Last Branch Records.".
751 @param ECX MSR_SANDY_BRIDGE_LBR_SELECT (0x000001C8)
752 @param EAX Lower 32-bits of MSR value.
753 Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.
754 @param EDX Upper 32-bits of MSR value.
755 Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.
759 MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER Msr;
761 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT);
762 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT, Msr.Uint64);
764 @note MSR_SANDY_BRIDGE_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
766 #define MSR_SANDY_BRIDGE_LBR_SELECT 0x000001C8
769 MSR information returned for MSR index #MSR_SANDY_BRIDGE_LBR_SELECT
773 /// Individual bit fields
777 /// [Bit 0] CPL_EQ_0.
781 /// [Bit 1] CPL_NEQ_0.
789 /// [Bit 3] NEAR_REL_CALL.
791 UINT32 NEAR_REL_CALL
:1;
793 /// [Bit 4] NEAR_IND_CALL.
795 UINT32 NEAR_IND_CALL
:1;
797 /// [Bit 5] NEAR_RET.
801 /// [Bit 6] NEAR_IND_JMP.
803 UINT32 NEAR_IND_JMP
:1;
805 /// [Bit 7] NEAR_REL_JMP.
807 UINT32 NEAR_REL_JMP
:1;
809 /// [Bit 8] FAR_BRANCH.
816 /// All bit fields as a 32-bit value
820 /// All bit fields as a 64-bit value
823 } MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER
;
827 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
828 that points to the MSR containing the most recent branch record. See
829 MSR_LASTBRANCH_0_FROM_IP (at 680H).
831 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_TOS (0x000001C9)
832 @param EAX Lower 32-bits of MSR value.
833 @param EDX Upper 32-bits of MSR value.
839 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS);
840 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS, Msr);
842 @note MSR_SANDY_BRIDGE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
844 #define MSR_SANDY_BRIDGE_LASTBRANCH_TOS 0x000001C9
848 Thread. Last Exception Record From Linear IP (R) Contains a pointer to the
849 last branch instruction that the processor executed prior to the last
850 exception that was generated or the last interrupt that was handled.
852 @param ECX MSR_SANDY_BRIDGE_LER_FROM_LIP (0x000001DD)
853 @param EAX Lower 32-bits of MSR value.
854 @param EDX Upper 32-bits of MSR value.
860 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_FROM_LIP);
862 @note MSR_SANDY_BRIDGE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
864 #define MSR_SANDY_BRIDGE_LER_FROM_LIP 0x000001DD
868 Thread. Last Exception Record To Linear IP (R) This area contains a pointer
869 to the target of the last branch instruction that the processor executed
870 prior to the last exception that was generated or the last interrupt that
873 @param ECX MSR_SANDY_BRIDGE_LER_TO_LIP (0x000001DE)
874 @param EAX Lower 32-bits of MSR value.
875 @param EDX Upper 32-bits of MSR value.
881 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_TO_LIP);
883 @note MSR_SANDY_BRIDGE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
885 #define MSR_SANDY_BRIDGE_LER_TO_LIP 0x000001DE
889 Core. See http://biosbits.org.
891 @param ECX MSR_SANDY_BRIDGE_POWER_CTL (0x000001FC)
892 @param EAX Lower 32-bits of MSR value.
893 @param EDX Upper 32-bits of MSR value.
899 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_POWER_CTL);
900 AsmWriteMsr64 (MSR_SANDY_BRIDGE_POWER_CTL, Msr);
902 @note MSR_SANDY_BRIDGE_POWER_CTL is defined as MSR_POWER_CTL in SDM.
904 #define MSR_SANDY_BRIDGE_POWER_CTL 0x000001FC
908 Package. Always 0 (CMCI not supported).
910 @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL2 (0x00000284)
911 @param EAX Lower 32-bits of MSR value.
912 @param EDX Upper 32-bits of MSR value.
918 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2);
919 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2, Msr);
921 @note MSR_SANDY_BRIDGE_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.
923 #define MSR_SANDY_BRIDGE_IA32_MC4_CTL2 0x00000284
927 See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".
929 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS (0x0000038E)
930 @param EAX Lower 32-bits of MSR value.
931 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER.
932 @param EDX Upper 32-bits of MSR value.
933 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER.
937 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
939 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS);
940 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);
942 @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
944 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS 0x0000038E
947 MSR information returned for MSR index
948 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS
952 /// Individual bit fields
956 /// [Bit 0] Thread. Ovf_PMC0.
960 /// [Bit 1] Thread. Ovf_PMC1.
964 /// [Bit 2] Thread. Ovf_PMC2.
968 /// [Bit 3] Thread. Ovf_PMC3.
972 /// [Bit 4] Core. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
976 /// [Bit 5] Core. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
980 /// [Bit 6] Core. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
984 /// [Bit 7] Core. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
989 /// [Bit 32] Thread. Ovf_FixedCtr0.
991 UINT32 Ovf_FixedCtr0
:1;
993 /// [Bit 33] Thread. Ovf_FixedCtr1.
995 UINT32 Ovf_FixedCtr1
:1;
997 /// [Bit 34] Thread. Ovf_FixedCtr2.
999 UINT32 Ovf_FixedCtr2
:1;
1000 UINT32 Reserved2
:26;
1002 /// [Bit 61] Thread. Ovf_Uncore.
1004 UINT32 Ovf_Uncore
:1;
1006 /// [Bit 62] Thread. Ovf_BufDSSAVE.
1008 UINT32 Ovf_BufDSSAVE
:1;
1010 /// [Bit 63] Thread. CondChgd.
1015 /// All bit fields as a 64-bit value
1018 } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER
;
1022 Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control
1025 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL (0x0000038F)
1026 @param EAX Lower 32-bits of MSR value.
1027 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.
1028 @param EDX Upper 32-bits of MSR value.
1029 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.
1031 <b>Example usage</b>
1033 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;
1035 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL);
1036 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);
1038 @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.
1040 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL 0x0000038F
1043 MSR information returned for MSR index
1044 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL
1048 /// Individual bit fields
1052 /// [Bit 0] Thread. Set 1 to enable PMC0 to count.
1056 /// [Bit 1] Thread. Set 1 to enable PMC1 to count.
1060 /// [Bit 2] Thread. Set 1 to enable PMC2 to count.
1064 /// [Bit 3] Thread. Set 1 to enable PMC3 to count.
1068 /// [Bit 4] Core. Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] >
1073 /// [Bit 5] Core. Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] >
1078 /// [Bit 6] Core. Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] >
1083 /// [Bit 7] Core. Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] >
1087 UINT32 Reserved1
:24;
1089 /// [Bit 32] Thread. Set 1 to enable FixedCtr0 to count.
1091 UINT32 FIXED_CTR0
:1;
1093 /// [Bit 33] Thread. Set 1 to enable FixedCtr1 to count.
1095 UINT32 FIXED_CTR1
:1;
1097 /// [Bit 34] Thread. Set 1 to enable FixedCtr2 to count.
1099 UINT32 FIXED_CTR2
:1;
1100 UINT32 Reserved2
:29;
1103 /// All bit fields as a 64-bit value
1106 } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
;
1110 See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".
1112 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)
1113 @param EAX Lower 32-bits of MSR value.
1114 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
1115 @param EDX Upper 32-bits of MSR value.
1116 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
1118 <b>Example usage</b>
1120 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;
1122 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL);
1123 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
1125 @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.
1127 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
1130 MSR information returned for MSR index
1131 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL
1135 /// Individual bit fields
1139 /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.
1143 /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.
1147 /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.
1151 /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.
1155 /// [Bit 4] Core. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
1159 /// [Bit 5] Core. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
1163 /// [Bit 6] Core. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
1167 /// [Bit 7] Core. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
1170 UINT32 Reserved1
:24;
1172 /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.
1174 UINT32 Ovf_FixedCtr0
:1;
1176 /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.
1178 UINT32 Ovf_FixedCtr1
:1;
1180 /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.
1182 UINT32 Ovf_FixedCtr2
:1;
1183 UINT32 Reserved2
:26;
1185 /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.
1187 UINT32 Ovf_Uncore
:1;
1189 /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.
1191 UINT32 Ovf_BufDSSAVE
:1;
1193 /// [Bit 63] Thread. Set 1 to clear CondChgd.
1198 /// All bit fields as a 64-bit value
1201 } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER
;
1205 Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".
1207 @param ECX MSR_SANDY_BRIDGE_PEBS_ENABLE (0x000003F1)
1208 @param EAX Lower 32-bits of MSR value.
1209 Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.
1210 @param EDX Upper 32-bits of MSR value.
1211 Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.
1213 <b>Example usage</b>
1215 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER Msr;
1217 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE);
1218 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE, Msr.Uint64);
1220 @note MSR_SANDY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1222 #define MSR_SANDY_BRIDGE_PEBS_ENABLE 0x000003F1
1225 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_ENABLE
1229 /// Individual bit fields
1233 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
1235 UINT32 PEBS_EN_PMC0
:1;
1237 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
1239 UINT32 PEBS_EN_PMC1
:1;
1241 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
1243 UINT32 PEBS_EN_PMC2
:1;
1245 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
1247 UINT32 PEBS_EN_PMC3
:1;
1248 UINT32 Reserved1
:28;
1250 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
1252 UINT32 LL_EN_PMC0
:1;
1254 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
1256 UINT32 LL_EN_PMC1
:1;
1258 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
1260 UINT32 LL_EN_PMC2
:1;
1262 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
1264 UINT32 LL_EN_PMC3
:1;
1265 UINT32 Reserved2
:27;
1267 /// [Bit 63] Enable Precise Store. (R/W).
1272 /// All bit fields as a 64-bit value
1275 } MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
;
1279 Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring
1282 @param ECX MSR_SANDY_BRIDGE_PEBS_LD_LAT (0x000003F6)
1283 @param EAX Lower 32-bits of MSR value.
1284 Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.
1285 @param EDX Upper 32-bits of MSR value.
1286 Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.
1288 <b>Example usage</b>
1290 MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER Msr;
1292 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT);
1293 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT, Msr.Uint64);
1295 @note MSR_SANDY_BRIDGE_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.
1297 #define MSR_SANDY_BRIDGE_PEBS_LD_LAT 0x000003F6
1300 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_LD_LAT
1304 /// Individual bit fields
1308 /// [Bits 15:0] Minimum threshold latency value of tagged load operation
1309 /// that will be counted. (R/W).
1311 UINT32 MinimumThreshold
:16;
1312 UINT32 Reserved1
:16;
1313 UINT32 Reserved2
:32;
1316 /// All bit fields as a 32-bit value
1320 /// All bit fields as a 64-bit value
1323 } MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER
;
1327 Package. Note: C-state values are processor specific C-state code names,
1328 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3
1329 Residency Counter. (R/O) Value since last reset that this package is in
1330 processor-specific C3 states. Count at the same frequency as the TSC.
1332 @param ECX MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY (0x000003F8)
1333 @param EAX Lower 32-bits of MSR value.
1334 @param EDX Upper 32-bits of MSR value.
1336 <b>Example usage</b>
1340 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY);
1341 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY, Msr);
1343 @note MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
1345 #define MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY 0x000003F8
1349 Package. Note: C-state values are processor specific C-state code names,
1350 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
1351 Residency Counter. (R/O) Value since last reset that this package is in
1352 processor-specific C6 states. Count at the same frequency as the TSC.
1354 @param ECX MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY (0x000003F9)
1355 @param EAX Lower 32-bits of MSR value.
1356 @param EDX Upper 32-bits of MSR value.
1358 <b>Example usage</b>
1362 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY);
1363 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY, Msr);
1365 @note MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
1367 #define MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY 0x000003F9
1371 Package. Note: C-state values are processor specific C-state code names,
1372 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7
1373 Residency Counter. (R/O) Value since last reset that this package is in
1374 processor-specific C7 states. Count at the same frequency as the TSC.
1376 @param ECX MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY (0x000003FA)
1377 @param EAX Lower 32-bits of MSR value.
1378 @param EDX Upper 32-bits of MSR value.
1380 <b>Example usage</b>
1384 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY);
1385 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY, Msr);
1387 @note MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
1389 #define MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY 0x000003FA
1393 Core. Note: C-state values are processor specific C-state code names,
1394 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3
1395 Residency Counter. (R/O) Value since last reset that this core is in
1396 processor-specific C3 states. Count at the same frequency as the TSC.
1398 @param ECX MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY (0x000003FC)
1399 @param EAX Lower 32-bits of MSR value.
1400 @param EDX Upper 32-bits of MSR value.
1402 <b>Example usage</b>
1406 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY);
1407 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY, Msr);
1409 @note MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.
1411 #define MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY 0x000003FC
1415 Core. Note: C-state values are processor specific C-state code names,
1416 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6
1417 Residency Counter. (R/O) Value since last reset that this core is in
1418 processor-specific C6 states. Count at the same frequency as the TSC.
1420 @param ECX MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY (0x000003FD)
1421 @param EAX Lower 32-bits of MSR value.
1422 @param EDX Upper 32-bits of MSR value.
1424 <b>Example usage</b>
1428 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY);
1429 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY, Msr);
1431 @note MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
1433 #define MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY 0x000003FD
1437 Core. Note: C-state values are processor specific C-state code names,
1438 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C7
1439 Residency Counter. (R/O) Value since last reset that this core is in
1440 processor-specific C7 states. Count at the same frequency as the TSC.
1442 @param ECX MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY (0x000003FE)
1443 @param EAX Lower 32-bits of MSR value.
1444 @param EDX Upper 32-bits of MSR value.
1446 <b>Example usage</b>
1450 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY);
1451 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY, Msr);
1453 @note MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY is defined as MSR_CORE_C7_RESIDENCY in SDM.
1455 #define MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY 0x000003FE
1459 Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
1461 @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL (0x00000410)
1462 @param EAX Lower 32-bits of MSR value.
1463 Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER.
1464 @param EDX Upper 32-bits of MSR value.
1465 Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER.
1467 <b>Example usage</b>
1469 MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER Msr;
1471 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL);
1472 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL, Msr.Uint64);
1474 @note MSR_SANDY_BRIDGE_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.
1476 #define MSR_SANDY_BRIDGE_IA32_MC4_CTL 0x00000410
1479 MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MC4_CTL
1483 /// Individual bit fields
1487 /// [Bit 0] PCU Hardware Error (R/W) When set, enables signaling of PCU
1488 /// hardware detected errors.
1490 UINT32 PCUHardwareError
:1;
1492 /// [Bit 1] PCU Controller Error (R/W) When set, enables signaling of PCU
1493 /// controller detected errors.
1495 UINT32 PCUControllerError
:1;
1497 /// [Bit 2] PCU Firmware Error (R/W) When set, enables signaling of PCU
1498 /// firmware detected errors.
1500 UINT32 PCUFirmwareError
:1;
1501 UINT32 Reserved1
:29;
1502 UINT32 Reserved2
:32;
1505 /// All bit fields as a 32-bit value
1509 /// All bit fields as a 64-bit value
1512 } MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER
;
1516 Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.
1518 @param ECX MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
1519 @param EAX Lower 32-bits of MSR value.
1520 @param EDX Upper 32-bits of MSR value.
1522 <b>Example usage</b>
1526 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM);
1528 @note MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
1530 #define MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM 0x0000048C
1534 Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,
1537 @param ECX MSR_SANDY_BRIDGE_RAPL_POWER_UNIT (0x00000606)
1538 @param EAX Lower 32-bits of MSR value.
1539 @param EDX Upper 32-bits of MSR value.
1541 <b>Example usage</b>
1545 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_RAPL_POWER_UNIT);
1547 @note MSR_SANDY_BRIDGE_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
1549 #define MSR_SANDY_BRIDGE_RAPL_POWER_UNIT 0x00000606
1553 Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are
1554 processor specific C-state code names, unrelated to MWAIT extension C-state
1555 parameters or ACPI CStates.
1557 @param ECX MSR_SANDY_BRIDGE_PKGC3_IRTL (0x0000060A)
1558 @param EAX Lower 32-bits of MSR value.
1559 Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.
1560 @param EDX Upper 32-bits of MSR value.
1561 Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.
1563 <b>Example usage</b>
1565 MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER Msr;
1567 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL);
1568 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL, Msr.Uint64);
1570 @note MSR_SANDY_BRIDGE_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.
1572 #define MSR_SANDY_BRIDGE_PKGC3_IRTL 0x0000060A
1575 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC3_IRTL
1579 /// Individual bit fields
1583 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
1584 /// that should be used to decide if the package should be put into a
1585 /// package C3 state.
1587 UINT32 TimeLimit
:10;
1589 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
1590 /// unit of the interrupt response time limit. The following time unit
1591 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
1592 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
1597 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
1598 /// valid and can be used by the processor for package C-sate management.
1601 UINT32 Reserved2
:16;
1602 UINT32 Reserved3
:32;
1605 /// All bit fields as a 32-bit value
1609 /// All bit fields as a 64-bit value
1612 } MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER
;
1616 Package. Package C6 Interrupt Response Limit (R/W) This MSR defines the
1617 budget allocated for the package to exit from C6 to a C0 state, where
1618 interrupt request can be delivered to the core and serviced. Additional
1619 core-exit latency amy be applicable depending on the actual C-state the core
1620 is in. Note: C-state values are processor specific C-state code names,
1621 unrelated to MWAIT extension C-state parameters or ACPI CStates.
1623 @param ECX MSR_SANDY_BRIDGE_PKGC6_IRTL (0x0000060B)
1624 @param EAX Lower 32-bits of MSR value.
1625 Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.
1626 @param EDX Upper 32-bits of MSR value.
1627 Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.
1629 <b>Example usage</b>
1631 MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER Msr;
1633 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL);
1634 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL, Msr.Uint64);
1636 @note MSR_SANDY_BRIDGE_PKGC6_IRTL is defined as MSR_PKGC6_IRTL in SDM.
1638 #define MSR_SANDY_BRIDGE_PKGC6_IRTL 0x0000060B
1641 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC6_IRTL
1645 /// Individual bit fields
1649 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
1650 /// that should be used to decide if the package should be put into a
1651 /// package C6 state.
1653 UINT32 TimeLimit
:10;
1655 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
1656 /// unit of the interrupt response time limit. The following time unit
1657 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
1658 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
1663 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
1664 /// valid and can be used by the processor for package C-sate management.
1667 UINT32 Reserved2
:16;
1668 UINT32 Reserved3
:32;
1671 /// All bit fields as a 32-bit value
1675 /// All bit fields as a 64-bit value
1678 } MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER
;
1682 Package. Note: C-state values are processor specific C-state code names,
1683 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2
1684 Residency Counter. (R/O) Value since last reset that this package is in
1685 processor-specific C2 states. Count at the same frequency as the TSC.
1687 @param ECX MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY (0x0000060D)
1688 @param EAX Lower 32-bits of MSR value.
1689 @param EDX Upper 32-bits of MSR value.
1691 <b>Example usage</b>
1695 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY);
1696 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY, Msr);
1698 @note MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
1700 #define MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY 0x0000060D
1704 Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
1707 @param ECX MSR_SANDY_BRIDGE_PKG_POWER_LIMIT (0x00000610)
1708 @param EAX Lower 32-bits of MSR value.
1709 @param EDX Upper 32-bits of MSR value.
1711 <b>Example usage</b>
1715 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT);
1716 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT, Msr);
1718 @note MSR_SANDY_BRIDGE_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
1720 #define MSR_SANDY_BRIDGE_PKG_POWER_LIMIT 0x00000610
1724 Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1726 @param ECX MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS (0x00000611)
1727 @param EAX Lower 32-bits of MSR value.
1728 @param EDX Upper 32-bits of MSR value.
1730 <b>Example usage</b>
1734 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS);
1736 @note MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
1738 #define MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS 0x00000611
1742 Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL
1745 @param ECX MSR_SANDY_BRIDGE_PKG_POWER_INFO (0x00000614)
1746 @param EAX Lower 32-bits of MSR value.
1747 @param EDX Upper 32-bits of MSR value.
1749 <b>Example usage</b>
1753 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO);
1754 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO, Msr);
1756 @note MSR_SANDY_BRIDGE_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
1758 #define MSR_SANDY_BRIDGE_PKG_POWER_INFO 0x00000614
1762 Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
1765 @param ECX MSR_SANDY_BRIDGE_PP0_POWER_LIMIT (0x00000638)
1766 @param EAX Lower 32-bits of MSR value.
1767 @param EDX Upper 32-bits of MSR value.
1769 <b>Example usage</b>
1773 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT);
1774 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT, Msr);
1776 @note MSR_SANDY_BRIDGE_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
1778 #define MSR_SANDY_BRIDGE_PP0_POWER_LIMIT 0x00000638
1782 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1785 @param ECX MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)
1786 @param EAX Lower 32-bits of MSR value.
1787 @param EDX Upper 32-bits of MSR value.
1789 <b>Example usage</b>
1793 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS);
1795 @note MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
1797 #define MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS 0x00000639
1801 Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last
1802 branch record registers on the last branch record stack. This part of the
1803 stack contains pointers to the source instruction. See also: - Last Branch
1804 Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section
1807 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_FROM_IP
1808 @param EAX Lower 32-bits of MSR value.
1809 @param EDX Upper 32-bits of MSR value.
1811 <b>Example usage</b>
1815 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP);
1816 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP, Msr);
1818 @note MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
1819 MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
1820 MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
1821 MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
1822 MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
1823 MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
1824 MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
1825 MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
1826 MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.
1827 MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.
1828 MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.
1829 MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.
1830 MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.
1831 MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.
1832 MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.
1833 MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.
1836 #define MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP 0x00000680
1837 #define MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP 0x00000681
1838 #define MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP 0x00000682
1839 #define MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP 0x00000683
1840 #define MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP 0x00000684
1841 #define MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP 0x00000685
1842 #define MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP 0x00000686
1843 #define MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP 0x00000687
1844 #define MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP 0x00000688
1845 #define MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP 0x00000689
1846 #define MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP 0x0000068A
1847 #define MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP 0x0000068B
1848 #define MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP 0x0000068C
1849 #define MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP 0x0000068D
1850 #define MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP 0x0000068E
1851 #define MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP 0x0000068F
1856 Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch
1857 record registers on the last branch record stack. This part of the stack
1858 contains pointers to the destination instruction.
1860 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_TO_IP
1861 @param EAX Lower 32-bits of MSR value.
1862 @param EDX Upper 32-bits of MSR value.
1864 <b>Example usage</b>
1868 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP);
1869 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP, Msr);
1871 @note MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
1872 MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
1873 MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
1874 MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
1875 MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
1876 MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
1877 MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
1878 MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
1879 MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.
1880 MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.
1881 MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.
1882 MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.
1883 MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.
1884 MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.
1885 MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.
1886 MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.
1889 #define MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP 0x000006C0
1890 #define MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP 0x000006C1
1891 #define MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP 0x000006C2
1892 #define MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP 0x000006C3
1893 #define MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP 0x000006C4
1894 #define MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP 0x000006C5
1895 #define MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP 0x000006C6
1896 #define MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP 0x000006C7
1897 #define MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP 0x000006C8
1898 #define MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP 0x000006C9
1899 #define MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP 0x000006CA
1900 #define MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP 0x000006CB
1901 #define MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP 0x000006CC
1902 #define MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP 0x000006CD
1903 #define MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP 0x000006CE
1904 #define MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP 0x000006CF
1909 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
1910 RW if MSR_PLATFORM_INFO.[28] = 1.
1912 @param ECX MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT (0x000001AD)
1913 @param EAX Lower 32-bits of MSR value.
1914 Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.
1915 @param EDX Upper 32-bits of MSR value.
1916 Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.
1918 <b>Example usage</b>
1920 MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER Msr;
1922 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT);
1924 @note MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
1926 #define MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT 0x000001AD
1929 MSR information returned for MSR index #MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT
1933 /// Individual bit fields
1937 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
1938 /// limit of 1 core active.
1942 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
1943 /// limit of 2 core active.
1947 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
1948 /// limit of 3 core active.
1952 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
1953 /// limit of 4 core active.
1957 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
1958 /// limit of 5 core active.
1962 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
1963 /// limit of 6 core active.
1967 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
1968 /// limit of 7 core active.
1972 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
1973 /// limit of 8 core active.
1978 /// All bit fields as a 64-bit value
1981 } MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER
;
1985 Package. Uncore PMU global control.
1987 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL (0x00000391)
1988 @param EAX Lower 32-bits of MSR value.
1989 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.
1990 @param EDX Upper 32-bits of MSR value.
1991 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.
1993 <b>Example usage</b>
1995 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;
1997 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL);
1998 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);
2000 @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.
2002 #define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL 0x00000391
2005 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL
2009 /// Individual bit fields
2013 /// [Bit 0] Slice 0 select.
2015 UINT32 PMI_Sel_Slice0
:1;
2017 /// [Bit 1] Slice 1 select.
2019 UINT32 PMI_Sel_Slice1
:1;
2021 /// [Bit 2] Slice 2 select.
2023 UINT32 PMI_Sel_Slice2
:1;
2025 /// [Bit 3] Slice 3 select.
2027 UINT32 PMI_Sel_Slice3
:1;
2029 /// [Bit 4] Slice 4 select.
2031 UINT32 PMI_Sel_Slice4
:1;
2032 UINT32 Reserved1
:14;
2033 UINT32 Reserved2
:10;
2035 /// [Bit 29] Enable all uncore counters.
2039 /// [Bit 30] Enable wake on PMI.
2043 /// [Bit 31] Enable Freezing counter when overflow.
2046 UINT32 Reserved3
:32;
2049 /// All bit fields as a 32-bit value
2053 /// All bit fields as a 64-bit value
2056 } MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER
;
2060 Package. Uncore PMU main status.
2062 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS (0x00000392)
2063 @param EAX Lower 32-bits of MSR value.
2064 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.
2065 @param EDX Upper 32-bits of MSR value.
2066 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.
2068 <b>Example usage</b>
2070 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;
2072 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS);
2073 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);
2075 @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.
2077 #define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS 0x00000392
2080 MSR information returned for MSR index
2081 #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS
2085 /// Individual bit fields
2089 /// [Bit 0] Fixed counter overflowed.
2093 /// [Bit 1] An ARB counter overflowed.
2098 /// [Bit 3] A CBox counter overflowed (on any slice).
2101 UINT32 Reserved2
:28;
2102 UINT32 Reserved3
:32;
2105 /// All bit fields as a 32-bit value
2109 /// All bit fields as a 64-bit value
2112 } MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER
;
2116 Package. Uncore fixed counter control (R/W).
2118 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL (0x00000394)
2119 @param EAX Lower 32-bits of MSR value.
2120 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.
2121 @param EDX Upper 32-bits of MSR value.
2122 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.
2124 <b>Example usage</b>
2126 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER Msr;
2128 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL);
2129 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL, Msr.Uint64);
2131 @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.
2133 #define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL 0x00000394
2136 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL
2140 /// Individual bit fields
2143 UINT32 Reserved1
:20;
2145 /// [Bit 20] Enable overflow propagation.
2147 UINT32 EnableOverflow
:1;
2150 /// [Bit 22] Enable counting.
2152 UINT32 EnableCounting
:1;
2154 UINT32 Reserved4
:32;
2157 /// All bit fields as a 32-bit value
2161 /// All bit fields as a 64-bit value
2164 } MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER
;
2168 Package. Uncore fixed counter.
2170 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR (0x00000395)
2171 @param EAX Lower 32-bits of MSR value.
2172 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.
2173 @param EDX Upper 32-bits of MSR value.
2174 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.
2176 <b>Example usage</b>
2178 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER Msr;
2180 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR);
2181 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR, Msr.Uint64);
2183 @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.
2185 #define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR 0x00000395
2188 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR
2192 /// Individual bit fields
2196 /// [Bits 31:0] Current count.
2198 UINT32 CurrentCount
:32;
2200 /// [Bits 47:32] Current count.
2202 UINT32 CurrentCountHi
:16;
2206 /// All bit fields as a 64-bit value
2209 } MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER
;
2213 Package. Uncore C-Box configuration information (R/O).
2215 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_CONFIG (0x00000396)
2216 @param EAX Lower 32-bits of MSR value.
2217 Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.
2218 @param EDX Upper 32-bits of MSR value.
2219 Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.
2221 <b>Example usage</b>
2223 MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER Msr;
2225 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_CONFIG);
2227 @note MSR_SANDY_BRIDGE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.
2229 #define MSR_SANDY_BRIDGE_UNC_CBO_CONFIG 0x00000396
2232 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_CBO_CONFIG
2236 /// Individual bit fields
2240 /// [Bits 3:0] Report the number of C-Box units with performance counters,
2241 /// including processor cores and processor graphics".
2244 UINT32 Reserved1
:28;
2245 UINT32 Reserved2
:32;
2248 /// All bit fields as a 32-bit value
2252 /// All bit fields as a 64-bit value
2255 } MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER
;
2259 Package. Uncore Arb unit, performance counter 0.
2261 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 (0x000003B0)
2262 @param EAX Lower 32-bits of MSR value.
2263 @param EDX Upper 32-bits of MSR value.
2265 <b>Example usage</b>
2269 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0);
2270 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0, Msr);
2272 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.
2274 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 0x000003B0
2278 Package. Uncore Arb unit, performance counter 1.
2280 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 (0x000003B1)
2281 @param EAX Lower 32-bits of MSR value.
2282 @param EDX Upper 32-bits of MSR value.
2284 <b>Example usage</b>
2288 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1);
2289 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1, Msr);
2291 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.
2293 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 0x000003B1
2297 Package. Uncore Arb unit, counter 0 event select MSR.
2299 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 (0x000003B2)
2300 @param EAX Lower 32-bits of MSR value.
2301 @param EDX Upper 32-bits of MSR value.
2303 <b>Example usage</b>
2307 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0);
2308 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0, Msr);
2310 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.
2312 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 0x000003B2
2316 Package. Uncore Arb unit, counter 1 event select MSR.
2318 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 (0x000003B3)
2319 @param EAX Lower 32-bits of MSR value.
2320 @param EDX Upper 32-bits of MSR value.
2322 <b>Example usage</b>
2326 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1);
2327 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1, Msr);
2329 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.
2331 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 0x000003B3
2335 Package. Package C7 Interrupt Response Limit (R/W) This MSR defines the
2336 budget allocated for the package to exit from C7 to a C0 state, where
2337 interrupt request can be delivered to the core and serviced. Additional
2338 core-exit latency amy be applicable depending on the actual C-state the core
2339 is in. Note: C-state values are processor specific C-state code names,
2340 unrelated to MWAIT extension C-state parameters or ACPI CStates.
2342 @param ECX MSR_SANDY_BRIDGE_PKGC7_IRTL (0x0000060C)
2343 @param EAX Lower 32-bits of MSR value.
2344 Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.
2345 @param EDX Upper 32-bits of MSR value.
2346 Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.
2348 <b>Example usage</b>
2350 MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER Msr;
2352 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL);
2353 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL, Msr.Uint64);
2355 @note MSR_SANDY_BRIDGE_PKGC7_IRTL is defined as MSR_PKGC7_IRTL in SDM.
2357 #define MSR_SANDY_BRIDGE_PKGC7_IRTL 0x0000060C
2360 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC7_IRTL
2364 /// Individual bit fields
2368 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
2369 /// that should be used to decide if the package should be put into a
2370 /// package C7 state.
2372 UINT32 TimeLimit
:10;
2374 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
2375 /// unit of the interrupt response time limit. The following time unit
2376 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
2377 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
2382 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
2383 /// valid and can be used by the processor for package C-sate management.
2386 UINT32 Reserved2
:16;
2387 UINT32 Reserved3
:32;
2390 /// All bit fields as a 32-bit value
2394 /// All bit fields as a 64-bit value
2397 } MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER
;
2401 Package. PP0 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
2404 @param ECX MSR_SANDY_BRIDGE_PP0_POLICY (0x0000063A)
2405 @param EAX Lower 32-bits of MSR value.
2406 @param EDX Upper 32-bits of MSR value.
2408 <b>Example usage</b>
2412 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY);
2413 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY, Msr);
2415 @note MSR_SANDY_BRIDGE_PP0_POLICY is defined as MSR_PP0_POLICY in SDM.
2417 #define MSR_SANDY_BRIDGE_PP0_POLICY 0x0000063A
2421 Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
2424 @param ECX MSR_SANDY_BRIDGE_PP1_POWER_LIMIT (0x00000640)
2425 @param EAX Lower 32-bits of MSR value.
2426 @param EDX Upper 32-bits of MSR value.
2428 <b>Example usage</b>
2432 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT);
2433 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT, Msr);
2435 @note MSR_SANDY_BRIDGE_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.
2437 #define MSR_SANDY_BRIDGE_PP1_POWER_LIMIT 0x00000640
2441 Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
2444 @param ECX MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS (0x00000641)
2445 @param EAX Lower 32-bits of MSR value.
2446 @param EDX Upper 32-bits of MSR value.
2448 <b>Example usage</b>
2452 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS);
2454 @note MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.
2456 #define MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS 0x00000641
2460 Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
2463 @param ECX MSR_SANDY_BRIDGE_PP1_POLICY (0x00000642)
2464 @param EAX Lower 32-bits of MSR value.
2465 @param EDX Upper 32-bits of MSR value.
2467 <b>Example usage</b>
2471 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY);
2472 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY, Msr);
2474 @note MSR_SANDY_BRIDGE_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.
2476 #define MSR_SANDY_BRIDGE_PP1_POLICY 0x00000642
2480 Package. Uncore C-Box 0, counter n event select MSR.
2482 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSELn
2483 @param EAX Lower 32-bits of MSR value.
2484 @param EDX Upper 32-bits of MSR value.
2486 <b>Example usage</b>
2490 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0);
2491 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0, Msr);
2493 @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.
2494 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.
2495 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 is defined as MSR_UNC_CBO_0_PERFEVTSEL2 in SDM.
2496 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 is defined as MSR_UNC_CBO_0_PERFEVTSEL3 in SDM.
2499 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 0x00000700
2500 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701
2501 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 0x00000702
2502 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 0x00000703
2507 Package. Uncore C-Box n, unit status for counter 0-3.
2509 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_n_UNIT_STATUS
2510 @param EAX Lower 32-bits of MSR value.
2511 @param EDX Upper 32-bits of MSR value.
2513 <b>Example usage</b>
2517 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS);
2518 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS, Msr);
2520 @note MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS is defined as MSR_UNC_CBO_0_UNIT_STATUS in SDM.
2521 MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS is defined as MSR_UNC_CBO_1_UNIT_STATUS in SDM.
2522 MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS is defined as MSR_UNC_CBO_2_UNIT_STATUS in SDM.
2523 MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS is defined as MSR_UNC_CBO_3_UNIT_STATUS in SDM.
2524 MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS is defined as MSR_UNC_CBO_4_UNIT_STATUS in SDM.
2527 #define MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS 0x00000705
2528 #define MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS 0x00000715
2529 #define MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS 0x00000725
2530 #define MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS 0x00000735
2531 #define MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS 0x00000745
2536 Package. Uncore C-Box 0, performance counter n.
2538 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTRn
2539 @param EAX Lower 32-bits of MSR value.
2540 @param EDX Upper 32-bits of MSR value.
2542 <b>Example usage</b>
2546 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0);
2547 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0, Msr);
2549 @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.
2550 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.
2551 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 is defined as MSR_UNC_CBO_0_PERFCTR2 in SDM.
2552 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 is defined as MSR_UNC_CBO_0_PERFCTR3 in SDM.
2555 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 0x00000706
2556 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 0x00000707
2557 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 0x00000708
2558 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 0x00000709
2563 Package. Uncore C-Box 1, counter n event select MSR.
2565 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSELn
2566 @param EAX Lower 32-bits of MSR value.
2567 @param EDX Upper 32-bits of MSR value.
2569 <b>Example usage</b>
2573 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0);
2574 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0, Msr);
2576 @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.
2577 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.
2578 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 is defined as MSR_UNC_CBO_1_PERFEVTSEL2 in SDM.
2579 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 is defined as MSR_UNC_CBO_1_PERFEVTSEL3 in SDM.
2582 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 0x00000710
2583 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 0x00000711
2584 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 0x00000712
2585 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 0x00000713
2590 Package. Uncore C-Box 1, performance counter n.
2592 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTRn
2593 @param EAX Lower 32-bits of MSR value.
2594 @param EDX Upper 32-bits of MSR value.
2596 <b>Example usage</b>
2600 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0);
2601 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0, Msr);
2603 @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.
2604 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.
2605 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 is defined as MSR_UNC_CBO_1_PERFCTR2 in SDM.
2606 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 is defined as MSR_UNC_CBO_1_PERFCTR3 in SDM.
2609 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 0x00000716
2610 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 0x00000717
2611 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 0x00000718
2612 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 0x00000719
2617 Package. Uncore C-Box 2, counter n event select MSR.
2619 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSELn
2620 @param EAX Lower 32-bits of MSR value.
2621 @param EDX Upper 32-bits of MSR value.
2623 <b>Example usage</b>
2627 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0);
2628 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0, Msr);
2630 @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.
2631 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.
2632 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 is defined as MSR_UNC_CBO_2_PERFEVTSEL2 in SDM.
2633 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 is defined as MSR_UNC_CBO_2_PERFEVTSEL3 in SDM.
2636 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 0x00000720
2637 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 0x00000721
2638 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 0x00000722
2639 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 0x00000723
2644 Package. Uncore C-Box 2, performance counter n.
2646 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTRn
2647 @param EAX Lower 32-bits of MSR value.
2648 @param EDX Upper 32-bits of MSR value.
2650 <b>Example usage</b>
2654 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0);
2655 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0, Msr);
2657 @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.
2658 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.
2659 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 is defined as MSR_UNC_CBO_2_PERFCTR2 in SDM.
2660 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 is defined as MSR_UNC_CBO_2_PERFCTR3 in SDM.
2663 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 0x00000726
2664 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 0x00000727
2665 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 0x00000728
2666 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 0x00000729
2671 Package. Uncore C-Box 3, counter n event select MSR.
2673 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSELn
2674 @param EAX Lower 32-bits of MSR value.
2675 @param EDX Upper 32-bits of MSR value.
2677 <b>Example usage</b>
2681 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0);
2682 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0, Msr);
2684 @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.
2685 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.
2686 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 is defined as MSR_UNC_CBO_3_PERFEVTSEL2 in SDM.
2687 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 is defined as MSR_UNC_CBO_3_PERFEVTSEL3 in SDM.
2690 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 0x00000730
2691 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731
2692 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 0x00000732
2693 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 0x00000733
2698 Package. Uncore C-Box 3, performance counter n.
2700 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTRn
2701 @param EAX Lower 32-bits of MSR value.
2702 @param EDX Upper 32-bits of MSR value.
2704 <b>Example usage</b>
2708 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0);
2709 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0, Msr);
2711 @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.
2712 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.
2713 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 is defined as MSR_UNC_CBO_3_PERFCTR2 in SDM.
2714 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 is defined as MSR_UNC_CBO_3_PERFCTR3 in SDM.
2717 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736
2718 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737
2719 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 0x00000738
2720 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 0x00000739
2725 Package. Uncore C-Box 4, counter n event select MSR.
2727 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSELn
2728 @param EAX Lower 32-bits of MSR value.
2729 @param EDX Upper 32-bits of MSR value.
2731 <b>Example usage</b>
2735 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0);
2736 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0, Msr);
2738 @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 is defined as MSR_UNC_CBO_4_PERFEVTSEL0 in SDM.
2739 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 is defined as MSR_UNC_CBO_4_PERFEVTSEL1 in SDM.
2740 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 is defined as MSR_UNC_CBO_4_PERFEVTSEL2 in SDM.
2741 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 is defined as MSR_UNC_CBO_4_PERFEVTSEL3 in SDM.
2744 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 0x00000740
2745 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 0x00000741
2746 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 0x00000742
2747 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 0x00000743
2752 Package. Uncore C-Box 4, performance counter n.
2754 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTRn
2755 @param EAX Lower 32-bits of MSR value.
2756 @param EDX Upper 32-bits of MSR value.
2758 <b>Example usage</b>
2762 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0);
2763 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0, Msr);
2765 @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 is defined as MSR_UNC_CBO_4_PERFCTR0 in SDM.
2766 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 is defined as MSR_UNC_CBO_4_PERFCTR1 in SDM.
2767 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 is defined as MSR_UNC_CBO_4_PERFCTR2 in SDM.
2768 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 is defined as MSR_UNC_CBO_4_PERFCTR3 in SDM.
2771 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 0x00000746
2772 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 0x00000747
2773 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 0x00000748
2774 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 0x00000749
2779 Package. MC Bank Error Configuration (R/W).
2781 @param ECX MSR_SANDY_BRIDGE_ERROR_CONTROL (0x0000017F)
2782 @param EAX Lower 32-bits of MSR value.
2783 Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.
2784 @param EDX Upper 32-bits of MSR value.
2785 Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.
2787 <b>Example usage</b>
2789 MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER Msr;
2791 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL);
2792 AsmWriteMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL, Msr.Uint64);
2794 @note MSR_SANDY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
2796 #define MSR_SANDY_BRIDGE_ERROR_CONTROL 0x0000017F
2799 MSR information returned for MSR index #MSR_SANDY_BRIDGE_ERROR_CONTROL
2803 /// Individual bit fields
2808 /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank
2809 /// to log additional info in bits 36:32.
2811 UINT32 MemErrorLogEnable
:1;
2812 UINT32 Reserved2
:30;
2813 UINT32 Reserved3
:32;
2816 /// All bit fields as a 32-bit value
2820 /// All bit fields as a 64-bit value
2823 } MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER
;
2829 @param ECX MSR_SANDY_BRIDGE_PEBS_NUM_ALT (0x0000039C)
2830 @param EAX Lower 32-bits of MSR value.
2831 Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.
2832 @param EDX Upper 32-bits of MSR value.
2833 Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.
2835 <b>Example usage</b>
2837 MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER Msr;
2839 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT);
2840 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT, Msr.Uint64);
2842 @note MSR_SANDY_BRIDGE_PEBS_NUM_ALT is defined as MSR_PEBS_NUM_ALT in SDM.
2844 #define MSR_SANDY_BRIDGE_PEBS_NUM_ALT 0x0000039C
2847 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_NUM_ALT
2851 /// Individual bit fields
2855 /// [Bit 0] ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS
2856 /// counting logic for specific events requiring additional configuration,
2857 /// see Table 19-17.
2859 UINT32 ENABLE_PEBS_NUM_ALT
:1;
2860 UINT32 Reserved1
:31;
2861 UINT32 Reserved2
:32;
2864 /// All bit fields as a 32-bit value
2868 /// All bit fields as a 64-bit value
2871 } MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER
;
2875 Package. Package RAPL Perf Status (R/O).
2877 @param ECX MSR_SANDY_BRIDGE_PKG_PERF_STATUS (0x00000613)
2878 @param EAX Lower 32-bits of MSR value.
2879 @param EDX Upper 32-bits of MSR value.
2881 <b>Example usage</b>
2885 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_PERF_STATUS);
2887 @note MSR_SANDY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
2889 #define MSR_SANDY_BRIDGE_PKG_PERF_STATUS 0x00000613
2893 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
2896 @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)
2897 @param EAX Lower 32-bits of MSR value.
2898 @param EDX Upper 32-bits of MSR value.
2900 <b>Example usage</b>
2904 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT);
2905 AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT, Msr);
2907 @note MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
2909 #define MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT 0x00000618
2913 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
2915 @param ECX MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)
2916 @param EAX Lower 32-bits of MSR value.
2917 @param EDX Upper 32-bits of MSR value.
2919 <b>Example usage</b>
2923 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS);
2925 @note MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
2927 #define MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619
2931 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
2934 @param ECX MSR_SANDY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)
2935 @param EAX Lower 32-bits of MSR value.
2936 @param EDX Upper 32-bits of MSR value.
2938 <b>Example usage</b>
2942 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_PERF_STATUS);
2944 @note MSR_SANDY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
2946 #define MSR_SANDY_BRIDGE_DRAM_PERF_STATUS 0x0000061B
2950 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
2952 @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_INFO (0x0000061C)
2953 @param EAX Lower 32-bits of MSR value.
2954 @param EDX Upper 32-bits of MSR value.
2956 <b>Example usage</b>
2960 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO);
2961 AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO, Msr);
2963 @note MSR_SANDY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
2965 #define MSR_SANDY_BRIDGE_DRAM_POWER_INFO 0x0000061C
2969 Package. Uncore U-box UCLK fixed counter control.
2971 @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL (0x00000C08)
2972 @param EAX Lower 32-bits of MSR value.
2973 @param EDX Upper 32-bits of MSR value.
2975 <b>Example usage</b>
2979 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL);
2980 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL, Msr);
2982 @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.
2984 #define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL 0x00000C08
2988 Package. Uncore U-box UCLK fixed counter.
2990 @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR (0x00000C09)
2991 @param EAX Lower 32-bits of MSR value.
2992 @param EDX Upper 32-bits of MSR value.
2994 <b>Example usage</b>
2998 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR);
2999 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR, Msr);
3001 @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.
3003 #define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR 0x00000C09
3007 Package. Uncore U-box perfmon event select for U-box counter 0.
3009 @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 (0x00000C10)
3010 @param EAX Lower 32-bits of MSR value.
3011 @param EDX Upper 32-bits of MSR value.
3013 <b>Example usage</b>
3017 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0);
3018 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0, Msr);
3020 @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.
3022 #define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 0x00000C10
3026 Package. Uncore U-box perfmon event select for U-box counter 1.
3028 @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 (0x00000C11)
3029 @param EAX Lower 32-bits of MSR value.
3030 @param EDX Upper 32-bits of MSR value.
3032 <b>Example usage</b>
3036 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1);
3037 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1, Msr);
3039 @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.
3041 #define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 0x00000C11
3045 Package. Uncore U-box perfmon counter 0.
3047 @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR0 (0x00000C16)
3048 @param EAX Lower 32-bits of MSR value.
3049 @param EDX Upper 32-bits of MSR value.
3051 <b>Example usage</b>
3055 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0);
3056 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0, Msr);
3058 @note MSR_SANDY_BRIDGE_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.
3060 #define MSR_SANDY_BRIDGE_U_PMON_CTR0 0x00000C16
3064 Package. Uncore U-box perfmon counter 1.
3066 @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR1 (0x00000C17)
3067 @param EAX Lower 32-bits of MSR value.
3068 @param EDX Upper 32-bits of MSR value.
3070 <b>Example usage</b>
3074 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1);
3075 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1, Msr);
3077 @note MSR_SANDY_BRIDGE_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.
3079 #define MSR_SANDY_BRIDGE_U_PMON_CTR1 0x00000C17
3083 Package. Uncore PCU perfmon for PCU-box-wide control.
3085 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL (0x00000C24)
3086 @param EAX Lower 32-bits of MSR value.
3087 @param EDX Upper 32-bits of MSR value.
3089 <b>Example usage</b>
3093 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL);
3094 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL, Msr);
3096 @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.
3098 #define MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL 0x00000C24
3102 Package. Uncore PCU perfmon event select for PCU counter 0.
3104 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 (0x00000C30)
3105 @param EAX Lower 32-bits of MSR value.
3106 @param EDX Upper 32-bits of MSR value.
3108 <b>Example usage</b>
3112 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0);
3113 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0, Msr);
3115 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.
3117 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 0x00000C30
3121 Package. Uncore PCU perfmon event select for PCU counter 1.
3123 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 (0x00000C31)
3124 @param EAX Lower 32-bits of MSR value.
3125 @param EDX Upper 32-bits of MSR value.
3127 <b>Example usage</b>
3131 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1);
3132 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1, Msr);
3134 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.
3136 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 0x00000C31
3140 Package. Uncore PCU perfmon event select for PCU counter 2.
3142 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 (0x00000C32)
3143 @param EAX Lower 32-bits of MSR value.
3144 @param EDX Upper 32-bits of MSR value.
3146 <b>Example usage</b>
3150 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2);
3151 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2, Msr);
3153 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.
3155 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 0x00000C32
3159 Package. Uncore PCU perfmon event select for PCU counter 3.
3161 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 (0x00000C33)
3162 @param EAX Lower 32-bits of MSR value.
3163 @param EDX Upper 32-bits of MSR value.
3165 <b>Example usage</b>
3169 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3);
3170 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3, Msr);
3172 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.
3174 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 0x00000C33
3178 Package. Uncore PCU perfmon box-wide filter.
3180 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER (0x00000C34)
3181 @param EAX Lower 32-bits of MSR value.
3182 @param EDX Upper 32-bits of MSR value.
3184 <b>Example usage</b>
3188 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER);
3189 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER, Msr);
3191 @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.
3193 #define MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER 0x00000C34
3197 Package. Uncore PCU perfmon counter 0.
3199 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR0 (0x00000C36)
3200 @param EAX Lower 32-bits of MSR value.
3201 @param EDX Upper 32-bits of MSR value.
3203 <b>Example usage</b>
3207 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0);
3208 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0, Msr);
3210 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.
3212 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR0 0x00000C36
3216 Package. Uncore PCU perfmon counter 1.
3218 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR1 (0x00000C37)
3219 @param EAX Lower 32-bits of MSR value.
3220 @param EDX Upper 32-bits of MSR value.
3222 <b>Example usage</b>
3226 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1);
3227 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1, Msr);
3229 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.
3231 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR1 0x00000C37
3235 Package. Uncore PCU perfmon counter 2.
3237 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR2 (0x00000C38)
3238 @param EAX Lower 32-bits of MSR value.
3239 @param EDX Upper 32-bits of MSR value.
3241 <b>Example usage</b>
3245 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2);
3246 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2, Msr);
3248 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.
3250 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR2 0x00000C38
3254 Package. Uncore PCU perfmon counter 3.
3256 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR3 (0x00000C39)
3257 @param EAX Lower 32-bits of MSR value.
3258 @param EDX Upper 32-bits of MSR value.
3260 <b>Example usage</b>
3264 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3);
3265 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3, Msr);
3267 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.
3269 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR3 0x00000C39
3273 Package. Uncore C-box 0 perfmon local box wide control.
3275 @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL (0x00000D04)
3276 @param EAX Lower 32-bits of MSR value.
3277 @param EDX Upper 32-bits of MSR value.
3279 <b>Example usage</b>
3283 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL);
3284 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL, Msr);
3286 @note MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.
3288 #define MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL 0x00000D04
3292 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.
3294 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 (0x00000D10)
3295 @param EAX Lower 32-bits of MSR value.
3296 @param EDX Upper 32-bits of MSR value.
3298 <b>Example usage</b>
3302 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0);
3303 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0, Msr);
3305 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.
3307 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 0x00000D10
3311 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.
3313 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 (0x00000D11)
3314 @param EAX Lower 32-bits of MSR value.
3315 @param EDX Upper 32-bits of MSR value.
3317 <b>Example usage</b>
3321 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1);
3322 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1, Msr);
3324 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.
3326 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 0x00000D11
3330 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.
3332 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 (0x00000D12)
3333 @param EAX Lower 32-bits of MSR value.
3334 @param EDX Upper 32-bits of MSR value.
3336 <b>Example usage</b>
3340 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2);
3341 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2, Msr);
3343 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.
3345 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 0x00000D12
3349 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.
3351 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 (0x00000D13)
3352 @param EAX Lower 32-bits of MSR value.
3353 @param EDX Upper 32-bits of MSR value.
3355 <b>Example usage</b>
3359 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3);
3360 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3, Msr);
3362 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.
3364 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 0x00000D13
3368 Package. Uncore C-box 0 perfmon box wide filter.
3370 @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER (0x00000D14)
3371 @param EAX Lower 32-bits of MSR value.
3372 @param EDX Upper 32-bits of MSR value.
3374 <b>Example usage</b>
3378 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER);
3379 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER, Msr);
3381 @note MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER is defined as MSR_C0_PMON_BOX_FILTER in SDM.
3383 #define MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER 0x00000D14
3387 Package. Uncore C-box 0 perfmon counter 0.
3389 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR0 (0x00000D16)
3390 @param EAX Lower 32-bits of MSR value.
3391 @param EDX Upper 32-bits of MSR value.
3393 <b>Example usage</b>
3397 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0);
3398 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0, Msr);
3400 @note MSR_SANDY_BRIDGE_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
3402 #define MSR_SANDY_BRIDGE_C0_PMON_CTR0 0x00000D16
3406 Package. Uncore C-box 0 perfmon counter 1.
3408 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR1 (0x00000D17)
3409 @param EAX Lower 32-bits of MSR value.
3410 @param EDX Upper 32-bits of MSR value.
3412 <b>Example usage</b>
3416 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1);
3417 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1, Msr);
3419 @note MSR_SANDY_BRIDGE_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
3421 #define MSR_SANDY_BRIDGE_C0_PMON_CTR1 0x00000D17
3425 Package. Uncore C-box 0 perfmon counter 2.
3427 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR2 (0x00000D18)
3428 @param EAX Lower 32-bits of MSR value.
3429 @param EDX Upper 32-bits of MSR value.
3431 <b>Example usage</b>
3435 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2);
3436 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2, Msr);
3438 @note MSR_SANDY_BRIDGE_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
3440 #define MSR_SANDY_BRIDGE_C0_PMON_CTR2 0x00000D18
3444 Package. Uncore C-box 0 perfmon counter 3.
3446 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR3 (0x00000D19)
3447 @param EAX Lower 32-bits of MSR value.
3448 @param EDX Upper 32-bits of MSR value.
3450 <b>Example usage</b>
3454 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3);
3455 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3, Msr);
3457 @note MSR_SANDY_BRIDGE_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
3459 #define MSR_SANDY_BRIDGE_C0_PMON_CTR3 0x00000D19
3463 Package. Uncore C-box 1 perfmon local box wide control.
3465 @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL (0x00000D24)
3466 @param EAX Lower 32-bits of MSR value.
3467 @param EDX Upper 32-bits of MSR value.
3469 <b>Example usage</b>
3473 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL);
3474 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL, Msr);
3476 @note MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.
3478 #define MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL 0x00000D24
3482 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.
3484 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 (0x00000D30)
3485 @param EAX Lower 32-bits of MSR value.
3486 @param EDX Upper 32-bits of MSR value.
3488 <b>Example usage</b>
3492 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0);
3493 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0, Msr);
3495 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.
3497 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 0x00000D30
3501 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.
3503 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 (0x00000D31)
3504 @param EAX Lower 32-bits of MSR value.
3505 @param EDX Upper 32-bits of MSR value.
3507 <b>Example usage</b>
3511 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1);
3512 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1, Msr);
3514 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.
3516 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 0x00000D31
3520 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.
3522 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 (0x00000D32)
3523 @param EAX Lower 32-bits of MSR value.
3524 @param EDX Upper 32-bits of MSR value.
3526 <b>Example usage</b>
3530 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2);
3531 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2, Msr);
3533 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.
3535 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 0x00000D32
3539 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.
3541 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 (0x00000D33)
3542 @param EAX Lower 32-bits of MSR value.
3543 @param EDX Upper 32-bits of MSR value.
3545 <b>Example usage</b>
3549 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3);
3550 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3, Msr);
3552 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.
3554 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 0x00000D33
3558 Package. Uncore C-box 1 perfmon box wide filter.
3560 @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER (0x00000D34)
3561 @param EAX Lower 32-bits of MSR value.
3562 @param EDX Upper 32-bits of MSR value.
3564 <b>Example usage</b>
3568 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER);
3569 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER, Msr);
3571 @note MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER is defined as MSR_C1_PMON_BOX_FILTER in SDM.
3573 #define MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER 0x00000D34
3577 Package. Uncore C-box 1 perfmon counter 0.
3579 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR0 (0x00000D36)
3580 @param EAX Lower 32-bits of MSR value.
3581 @param EDX Upper 32-bits of MSR value.
3583 <b>Example usage</b>
3587 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0);
3588 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0, Msr);
3590 @note MSR_SANDY_BRIDGE_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
3592 #define MSR_SANDY_BRIDGE_C1_PMON_CTR0 0x00000D36
3596 Package. Uncore C-box 1 perfmon counter 1.
3598 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR1 (0x00000D37)
3599 @param EAX Lower 32-bits of MSR value.
3600 @param EDX Upper 32-bits of MSR value.
3602 <b>Example usage</b>
3606 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1);
3607 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1, Msr);
3609 @note MSR_SANDY_BRIDGE_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
3611 #define MSR_SANDY_BRIDGE_C1_PMON_CTR1 0x00000D37
3615 Package. Uncore C-box 1 perfmon counter 2.
3617 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR2 (0x00000D38)
3618 @param EAX Lower 32-bits of MSR value.
3619 @param EDX Upper 32-bits of MSR value.
3621 <b>Example usage</b>
3625 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2);
3626 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2, Msr);
3628 @note MSR_SANDY_BRIDGE_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
3630 #define MSR_SANDY_BRIDGE_C1_PMON_CTR2 0x00000D38
3634 Package. Uncore C-box 1 perfmon counter 3.
3636 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR3 (0x00000D39)
3637 @param EAX Lower 32-bits of MSR value.
3638 @param EDX Upper 32-bits of MSR value.
3640 <b>Example usage</b>
3644 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3);
3645 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3, Msr);
3647 @note MSR_SANDY_BRIDGE_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
3649 #define MSR_SANDY_BRIDGE_C1_PMON_CTR3 0x00000D39
3653 Package. Uncore C-box 2 perfmon local box wide control.
3655 @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL (0x00000D44)
3656 @param EAX Lower 32-bits of MSR value.
3657 @param EDX Upper 32-bits of MSR value.
3659 <b>Example usage</b>
3663 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL);
3664 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL, Msr);
3666 @note MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.
3668 #define MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL 0x00000D44
3672 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.
3674 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 (0x00000D50)
3675 @param EAX Lower 32-bits of MSR value.
3676 @param EDX Upper 32-bits of MSR value.
3678 <b>Example usage</b>
3682 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0);
3683 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0, Msr);
3685 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.
3687 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 0x00000D50
3691 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.
3693 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 (0x00000D51)
3694 @param EAX Lower 32-bits of MSR value.
3695 @param EDX Upper 32-bits of MSR value.
3697 <b>Example usage</b>
3701 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1);
3702 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1, Msr);
3704 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.
3706 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 0x00000D51
3710 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.
3712 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 (0x00000D52)
3713 @param EAX Lower 32-bits of MSR value.
3714 @param EDX Upper 32-bits of MSR value.
3716 <b>Example usage</b>
3720 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2);
3721 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2, Msr);
3723 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.
3725 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 0x00000D52
3729 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.
3731 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 (0x00000D53)
3732 @param EAX Lower 32-bits of MSR value.
3733 @param EDX Upper 32-bits of MSR value.
3735 <b>Example usage</b>
3739 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3);
3740 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3, Msr);
3742 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.
3744 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 0x00000D53
3748 Package. Uncore C-box 2 perfmon box wide filter.
3750 @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER (0x00000D54)
3751 @param EAX Lower 32-bits of MSR value.
3752 @param EDX Upper 32-bits of MSR value.
3754 <b>Example usage</b>
3758 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER);
3759 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER, Msr);
3761 @note MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER is defined as MSR_C2_PMON_BOX_FILTER in SDM.
3763 #define MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER 0x00000D54
3767 Package. Uncore C-box 2 perfmon counter 0.
3769 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR0 (0x00000D56)
3770 @param EAX Lower 32-bits of MSR value.
3771 @param EDX Upper 32-bits of MSR value.
3773 <b>Example usage</b>
3777 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0);
3778 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0, Msr);
3780 @note MSR_SANDY_BRIDGE_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
3782 #define MSR_SANDY_BRIDGE_C2_PMON_CTR0 0x00000D56
3786 Package. Uncore C-box 2 perfmon counter 1.
3788 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR1 (0x00000D57)
3789 @param EAX Lower 32-bits of MSR value.
3790 @param EDX Upper 32-bits of MSR value.
3792 <b>Example usage</b>
3796 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1);
3797 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1, Msr);
3799 @note MSR_SANDY_BRIDGE_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
3801 #define MSR_SANDY_BRIDGE_C2_PMON_CTR1 0x00000D57
3805 Package. Uncore C-box 2 perfmon counter 2.
3807 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR2 (0x00000D58)
3808 @param EAX Lower 32-bits of MSR value.
3809 @param EDX Upper 32-bits of MSR value.
3811 <b>Example usage</b>
3815 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2);
3816 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2, Msr);
3818 @note MSR_SANDY_BRIDGE_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
3820 #define MSR_SANDY_BRIDGE_C2_PMON_CTR2 0x00000D58
3824 Package. Uncore C-box 2 perfmon counter 3.
3826 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR3 (0x00000D59)
3827 @param EAX Lower 32-bits of MSR value.
3828 @param EDX Upper 32-bits of MSR value.
3830 <b>Example usage</b>
3834 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3);
3835 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3, Msr);
3837 @note MSR_SANDY_BRIDGE_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
3839 #define MSR_SANDY_BRIDGE_C2_PMON_CTR3 0x00000D59
3843 Package. Uncore C-box 3 perfmon local box wide control.
3845 @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL (0x00000D64)
3846 @param EAX Lower 32-bits of MSR value.
3847 @param EDX Upper 32-bits of MSR value.
3849 <b>Example usage</b>
3853 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL);
3854 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL, Msr);
3856 @note MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.
3858 #define MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL 0x00000D64
3862 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.
3864 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 (0x00000D70)
3865 @param EAX Lower 32-bits of MSR value.
3866 @param EDX Upper 32-bits of MSR value.
3868 <b>Example usage</b>
3872 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0);
3873 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0, Msr);
3875 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.
3877 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 0x00000D70
3881 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.
3883 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 (0x00000D71)
3884 @param EAX Lower 32-bits of MSR value.
3885 @param EDX Upper 32-bits of MSR value.
3887 <b>Example usage</b>
3891 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1);
3892 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1, Msr);
3894 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.
3896 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 0x00000D71
3900 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.
3902 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 (0x00000D72)
3903 @param EAX Lower 32-bits of MSR value.
3904 @param EDX Upper 32-bits of MSR value.
3906 <b>Example usage</b>
3910 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2);
3911 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2, Msr);
3913 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.
3915 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 0x00000D72
3919 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.
3921 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 (0x00000D73)
3922 @param EAX Lower 32-bits of MSR value.
3923 @param EDX Upper 32-bits of MSR value.
3925 <b>Example usage</b>
3929 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3);
3930 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3, Msr);
3932 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.
3934 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 0x00000D73
3938 Package. Uncore C-box 3 perfmon box wide filter.
3940 @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER (0x00000D74)
3941 @param EAX Lower 32-bits of MSR value.
3942 @param EDX Upper 32-bits of MSR value.
3944 <b>Example usage</b>
3948 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER);
3949 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER, Msr);
3951 @note MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER is defined as MSR_C3_PMON_BOX_FILTER in SDM.
3953 #define MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER 0x00000D74
3957 Package. Uncore C-box 3 perfmon counter 0.
3959 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR0 (0x00000D76)
3960 @param EAX Lower 32-bits of MSR value.
3961 @param EDX Upper 32-bits of MSR value.
3963 <b>Example usage</b>
3967 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0);
3968 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0, Msr);
3970 @note MSR_SANDY_BRIDGE_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
3972 #define MSR_SANDY_BRIDGE_C3_PMON_CTR0 0x00000D76
3976 Package. Uncore C-box 3 perfmon counter 1.
3978 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR1 (0x00000D77)
3979 @param EAX Lower 32-bits of MSR value.
3980 @param EDX Upper 32-bits of MSR value.
3982 <b>Example usage</b>
3986 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1);
3987 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1, Msr);
3989 @note MSR_SANDY_BRIDGE_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
3991 #define MSR_SANDY_BRIDGE_C3_PMON_CTR1 0x00000D77
3995 Package. Uncore C-box 3 perfmon counter 2.
3997 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR2 (0x00000D78)
3998 @param EAX Lower 32-bits of MSR value.
3999 @param EDX Upper 32-bits of MSR value.
4001 <b>Example usage</b>
4005 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2);
4006 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2, Msr);
4008 @note MSR_SANDY_BRIDGE_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
4010 #define MSR_SANDY_BRIDGE_C3_PMON_CTR2 0x00000D78
4014 Package. Uncore C-box 3 perfmon counter 3.
4016 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR3 (0x00000D79)
4017 @param EAX Lower 32-bits of MSR value.
4018 @param EDX Upper 32-bits of MSR value.
4020 <b>Example usage</b>
4024 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3);
4025 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3, Msr);
4027 @note MSR_SANDY_BRIDGE_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
4029 #define MSR_SANDY_BRIDGE_C3_PMON_CTR3 0x00000D79
4033 Package. Uncore C-box 4 perfmon local box wide control.
4035 @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL (0x00000D84)
4036 @param EAX Lower 32-bits of MSR value.
4037 @param EDX Upper 32-bits of MSR value.
4039 <b>Example usage</b>
4043 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL);
4044 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL, Msr);
4046 @note MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.
4048 #define MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL 0x00000D84
4052 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.
4054 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 (0x00000D90)
4055 @param EAX Lower 32-bits of MSR value.
4056 @param EDX Upper 32-bits of MSR value.
4058 <b>Example usage</b>
4062 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0);
4063 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0, Msr);
4065 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.
4067 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 0x00000D90
4071 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.
4073 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 (0x00000D91)
4074 @param EAX Lower 32-bits of MSR value.
4075 @param EDX Upper 32-bits of MSR value.
4077 <b>Example usage</b>
4081 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1);
4082 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1, Msr);
4084 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.
4086 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 0x00000D91
4090 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.
4092 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 (0x00000D92)
4093 @param EAX Lower 32-bits of MSR value.
4094 @param EDX Upper 32-bits of MSR value.
4096 <b>Example usage</b>
4100 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2);
4101 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2, Msr);
4103 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.
4105 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 0x00000D92
4109 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.
4111 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 (0x00000D93)
4112 @param EAX Lower 32-bits of MSR value.
4113 @param EDX Upper 32-bits of MSR value.
4115 <b>Example usage</b>
4119 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3);
4120 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3, Msr);
4122 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.
4124 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 0x00000D93
4128 Package. Uncore C-box 4 perfmon box wide filter.
4130 @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER (0x00000D94)
4131 @param EAX Lower 32-bits of MSR value.
4132 @param EDX Upper 32-bits of MSR value.
4134 <b>Example usage</b>
4138 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER);
4139 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER, Msr);
4141 @note MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER is defined as MSR_C4_PMON_BOX_FILTER in SDM.
4143 #define MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER 0x00000D94
4147 Package. Uncore C-box 4 perfmon counter 0.
4149 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR0 (0x00000D96)
4150 @param EAX Lower 32-bits of MSR value.
4151 @param EDX Upper 32-bits of MSR value.
4153 <b>Example usage</b>
4157 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0);
4158 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0, Msr);
4160 @note MSR_SANDY_BRIDGE_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
4162 #define MSR_SANDY_BRIDGE_C4_PMON_CTR0 0x00000D96
4166 Package. Uncore C-box 4 perfmon counter 1.
4168 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR1 (0x00000D97)
4169 @param EAX Lower 32-bits of MSR value.
4170 @param EDX Upper 32-bits of MSR value.
4172 <b>Example usage</b>
4176 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1);
4177 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1, Msr);
4179 @note MSR_SANDY_BRIDGE_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
4181 #define MSR_SANDY_BRIDGE_C4_PMON_CTR1 0x00000D97
4185 Package. Uncore C-box 4 perfmon counter 2.
4187 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR2 (0x00000D98)
4188 @param EAX Lower 32-bits of MSR value.
4189 @param EDX Upper 32-bits of MSR value.
4191 <b>Example usage</b>
4195 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2);
4196 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2, Msr);
4198 @note MSR_SANDY_BRIDGE_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
4200 #define MSR_SANDY_BRIDGE_C4_PMON_CTR2 0x00000D98
4204 Package. Uncore C-box 4 perfmon counter 3.
4206 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR3 (0x00000D99)
4207 @param EAX Lower 32-bits of MSR value.
4208 @param EDX Upper 32-bits of MSR value.
4210 <b>Example usage</b>
4214 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3);
4215 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3, Msr);
4217 @note MSR_SANDY_BRIDGE_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
4219 #define MSR_SANDY_BRIDGE_C4_PMON_CTR3 0x00000D99
4223 Package. Uncore C-box 5 perfmon local box wide control.
4225 @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL (0x00000DA4)
4226 @param EAX Lower 32-bits of MSR value.
4227 @param EDX Upper 32-bits of MSR value.
4229 <b>Example usage</b>
4233 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL);
4234 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL, Msr);
4236 @note MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.
4238 #define MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL 0x00000DA4
4242 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.
4244 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 (0x00000DB0)
4245 @param EAX Lower 32-bits of MSR value.
4246 @param EDX Upper 32-bits of MSR value.
4248 <b>Example usage</b>
4252 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0);
4253 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0, Msr);
4255 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.
4257 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 0x00000DB0
4261 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.
4263 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 (0x00000DB1)
4264 @param EAX Lower 32-bits of MSR value.
4265 @param EDX Upper 32-bits of MSR value.
4267 <b>Example usage</b>
4271 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1);
4272 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1, Msr);
4274 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.
4276 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 0x00000DB1
4280 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.
4282 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 (0x00000DB2)
4283 @param EAX Lower 32-bits of MSR value.
4284 @param EDX Upper 32-bits of MSR value.
4286 <b>Example usage</b>
4290 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2);
4291 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2, Msr);
4293 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.
4295 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 0x00000DB2
4299 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.
4301 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 (0x00000DB3)
4302 @param EAX Lower 32-bits of MSR value.
4303 @param EDX Upper 32-bits of MSR value.
4305 <b>Example usage</b>
4309 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3);
4310 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3, Msr);
4312 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.
4314 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 0x00000DB3
4318 Package. Uncore C-box 5 perfmon box wide filter.
4320 @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER (0x00000DB4)
4321 @param EAX Lower 32-bits of MSR value.
4322 @param EDX Upper 32-bits of MSR value.
4324 <b>Example usage</b>
4328 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER);
4329 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER, Msr);
4331 @note MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER is defined as MSR_C5_PMON_BOX_FILTER in SDM.
4333 #define MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER 0x00000DB4
4337 Package. Uncore C-box 5 perfmon counter 0.
4339 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR0 (0x00000DB6)
4340 @param EAX Lower 32-bits of MSR value.
4341 @param EDX Upper 32-bits of MSR value.
4343 <b>Example usage</b>
4347 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0);
4348 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0, Msr);
4350 @note MSR_SANDY_BRIDGE_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
4352 #define MSR_SANDY_BRIDGE_C5_PMON_CTR0 0x00000DB6
4356 Package. Uncore C-box 5 perfmon counter 1.
4358 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR1 (0x00000DB7)
4359 @param EAX Lower 32-bits of MSR value.
4360 @param EDX Upper 32-bits of MSR value.
4362 <b>Example usage</b>
4366 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1);
4367 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1, Msr);
4369 @note MSR_SANDY_BRIDGE_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
4371 #define MSR_SANDY_BRIDGE_C5_PMON_CTR1 0x00000DB7
4375 Package. Uncore C-box 5 perfmon counter 2.
4377 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR2 (0x00000DB8)
4378 @param EAX Lower 32-bits of MSR value.
4379 @param EDX Upper 32-bits of MSR value.
4381 <b>Example usage</b>
4385 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2);
4386 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2, Msr);
4388 @note MSR_SANDY_BRIDGE_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
4390 #define MSR_SANDY_BRIDGE_C5_PMON_CTR2 0x00000DB8
4394 Package. Uncore C-box 5 perfmon counter 3.
4396 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR3 (0x00000DB9)
4397 @param EAX Lower 32-bits of MSR value.
4398 @param EDX Upper 32-bits of MSR value.
4400 <b>Example usage</b>
4404 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3);
4405 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3, Msr);
4407 @note MSR_SANDY_BRIDGE_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
4409 #define MSR_SANDY_BRIDGE_C5_PMON_CTR3 0x00000DB9
4413 Package. Uncore C-box 6 perfmon local box wide control.
4415 @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL (0x00000DC4)
4416 @param EAX Lower 32-bits of MSR value.
4417 @param EDX Upper 32-bits of MSR value.
4419 <b>Example usage</b>
4423 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL);
4424 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL, Msr);
4426 @note MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.
4428 #define MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL 0x00000DC4
4432 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.
4434 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 (0x00000DD0)
4435 @param EAX Lower 32-bits of MSR value.
4436 @param EDX Upper 32-bits of MSR value.
4438 <b>Example usage</b>
4442 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0);
4443 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0, Msr);
4445 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.
4447 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 0x00000DD0
4451 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.
4453 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 (0x00000DD1)
4454 @param EAX Lower 32-bits of MSR value.
4455 @param EDX Upper 32-bits of MSR value.
4457 <b>Example usage</b>
4461 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1);
4462 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1, Msr);
4464 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.
4466 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 0x00000DD1
4470 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.
4472 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 (0x00000DD2)
4473 @param EAX Lower 32-bits of MSR value.
4474 @param EDX Upper 32-bits of MSR value.
4476 <b>Example usage</b>
4480 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2);
4481 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2, Msr);
4483 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.
4485 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 0x00000DD2
4489 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.
4491 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 (0x00000DD3)
4492 @param EAX Lower 32-bits of MSR value.
4493 @param EDX Upper 32-bits of MSR value.
4495 <b>Example usage</b>
4499 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3);
4500 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3, Msr);
4502 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.
4504 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 0x00000DD3
4508 Package. Uncore C-box 6 perfmon box wide filter.
4510 @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER (0x00000DD4)
4511 @param EAX Lower 32-bits of MSR value.
4512 @param EDX Upper 32-bits of MSR value.
4514 <b>Example usage</b>
4518 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER);
4519 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER, Msr);
4521 @note MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER is defined as MSR_C6_PMON_BOX_FILTER in SDM.
4523 #define MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER 0x00000DD4
4527 Package. Uncore C-box 6 perfmon counter 0.
4529 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR0 (0x00000DD6)
4530 @param EAX Lower 32-bits of MSR value.
4531 @param EDX Upper 32-bits of MSR value.
4533 <b>Example usage</b>
4537 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0);
4538 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0, Msr);
4540 @note MSR_SANDY_BRIDGE_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
4542 #define MSR_SANDY_BRIDGE_C6_PMON_CTR0 0x00000DD6
4546 Package. Uncore C-box 6 perfmon counter 1.
4548 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR1 (0x00000DD7)
4549 @param EAX Lower 32-bits of MSR value.
4550 @param EDX Upper 32-bits of MSR value.
4552 <b>Example usage</b>
4556 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1);
4557 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1, Msr);
4559 @note MSR_SANDY_BRIDGE_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
4561 #define MSR_SANDY_BRIDGE_C6_PMON_CTR1 0x00000DD7
4565 Package. Uncore C-box 6 perfmon counter 2.
4567 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR2 (0x00000DD8)
4568 @param EAX Lower 32-bits of MSR value.
4569 @param EDX Upper 32-bits of MSR value.
4571 <b>Example usage</b>
4575 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2);
4576 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2, Msr);
4578 @note MSR_SANDY_BRIDGE_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
4580 #define MSR_SANDY_BRIDGE_C6_PMON_CTR2 0x00000DD8
4584 Package. Uncore C-box 6 perfmon counter 3.
4586 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR3 (0x00000DD9)
4587 @param EAX Lower 32-bits of MSR value.
4588 @param EDX Upper 32-bits of MSR value.
4590 <b>Example usage</b>
4594 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3);
4595 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3, Msr);
4597 @note MSR_SANDY_BRIDGE_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
4599 #define MSR_SANDY_BRIDGE_C6_PMON_CTR3 0x00000DD9
4603 Package. Uncore C-box 7 perfmon local box wide control.
4605 @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL (0x00000DE4)
4606 @param EAX Lower 32-bits of MSR value.
4607 @param EDX Upper 32-bits of MSR value.
4609 <b>Example usage</b>
4613 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL);
4614 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL, Msr);
4616 @note MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.
4618 #define MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL 0x00000DE4
4622 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.
4624 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 (0x00000DF0)
4625 @param EAX Lower 32-bits of MSR value.
4626 @param EDX Upper 32-bits of MSR value.
4628 <b>Example usage</b>
4632 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0);
4633 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0, Msr);
4635 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.
4637 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 0x00000DF0
4641 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.
4643 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 (0x00000DF1)
4644 @param EAX Lower 32-bits of MSR value.
4645 @param EDX Upper 32-bits of MSR value.
4647 <b>Example usage</b>
4651 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1);
4652 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1, Msr);
4654 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.
4656 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 0x00000DF1
4660 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.
4662 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 (0x00000DF2)
4663 @param EAX Lower 32-bits of MSR value.
4664 @param EDX Upper 32-bits of MSR value.
4666 <b>Example usage</b>
4670 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2);
4671 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2, Msr);
4673 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.
4675 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 0x00000DF2
4679 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.
4681 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 (0x00000DF3)
4682 @param EAX Lower 32-bits of MSR value.
4683 @param EDX Upper 32-bits of MSR value.
4685 <b>Example usage</b>
4689 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3);
4690 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3, Msr);
4692 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.
4694 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 0x00000DF3
4698 Package. Uncore C-box 7 perfmon box wide filter.
4700 @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER (0x00000DF4)
4701 @param EAX Lower 32-bits of MSR value.
4702 @param EDX Upper 32-bits of MSR value.
4704 <b>Example usage</b>
4708 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER);
4709 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER, Msr);
4711 @note MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER is defined as MSR_C7_PMON_BOX_FILTER in SDM.
4713 #define MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER 0x00000DF4
4717 Package. Uncore C-box 7 perfmon counter 0.
4719 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR0 (0x00000DF6)
4720 @param EAX Lower 32-bits of MSR value.
4721 @param EDX Upper 32-bits of MSR value.
4723 <b>Example usage</b>
4727 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0);
4728 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0, Msr);
4730 @note MSR_SANDY_BRIDGE_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
4732 #define MSR_SANDY_BRIDGE_C7_PMON_CTR0 0x00000DF6
4736 Package. Uncore C-box 7 perfmon counter 1.
4738 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR1 (0x00000DF7)
4739 @param EAX Lower 32-bits of MSR value.
4740 @param EDX Upper 32-bits of MSR value.
4742 <b>Example usage</b>
4746 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1);
4747 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1, Msr);
4749 @note MSR_SANDY_BRIDGE_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
4751 #define MSR_SANDY_BRIDGE_C7_PMON_CTR1 0x00000DF7
4755 Package. Uncore C-box 7 perfmon counter 2.
4757 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR2 (0x00000DF8)
4758 @param EAX Lower 32-bits of MSR value.
4759 @param EDX Upper 32-bits of MSR value.
4761 <b>Example usage</b>
4765 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2);
4766 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2, Msr);
4768 @note MSR_SANDY_BRIDGE_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
4770 #define MSR_SANDY_BRIDGE_C7_PMON_CTR2 0x00000DF8
4774 Package. Uncore C-box 7 perfmon counter 3.
4776 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR3 (0x00000DF9)
4777 @param EAX Lower 32-bits of MSR value.
4778 @param EDX Upper 32-bits of MSR value.
4780 <b>Example usage</b>
4784 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3);
4785 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3, Msr);
4787 @note MSR_SANDY_BRIDGE_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
4789 #define MSR_SANDY_BRIDGE_C7_PMON_CTR3 0x00000DF9