2 MSR Definitions for Intel processors based on the Sandy Bridge microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
20 May 2018, Volume 4: Model-Specific-Registers (MSR)
24 #ifndef __SANDY_BRIDGE_MSR_H__
25 #define __SANDY_BRIDGE_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Is Intel processors based on the Sandy Bridge microarchitecture?
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
38 #define IS_SANDY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
41 DisplayModel == 0x2A || \
42 DisplayModel == 0x2D \
47 Thread. SMI Counter (R/O).
49 @param ECX MSR_SANDY_BRIDGE_SMI_COUNT (0x00000034)
50 @param EAX Lower 32-bits of MSR value.
51 Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.
52 @param EDX Upper 32-bits of MSR value.
53 Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.
57 MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER Msr;
59 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_SMI_COUNT);
61 @note MSR_SANDY_BRIDGE_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
63 #define MSR_SANDY_BRIDGE_SMI_COUNT 0x00000034
66 MSR information returned for MSR index #MSR_SANDY_BRIDGE_SMI_COUNT
70 /// Individual bit fields
74 /// [Bits 31:0] SMI Count (R/O) Count SMIs.
80 /// All bit fields as a 32-bit value
84 /// All bit fields as a 64-bit value
87 } MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER
;
91 Package. Platform Information Contains power management and other model
92 specific features enumeration. See http://biosbits.org.
94 @param ECX MSR_SANDY_BRIDGE_PLATFORM_INFO (0x000000CE)
95 @param EAX Lower 32-bits of MSR value.
96 Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.
97 @param EDX Upper 32-bits of MSR value.
98 Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.
102 MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER Msr;
104 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO);
105 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
107 @note MSR_SANDY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
109 #define MSR_SANDY_BRIDGE_PLATFORM_INFO 0x000000CE
112 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PLATFORM_INFO
116 /// Individual bit fields
121 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
122 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
125 UINT32 MaximumNonTurboRatio
:8;
128 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
129 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
130 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
131 /// Turbo mode is disabled.
135 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
136 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
137 /// and when set to 0, indicates TDP Limit for Turbo mode is not
144 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
145 /// minimum ratio (maximum efficiency) that the processor can operates, in
148 UINT32 MaximumEfficiencyRatio
:8;
152 /// All bit fields as a 64-bit value
155 } MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER
;
159 Core. C-State Configuration Control (R/W) Note: C-state values are
160 processor specific C-state code names, unrelated to MWAIT extension C-state
161 parameters or ACPI CStates. See http://biosbits.org.
163 @param ECX MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)
164 @param EAX Lower 32-bits of MSR value.
165 Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
166 @param EDX Upper 32-bits of MSR value.
167 Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
171 MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
173 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL);
174 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
176 @note MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
178 #define MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2
181 MSR information returned for MSR index
182 #MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL
186 /// Individual bit fields
190 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
191 /// processor-specific C-state code name (consuming the least power). for
192 /// the package. The default is set as factory-configured package C-state
193 /// limit. The following C-state code name encodings are supported: 000b:
194 /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:
195 /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:
196 /// This field cannot be used to limit package C-state to C3.
201 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
202 /// IO_read instructions sent to IO register specified by
203 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
208 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
209 /// until next reset.
214 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor
215 /// will conditionally demote C6/C7 requests to C3 based on uncore
216 /// auto-demote information.
218 UINT32 C3AutoDemotion
:1;
220 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor
221 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
222 /// auto-demote information.
224 UINT32 C1AutoDemotion
:1;
226 /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from
229 UINT32 C3Undemotion
:1;
231 /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from
234 UINT32 C1Undemotion
:1;
239 /// All bit fields as a 32-bit value
243 /// All bit fields as a 64-bit value
246 } MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER
;
250 Core. Power Management IO Redirection in C-state (R/W) See
253 @param ECX MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE (0x000000E4)
254 @param EAX Lower 32-bits of MSR value.
255 Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.
256 @param EDX Upper 32-bits of MSR value.
257 Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.
261 MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER Msr;
263 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE);
264 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE, Msr.Uint64);
266 @note MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
268 #define MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE 0x000000E4
271 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE
275 /// Individual bit fields
279 /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address
280 /// visible to software for IO redirection. If IO MWAIT Redirection is
281 /// enabled, reads to this address will be consumed by the power
282 /// management logic and decoded to MWAIT instructions. When IO port
283 /// address redirection is enabled, this is the IO port address reported
284 /// to the OS/software.
288 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
289 /// maximum C-State code name to be included when IO read to MWAIT
290 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3
291 /// is the max C-State to include 001b - C6 is the max C-State to include
292 /// 010b - C7 is the max C-State to include.
294 UINT32 CStateRange
:3;
299 /// All bit fields as a 32-bit value
303 /// All bit fields as a 64-bit value
306 } MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER
;
310 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
311 handler to handle unsuccessful read of this MSR.
313 @param ECX MSR_SANDY_BRIDGE_FEATURE_CONFIG (0x0000013C)
314 @param EAX Lower 32-bits of MSR value.
315 Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.
316 @param EDX Upper 32-bits of MSR value.
317 Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.
321 MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER Msr;
323 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);
324 AsmWriteMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG, Msr.Uint64);
326 @note MSR_SANDY_BRIDGE_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
328 #define MSR_SANDY_BRIDGE_FEATURE_CONFIG 0x0000013C
331 MSR information returned for MSR index #MSR_SANDY_BRIDGE_FEATURE_CONFIG
335 /// Individual bit fields
339 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
340 /// MSR, the configuration of AES instruction set availability is as
341 /// follows: 11b: AES instructions are not available until next RESET.
342 /// otherwise, AES instructions are available. Note, AES instruction set
343 /// is not available if read is unsuccessful. If the configuration is not
344 /// 01b, AES instruction can be mis-configured if a privileged agent
345 /// unintentionally writes 11b.
347 UINT32 AESConfiguration
:2;
352 /// All bit fields as a 32-bit value
356 /// All bit fields as a 64-bit value
359 } MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER
;
363 Core. See Table 2-2. If CPUID.0AH:EAX[15:8] = 8.
365 @param ECX MSR_SANDY_BRIDGE_IA32_PERFEVTSELn
366 @param EAX Lower 32-bits of MSR value.
367 @param EDX Upper 32-bits of MSR value.
373 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4);
374 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4, Msr);
376 @note MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 is defined as IA32_PERFEVTSEL4 in SDM.
377 MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 is defined as IA32_PERFEVTSEL5 in SDM.
378 MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 is defined as IA32_PERFEVTSEL6 in SDM.
379 MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 is defined as IA32_PERFEVTSEL7 in SDM.
382 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 0x0000018A
383 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 0x0000018B
384 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 0x0000018C
385 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 0x0000018D
392 @param ECX MSR_SANDY_BRIDGE_PERF_STATUS (0x00000198)
393 @param EAX Lower 32-bits of MSR value.
394 Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.
395 @param EDX Upper 32-bits of MSR value.
396 Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.
400 MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER Msr;
402 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS);
403 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS, Msr.Uint64);
405 @note MSR_SANDY_BRIDGE_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
407 #define MSR_SANDY_BRIDGE_PERF_STATUS 0x00000198
410 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PERF_STATUS
414 /// Individual bit fields
419 /// [Bits 47:32] Core Voltage (R/O) P-state core voltage can be computed
420 /// by MSR_PERF_STATUS[37:32] * (float) 1/(2^13).
422 UINT32 CoreVoltage
:16;
426 /// All bit fields as a 64-bit value
429 } MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER
;
433 Thread. Clock Modulation (R/W) See Table 2-2. IA32_CLOCK_MODULATION MSR was
434 originally named IA32_THERM_CONTROL MSR.
436 @param ECX MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION (0x0000019A)
437 @param EAX Lower 32-bits of MSR value.
438 Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.
439 @param EDX Upper 32-bits of MSR value.
440 Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.
444 MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER Msr;
446 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION);
447 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, Msr.Uint64);
449 @note MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.
451 #define MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION 0x0000019A
454 MSR information returned for MSR index
455 #MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION
459 /// Individual bit fields
463 /// [Bits 3:0] On demand Clock Modulation Duty Cycle (R/W) In 6.25%
466 UINT32 OnDemandClockModulationDutyCycle
:4;
468 /// [Bit 4] On demand Clock Modulation Enable (R/W).
470 UINT32 OnDemandClockModulationEnable
:1;
475 /// All bit fields as a 32-bit value
479 /// All bit fields as a 64-bit value
482 } MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER
;
486 Enable Misc. Processor Features (R/W) Allows a variety of processor
487 functions to be enabled and disabled.
489 @param ECX MSR_SANDY_BRIDGE_IA32_MISC_ENABLE (0x000001A0)
490 @param EAX Lower 32-bits of MSR value.
491 Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.
492 @param EDX Upper 32-bits of MSR value.
493 Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.
497 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER Msr;
499 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE);
500 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE, Msr.Uint64);
502 @note MSR_SANDY_BRIDGE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
504 #define MSR_SANDY_BRIDGE_IA32_MISC_ENABLE 0x000001A0
507 MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MISC_ENABLE
511 /// Individual bit fields
515 /// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.
517 UINT32 FastStrings
:1;
520 /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.
522 UINT32 PerformanceMonitoring
:1;
525 /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.
529 /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See
535 /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
541 /// [Bit 18] Thread. ENABLE MONITOR FSM (R/W) See Table 2-2.
546 /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.
548 UINT32 LimitCpuidMaxval
:1;
550 /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.
552 UINT32 xTPR_Message_Disable
:1;
556 /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.
561 /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors
562 /// that support Intel Turbo Boost Technology, the turbo mode feature is
563 /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
564 /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
565 /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
566 /// the power-on default value is used by BIOS to detect hardware support
567 /// of turbo mode. If power-on default value is 1, turbo mode is available
568 /// in the processor. If power-on default value is 0, turbo mode is not
571 UINT32 TurboModeDisable
:1;
575 /// All bit fields as a 64-bit value
578 } MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER
;
584 @param ECX MSR_SANDY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)
585 @param EAX Lower 32-bits of MSR value.
586 Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
587 @param EDX Upper 32-bits of MSR value.
588 Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
592 MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr;
594 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET);
595 AsmWriteMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);
597 @note MSR_SANDY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
599 #define MSR_SANDY_BRIDGE_TEMPERATURE_TARGET 0x000001A2
602 MSR information returned for MSR index #MSR_SANDY_BRIDGE_TEMPERATURE_TARGET
606 /// Individual bit fields
611 /// [Bits 23:16] Temperature Target (R) The minimum temperature at which
612 /// PROCHOT# will be asserted. The value is degree C.
614 UINT32 TemperatureTarget
:8;
619 /// All bit fields as a 32-bit value
623 /// All bit fields as a 64-bit value
626 } MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER
;
630 Miscellaneous Feature Control (R/W).
632 @param ECX MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL (0x000001A4)
633 @param EAX Lower 32-bits of MSR value.
634 Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.
635 @param EDX Upper 32-bits of MSR value.
636 Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.
640 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER Msr;
642 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL);
643 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL, Msr.Uint64);
645 @note MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
647 #define MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL 0x000001A4
650 MSR information returned for MSR index #MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL
654 /// Individual bit fields
658 /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
659 /// L2 hardware prefetcher, which fetches additional lines of code or data
660 /// into the L2 cache.
662 UINT32 L2HardwarePrefetcherDisable
:1;
664 /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,
665 /// disables the adjacent cache line prefetcher, which fetches the cache
666 /// line that comprises a cache line pair (128 bytes).
668 UINT32 L2AdjacentCacheLinePrefetcherDisable
:1;
670 /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables
671 /// the L1 data cache prefetcher, which fetches the next cache line into
674 UINT32 DCUHardwarePrefetcherDisable
:1;
676 /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1
677 /// data cache IP prefetcher, which uses sequential load history (based on
678 /// instruction Pointer of previous loads) to determine whether to
679 /// prefetch additional lines.
681 UINT32 DCUIPPrefetcherDisable
:1;
686 /// All bit fields as a 32-bit value
690 /// All bit fields as a 64-bit value
693 } MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER
;
697 Thread. Offcore Response Event Select Register (R/W).
699 @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_0 (0x000001A6)
700 @param EAX Lower 32-bits of MSR value.
701 @param EDX Upper 32-bits of MSR value.
707 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0);
708 AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0, Msr);
710 @note MSR_SANDY_BRIDGE_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
712 #define MSR_SANDY_BRIDGE_OFFCORE_RSP_0 0x000001A6
716 Thread. Offcore Response Event Select Register (R/W).
718 @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_1 (0x000001A7)
719 @param EAX Lower 32-bits of MSR value.
720 @param EDX Upper 32-bits of MSR value.
726 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1);
727 AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1, Msr);
729 @note MSR_SANDY_BRIDGE_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
731 #define MSR_SANDY_BRIDGE_OFFCORE_RSP_1 0x000001A7
735 See http://biosbits.org.
737 @param ECX MSR_SANDY_BRIDGE_MISC_PWR_MGMT (0x000001AA)
738 @param EAX Lower 32-bits of MSR value.
739 @param EDX Upper 32-bits of MSR value.
745 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT);
746 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT, Msr);
748 @note MSR_SANDY_BRIDGE_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.
750 #define MSR_SANDY_BRIDGE_MISC_PWR_MGMT 0x000001AA
754 Thread. Last Branch Record Filtering Select Register (R/W) See Section
755 17.9.2, "Filtering of Last Branch Records.".
757 @param ECX MSR_SANDY_BRIDGE_LBR_SELECT (0x000001C8)
758 @param EAX Lower 32-bits of MSR value.
759 Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.
760 @param EDX Upper 32-bits of MSR value.
761 Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.
765 MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER Msr;
767 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT);
768 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT, Msr.Uint64);
770 @note MSR_SANDY_BRIDGE_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
772 #define MSR_SANDY_BRIDGE_LBR_SELECT 0x000001C8
775 MSR information returned for MSR index #MSR_SANDY_BRIDGE_LBR_SELECT
779 /// Individual bit fields
783 /// [Bit 0] CPL_EQ_0.
787 /// [Bit 1] CPL_NEQ_0.
795 /// [Bit 3] NEAR_REL_CALL.
797 UINT32 NEAR_REL_CALL
:1;
799 /// [Bit 4] NEAR_IND_CALL.
801 UINT32 NEAR_IND_CALL
:1;
803 /// [Bit 5] NEAR_RET.
807 /// [Bit 6] NEAR_IND_JMP.
809 UINT32 NEAR_IND_JMP
:1;
811 /// [Bit 7] NEAR_REL_JMP.
813 UINT32 NEAR_REL_JMP
:1;
815 /// [Bit 8] FAR_BRANCH.
822 /// All bit fields as a 32-bit value
826 /// All bit fields as a 64-bit value
829 } MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER
;
833 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
834 that points to the MSR containing the most recent branch record. See
835 MSR_LASTBRANCH_0_FROM_IP (at 680H).
837 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_TOS (0x000001C9)
838 @param EAX Lower 32-bits of MSR value.
839 @param EDX Upper 32-bits of MSR value.
845 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS);
846 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS, Msr);
848 @note MSR_SANDY_BRIDGE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
850 #define MSR_SANDY_BRIDGE_LASTBRANCH_TOS 0x000001C9
854 Thread. Last Exception Record From Linear IP (R) Contains a pointer to the
855 last branch instruction that the processor executed prior to the last
856 exception that was generated or the last interrupt that was handled.
858 @param ECX MSR_SANDY_BRIDGE_LER_FROM_LIP (0x000001DD)
859 @param EAX Lower 32-bits of MSR value.
860 @param EDX Upper 32-bits of MSR value.
866 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_FROM_LIP);
868 @note MSR_SANDY_BRIDGE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
870 #define MSR_SANDY_BRIDGE_LER_FROM_LIP 0x000001DD
874 Thread. Last Exception Record To Linear IP (R) This area contains a pointer
875 to the target of the last branch instruction that the processor executed
876 prior to the last exception that was generated or the last interrupt that
879 @param ECX MSR_SANDY_BRIDGE_LER_TO_LIP (0x000001DE)
880 @param EAX Lower 32-bits of MSR value.
881 @param EDX Upper 32-bits of MSR value.
887 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_TO_LIP);
889 @note MSR_SANDY_BRIDGE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
891 #define MSR_SANDY_BRIDGE_LER_TO_LIP 0x000001DE
895 Core. See http://biosbits.org.
897 @param ECX MSR_SANDY_BRIDGE_POWER_CTL (0x000001FC)
898 @param EAX Lower 32-bits of MSR value.
899 @param EDX Upper 32-bits of MSR value.
905 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_POWER_CTL);
906 AsmWriteMsr64 (MSR_SANDY_BRIDGE_POWER_CTL, Msr);
908 @note MSR_SANDY_BRIDGE_POWER_CTL is defined as MSR_POWER_CTL in SDM.
910 #define MSR_SANDY_BRIDGE_POWER_CTL 0x000001FC
914 Package. Always 0 (CMCI not supported).
916 @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL2 (0x00000284)
917 @param EAX Lower 32-bits of MSR value.
918 @param EDX Upper 32-bits of MSR value.
924 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2);
925 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2, Msr);
927 @note MSR_SANDY_BRIDGE_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.
929 #define MSR_SANDY_BRIDGE_IA32_MC4_CTL2 0x00000284
933 See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".
935 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS (0x0000038E)
936 @param EAX Lower 32-bits of MSR value.
937 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER.
938 @param EDX Upper 32-bits of MSR value.
939 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER.
943 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
945 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS);
946 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);
948 @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
950 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS 0x0000038E
953 MSR information returned for MSR index
954 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS
958 /// Individual bit fields
962 /// [Bit 0] Thread. Ovf_PMC0.
966 /// [Bit 1] Thread. Ovf_PMC1.
970 /// [Bit 2] Thread. Ovf_PMC2.
974 /// [Bit 3] Thread. Ovf_PMC3.
978 /// [Bit 4] Core. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
982 /// [Bit 5] Core. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
986 /// [Bit 6] Core. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
990 /// [Bit 7] Core. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
995 /// [Bit 32] Thread. Ovf_FixedCtr0.
997 UINT32 Ovf_FixedCtr0
:1;
999 /// [Bit 33] Thread. Ovf_FixedCtr1.
1001 UINT32 Ovf_FixedCtr1
:1;
1003 /// [Bit 34] Thread. Ovf_FixedCtr2.
1005 UINT32 Ovf_FixedCtr2
:1;
1006 UINT32 Reserved2
:26;
1008 /// [Bit 61] Thread. Ovf_Uncore.
1010 UINT32 Ovf_Uncore
:1;
1012 /// [Bit 62] Thread. Ovf_BufDSSAVE.
1014 UINT32 Ovf_BufDSSAVE
:1;
1016 /// [Bit 63] Thread. CondChgd.
1021 /// All bit fields as a 64-bit value
1024 } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER
;
1028 Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control
1031 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL (0x0000038F)
1032 @param EAX Lower 32-bits of MSR value.
1033 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.
1034 @param EDX Upper 32-bits of MSR value.
1035 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.
1037 <b>Example usage</b>
1039 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;
1041 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL);
1042 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);
1044 @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.
1046 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL 0x0000038F
1049 MSR information returned for MSR index
1050 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL
1054 /// Individual bit fields
1058 /// [Bit 0] Thread. Set 1 to enable PMC0 to count.
1062 /// [Bit 1] Thread. Set 1 to enable PMC1 to count.
1066 /// [Bit 2] Thread. Set 1 to enable PMC2 to count.
1070 /// [Bit 3] Thread. Set 1 to enable PMC3 to count.
1074 /// [Bit 4] Core. Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] >
1079 /// [Bit 5] Core. Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] >
1084 /// [Bit 6] Core. Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] >
1089 /// [Bit 7] Core. Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] >
1093 UINT32 Reserved1
:24;
1095 /// [Bit 32] Thread. Set 1 to enable FixedCtr0 to count.
1097 UINT32 FIXED_CTR0
:1;
1099 /// [Bit 33] Thread. Set 1 to enable FixedCtr1 to count.
1101 UINT32 FIXED_CTR1
:1;
1103 /// [Bit 34] Thread. Set 1 to enable FixedCtr2 to count.
1105 UINT32 FIXED_CTR2
:1;
1106 UINT32 Reserved2
:29;
1109 /// All bit fields as a 64-bit value
1112 } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
;
1116 See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".
1118 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)
1119 @param EAX Lower 32-bits of MSR value.
1120 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
1121 @param EDX Upper 32-bits of MSR value.
1122 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
1124 <b>Example usage</b>
1126 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;
1128 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL);
1129 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
1131 @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.
1133 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
1136 MSR information returned for MSR index
1137 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL
1141 /// Individual bit fields
1145 /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.
1149 /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.
1153 /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.
1157 /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.
1161 /// [Bit 4] Core. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
1165 /// [Bit 5] Core. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
1169 /// [Bit 6] Core. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
1173 /// [Bit 7] Core. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
1176 UINT32 Reserved1
:24;
1178 /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.
1180 UINT32 Ovf_FixedCtr0
:1;
1182 /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.
1184 UINT32 Ovf_FixedCtr1
:1;
1186 /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.
1188 UINT32 Ovf_FixedCtr2
:1;
1189 UINT32 Reserved2
:26;
1191 /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.
1193 UINT32 Ovf_Uncore
:1;
1195 /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.
1197 UINT32 Ovf_BufDSSAVE
:1;
1199 /// [Bit 63] Thread. Set 1 to clear CondChgd.
1204 /// All bit fields as a 64-bit value
1207 } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER
;
1211 Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".
1213 @param ECX MSR_SANDY_BRIDGE_PEBS_ENABLE (0x000003F1)
1214 @param EAX Lower 32-bits of MSR value.
1215 Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.
1216 @param EDX Upper 32-bits of MSR value.
1217 Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.
1219 <b>Example usage</b>
1221 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER Msr;
1223 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE);
1224 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE, Msr.Uint64);
1226 @note MSR_SANDY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1228 #define MSR_SANDY_BRIDGE_PEBS_ENABLE 0x000003F1
1231 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_ENABLE
1235 /// Individual bit fields
1239 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
1241 UINT32 PEBS_EN_PMC0
:1;
1243 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
1245 UINT32 PEBS_EN_PMC1
:1;
1247 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
1249 UINT32 PEBS_EN_PMC2
:1;
1251 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
1253 UINT32 PEBS_EN_PMC3
:1;
1254 UINT32 Reserved1
:28;
1256 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
1258 UINT32 LL_EN_PMC0
:1;
1260 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
1262 UINT32 LL_EN_PMC1
:1;
1264 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
1266 UINT32 LL_EN_PMC2
:1;
1268 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
1270 UINT32 LL_EN_PMC3
:1;
1271 UINT32 Reserved2
:27;
1273 /// [Bit 63] Enable Precise Store. (R/W).
1278 /// All bit fields as a 64-bit value
1281 } MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
;
1285 Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring
1288 @param ECX MSR_SANDY_BRIDGE_PEBS_LD_LAT (0x000003F6)
1289 @param EAX Lower 32-bits of MSR value.
1290 Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.
1291 @param EDX Upper 32-bits of MSR value.
1292 Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.
1294 <b>Example usage</b>
1296 MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER Msr;
1298 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT);
1299 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT, Msr.Uint64);
1301 @note MSR_SANDY_BRIDGE_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.
1303 #define MSR_SANDY_BRIDGE_PEBS_LD_LAT 0x000003F6
1306 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_LD_LAT
1310 /// Individual bit fields
1314 /// [Bits 15:0] Minimum threshold latency value of tagged load operation
1315 /// that will be counted. (R/W).
1317 UINT32 MinimumThreshold
:16;
1318 UINT32 Reserved1
:16;
1319 UINT32 Reserved2
:32;
1322 /// All bit fields as a 32-bit value
1326 /// All bit fields as a 64-bit value
1329 } MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER
;
1333 Package. Note: C-state values are processor specific C-state code names,
1334 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3
1335 Residency Counter. (R/O) Value since last reset that this package is in
1336 processor-specific C3 states. Count at the same frequency as the TSC.
1338 @param ECX MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY (0x000003F8)
1339 @param EAX Lower 32-bits of MSR value.
1340 @param EDX Upper 32-bits of MSR value.
1342 <b>Example usage</b>
1346 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY);
1347 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY, Msr);
1349 @note MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
1351 #define MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY 0x000003F8
1355 Package. Note: C-state values are processor specific C-state code names,
1356 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
1357 Residency Counter. (R/O) Value since last reset that this package is in
1358 processor-specific C6 states. Count at the same frequency as the TSC.
1360 @param ECX MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY (0x000003F9)
1361 @param EAX Lower 32-bits of MSR value.
1362 @param EDX Upper 32-bits of MSR value.
1364 <b>Example usage</b>
1368 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY);
1369 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY, Msr);
1371 @note MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
1373 #define MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY 0x000003F9
1377 Package. Note: C-state values are processor specific C-state code names,
1378 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7
1379 Residency Counter. (R/O) Value since last reset that this package is in
1380 processor-specific C7 states. Count at the same frequency as the TSC.
1382 @param ECX MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY (0x000003FA)
1383 @param EAX Lower 32-bits of MSR value.
1384 @param EDX Upper 32-bits of MSR value.
1386 <b>Example usage</b>
1390 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY);
1391 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY, Msr);
1393 @note MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
1395 #define MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY 0x000003FA
1399 Core. Note: C-state values are processor specific C-state code names,
1400 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3
1401 Residency Counter. (R/O) Value since last reset that this core is in
1402 processor-specific C3 states. Count at the same frequency as the TSC.
1404 @param ECX MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY (0x000003FC)
1405 @param EAX Lower 32-bits of MSR value.
1406 @param EDX Upper 32-bits of MSR value.
1408 <b>Example usage</b>
1412 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY);
1413 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY, Msr);
1415 @note MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.
1417 #define MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY 0x000003FC
1421 Core. Note: C-state values are processor specific C-state code names,
1422 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6
1423 Residency Counter. (R/O) Value since last reset that this core is in
1424 processor-specific C6 states. Count at the same frequency as the TSC.
1426 @param ECX MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY (0x000003FD)
1427 @param EAX Lower 32-bits of MSR value.
1428 @param EDX Upper 32-bits of MSR value.
1430 <b>Example usage</b>
1434 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY);
1435 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY, Msr);
1437 @note MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
1439 #define MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY 0x000003FD
1443 Core. Note: C-state values are processor specific C-state code names,
1444 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C7
1445 Residency Counter. (R/O) Value since last reset that this core is in
1446 processor-specific C7 states. Count at the same frequency as the TSC.
1448 @param ECX MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY (0x000003FE)
1449 @param EAX Lower 32-bits of MSR value.
1450 @param EDX Upper 32-bits of MSR value.
1452 <b>Example usage</b>
1456 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY);
1457 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY, Msr);
1459 @note MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY is defined as MSR_CORE_C7_RESIDENCY in SDM.
1461 #define MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY 0x000003FE
1465 Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
1467 @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL (0x00000410)
1468 @param EAX Lower 32-bits of MSR value.
1469 Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER.
1470 @param EDX Upper 32-bits of MSR value.
1471 Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER.
1473 <b>Example usage</b>
1475 MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER Msr;
1477 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL);
1478 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL, Msr.Uint64);
1480 @note MSR_SANDY_BRIDGE_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.
1482 #define MSR_SANDY_BRIDGE_IA32_MC4_CTL 0x00000410
1485 MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MC4_CTL
1489 /// Individual bit fields
1493 /// [Bit 0] PCU Hardware Error (R/W) When set, enables signaling of PCU
1494 /// hardware detected errors.
1496 UINT32 PCUHardwareError
:1;
1498 /// [Bit 1] PCU Controller Error (R/W) When set, enables signaling of PCU
1499 /// controller detected errors.
1501 UINT32 PCUControllerError
:1;
1503 /// [Bit 2] PCU Firmware Error (R/W) When set, enables signaling of PCU
1504 /// firmware detected errors.
1506 UINT32 PCUFirmwareError
:1;
1507 UINT32 Reserved1
:29;
1508 UINT32 Reserved2
:32;
1511 /// All bit fields as a 32-bit value
1515 /// All bit fields as a 64-bit value
1518 } MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER
;
1522 Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.
1524 @param ECX MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
1525 @param EAX Lower 32-bits of MSR value.
1526 @param EDX Upper 32-bits of MSR value.
1528 <b>Example usage</b>
1532 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM);
1534 @note MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
1536 #define MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM 0x0000048C
1540 Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,
1543 @param ECX MSR_SANDY_BRIDGE_RAPL_POWER_UNIT (0x00000606)
1544 @param EAX Lower 32-bits of MSR value.
1545 @param EDX Upper 32-bits of MSR value.
1547 <b>Example usage</b>
1551 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_RAPL_POWER_UNIT);
1553 @note MSR_SANDY_BRIDGE_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
1555 #define MSR_SANDY_BRIDGE_RAPL_POWER_UNIT 0x00000606
1559 Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are
1560 processor specific C-state code names, unrelated to MWAIT extension C-state
1561 parameters or ACPI CStates.
1563 @param ECX MSR_SANDY_BRIDGE_PKGC3_IRTL (0x0000060A)
1564 @param EAX Lower 32-bits of MSR value.
1565 Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.
1566 @param EDX Upper 32-bits of MSR value.
1567 Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.
1569 <b>Example usage</b>
1571 MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER Msr;
1573 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL);
1574 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL, Msr.Uint64);
1576 @note MSR_SANDY_BRIDGE_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.
1578 #define MSR_SANDY_BRIDGE_PKGC3_IRTL 0x0000060A
1581 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC3_IRTL
1585 /// Individual bit fields
1589 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
1590 /// that should be used to decide if the package should be put into a
1591 /// package C3 state.
1593 UINT32 TimeLimit
:10;
1595 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
1596 /// unit of the interrupt response time limit. The following time unit
1597 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
1598 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
1603 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
1604 /// valid and can be used by the processor for package C-sate management.
1607 UINT32 Reserved2
:16;
1608 UINT32 Reserved3
:32;
1611 /// All bit fields as a 32-bit value
1615 /// All bit fields as a 64-bit value
1618 } MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER
;
1622 Package. Package C6 Interrupt Response Limit (R/W) This MSR defines the
1623 budget allocated for the package to exit from C6 to a C0 state, where
1624 interrupt request can be delivered to the core and serviced. Additional
1625 core-exit latency amy be applicable depending on the actual C-state the core
1626 is in. Note: C-state values are processor specific C-state code names,
1627 unrelated to MWAIT extension C-state parameters or ACPI CStates.
1629 @param ECX MSR_SANDY_BRIDGE_PKGC6_IRTL (0x0000060B)
1630 @param EAX Lower 32-bits of MSR value.
1631 Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.
1632 @param EDX Upper 32-bits of MSR value.
1633 Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.
1635 <b>Example usage</b>
1637 MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER Msr;
1639 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL);
1640 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL, Msr.Uint64);
1642 @note MSR_SANDY_BRIDGE_PKGC6_IRTL is defined as MSR_PKGC6_IRTL in SDM.
1644 #define MSR_SANDY_BRIDGE_PKGC6_IRTL 0x0000060B
1647 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC6_IRTL
1651 /// Individual bit fields
1655 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
1656 /// that should be used to decide if the package should be put into a
1657 /// package C6 state.
1659 UINT32 TimeLimit
:10;
1661 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
1662 /// unit of the interrupt response time limit. The following time unit
1663 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
1664 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
1669 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
1670 /// valid and can be used by the processor for package C-sate management.
1673 UINT32 Reserved2
:16;
1674 UINT32 Reserved3
:32;
1677 /// All bit fields as a 32-bit value
1681 /// All bit fields as a 64-bit value
1684 } MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER
;
1688 Package. Note: C-state values are processor specific C-state code names,
1689 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2
1690 Residency Counter. (R/O) Value since last reset that this package is in
1691 processor-specific C2 states. Count at the same frequency as the TSC.
1693 @param ECX MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY (0x0000060D)
1694 @param EAX Lower 32-bits of MSR value.
1695 @param EDX Upper 32-bits of MSR value.
1697 <b>Example usage</b>
1701 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY);
1702 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY, Msr);
1704 @note MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
1706 #define MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY 0x0000060D
1710 Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
1713 @param ECX MSR_SANDY_BRIDGE_PKG_POWER_LIMIT (0x00000610)
1714 @param EAX Lower 32-bits of MSR value.
1715 @param EDX Upper 32-bits of MSR value.
1717 <b>Example usage</b>
1721 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT);
1722 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT, Msr);
1724 @note MSR_SANDY_BRIDGE_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
1726 #define MSR_SANDY_BRIDGE_PKG_POWER_LIMIT 0x00000610
1730 Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1732 @param ECX MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS (0x00000611)
1733 @param EAX Lower 32-bits of MSR value.
1734 @param EDX Upper 32-bits of MSR value.
1736 <b>Example usage</b>
1740 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS);
1742 @note MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
1744 #define MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS 0x00000611
1748 Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL
1751 @param ECX MSR_SANDY_BRIDGE_PKG_POWER_INFO (0x00000614)
1752 @param EAX Lower 32-bits of MSR value.
1753 @param EDX Upper 32-bits of MSR value.
1755 <b>Example usage</b>
1759 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO);
1760 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO, Msr);
1762 @note MSR_SANDY_BRIDGE_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
1764 #define MSR_SANDY_BRIDGE_PKG_POWER_INFO 0x00000614
1768 Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
1771 @param ECX MSR_SANDY_BRIDGE_PP0_POWER_LIMIT (0x00000638)
1772 @param EAX Lower 32-bits of MSR value.
1773 @param EDX Upper 32-bits of MSR value.
1775 <b>Example usage</b>
1779 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT);
1780 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT, Msr);
1782 @note MSR_SANDY_BRIDGE_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
1784 #define MSR_SANDY_BRIDGE_PP0_POWER_LIMIT 0x00000638
1788 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1791 @param ECX MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)
1792 @param EAX Lower 32-bits of MSR value.
1793 @param EDX Upper 32-bits of MSR value.
1795 <b>Example usage</b>
1799 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS);
1801 @note MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
1803 #define MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS 0x00000639
1807 Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last
1808 branch record registers on the last branch record stack. This part of the
1809 stack contains pointers to the source instruction. See also: - Last Branch
1810 Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section
1813 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_FROM_IP
1814 @param EAX Lower 32-bits of MSR value.
1815 @param EDX Upper 32-bits of MSR value.
1817 <b>Example usage</b>
1821 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP);
1822 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP, Msr);
1824 @note MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
1825 MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
1826 MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
1827 MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
1828 MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
1829 MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
1830 MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
1831 MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
1832 MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.
1833 MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.
1834 MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.
1835 MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.
1836 MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.
1837 MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.
1838 MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.
1839 MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.
1842 #define MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP 0x00000680
1843 #define MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP 0x00000681
1844 #define MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP 0x00000682
1845 #define MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP 0x00000683
1846 #define MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP 0x00000684
1847 #define MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP 0x00000685
1848 #define MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP 0x00000686
1849 #define MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP 0x00000687
1850 #define MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP 0x00000688
1851 #define MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP 0x00000689
1852 #define MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP 0x0000068A
1853 #define MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP 0x0000068B
1854 #define MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP 0x0000068C
1855 #define MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP 0x0000068D
1856 #define MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP 0x0000068E
1857 #define MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP 0x0000068F
1862 Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch
1863 record registers on the last branch record stack. This part of the stack
1864 contains pointers to the destination instruction.
1866 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_TO_IP
1867 @param EAX Lower 32-bits of MSR value.
1868 @param EDX Upper 32-bits of MSR value.
1870 <b>Example usage</b>
1874 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP);
1875 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP, Msr);
1877 @note MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
1878 MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
1879 MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
1880 MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
1881 MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
1882 MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
1883 MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
1884 MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
1885 MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.
1886 MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.
1887 MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.
1888 MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.
1889 MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.
1890 MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.
1891 MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.
1892 MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.
1895 #define MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP 0x000006C0
1896 #define MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP 0x000006C1
1897 #define MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP 0x000006C2
1898 #define MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP 0x000006C3
1899 #define MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP 0x000006C4
1900 #define MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP 0x000006C5
1901 #define MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP 0x000006C6
1902 #define MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP 0x000006C7
1903 #define MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP 0x000006C8
1904 #define MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP 0x000006C9
1905 #define MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP 0x000006CA
1906 #define MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP 0x000006CB
1907 #define MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP 0x000006CC
1908 #define MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP 0x000006CD
1909 #define MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP 0x000006CE
1910 #define MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP 0x000006CF
1915 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
1916 RW if MSR_PLATFORM_INFO.[28] = 1.
1918 @param ECX MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT (0x000001AD)
1919 @param EAX Lower 32-bits of MSR value.
1920 Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.
1921 @param EDX Upper 32-bits of MSR value.
1922 Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.
1924 <b>Example usage</b>
1926 MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER Msr;
1928 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT);
1930 @note MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
1932 #define MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT 0x000001AD
1935 MSR information returned for MSR index #MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT
1939 /// Individual bit fields
1943 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
1944 /// limit of 1 core active.
1948 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
1949 /// limit of 2 core active.
1953 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
1954 /// limit of 3 core active.
1958 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
1959 /// limit of 4 core active.
1963 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
1964 /// limit of 5 core active.
1968 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
1969 /// limit of 6 core active.
1973 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
1974 /// limit of 7 core active.
1978 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
1979 /// limit of 8 core active.
1984 /// All bit fields as a 64-bit value
1987 } MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER
;
1991 Package. Uncore PMU global control.
1993 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL (0x00000391)
1994 @param EAX Lower 32-bits of MSR value.
1995 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.
1996 @param EDX Upper 32-bits of MSR value.
1997 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.
1999 <b>Example usage</b>
2001 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;
2003 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL);
2004 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);
2006 @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.
2008 #define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL 0x00000391
2011 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL
2015 /// Individual bit fields
2019 /// [Bit 0] Slice 0 select.
2021 UINT32 PMI_Sel_Slice0
:1;
2023 /// [Bit 1] Slice 1 select.
2025 UINT32 PMI_Sel_Slice1
:1;
2027 /// [Bit 2] Slice 2 select.
2029 UINT32 PMI_Sel_Slice2
:1;
2031 /// [Bit 3] Slice 3 select.
2033 UINT32 PMI_Sel_Slice3
:1;
2035 /// [Bit 4] Slice 4 select.
2037 UINT32 PMI_Sel_Slice4
:1;
2038 UINT32 Reserved1
:14;
2039 UINT32 Reserved2
:10;
2041 /// [Bit 29] Enable all uncore counters.
2045 /// [Bit 30] Enable wake on PMI.
2049 /// [Bit 31] Enable Freezing counter when overflow.
2052 UINT32 Reserved3
:32;
2055 /// All bit fields as a 32-bit value
2059 /// All bit fields as a 64-bit value
2062 } MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER
;
2066 Package. Uncore PMU main status.
2068 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS (0x00000392)
2069 @param EAX Lower 32-bits of MSR value.
2070 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.
2071 @param EDX Upper 32-bits of MSR value.
2072 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.
2074 <b>Example usage</b>
2076 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;
2078 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS);
2079 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);
2081 @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.
2083 #define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS 0x00000392
2086 MSR information returned for MSR index
2087 #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS
2091 /// Individual bit fields
2095 /// [Bit 0] Fixed counter overflowed.
2099 /// [Bit 1] An ARB counter overflowed.
2104 /// [Bit 3] A CBox counter overflowed (on any slice).
2107 UINT32 Reserved2
:28;
2108 UINT32 Reserved3
:32;
2111 /// All bit fields as a 32-bit value
2115 /// All bit fields as a 64-bit value
2118 } MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER
;
2122 Package. Uncore fixed counter control (R/W).
2124 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL (0x00000394)
2125 @param EAX Lower 32-bits of MSR value.
2126 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.
2127 @param EDX Upper 32-bits of MSR value.
2128 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.
2130 <b>Example usage</b>
2132 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER Msr;
2134 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL);
2135 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL, Msr.Uint64);
2137 @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.
2139 #define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL 0x00000394
2142 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL
2146 /// Individual bit fields
2149 UINT32 Reserved1
:20;
2151 /// [Bit 20] Enable overflow propagation.
2153 UINT32 EnableOverflow
:1;
2156 /// [Bit 22] Enable counting.
2158 UINT32 EnableCounting
:1;
2160 UINT32 Reserved4
:32;
2163 /// All bit fields as a 32-bit value
2167 /// All bit fields as a 64-bit value
2170 } MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER
;
2174 Package. Uncore fixed counter.
2176 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR (0x00000395)
2177 @param EAX Lower 32-bits of MSR value.
2178 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.
2179 @param EDX Upper 32-bits of MSR value.
2180 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.
2182 <b>Example usage</b>
2184 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER Msr;
2186 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR);
2187 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR, Msr.Uint64);
2189 @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.
2191 #define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR 0x00000395
2194 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR
2198 /// Individual bit fields
2202 /// [Bits 31:0] Current count.
2204 UINT32 CurrentCount
:32;
2206 /// [Bits 47:32] Current count.
2208 UINT32 CurrentCountHi
:16;
2212 /// All bit fields as a 64-bit value
2215 } MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER
;
2219 Package. Uncore C-Box configuration information (R/O).
2221 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_CONFIG (0x00000396)
2222 @param EAX Lower 32-bits of MSR value.
2223 Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.
2224 @param EDX Upper 32-bits of MSR value.
2225 Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.
2227 <b>Example usage</b>
2229 MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER Msr;
2231 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_CONFIG);
2233 @note MSR_SANDY_BRIDGE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.
2235 #define MSR_SANDY_BRIDGE_UNC_CBO_CONFIG 0x00000396
2238 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_CBO_CONFIG
2242 /// Individual bit fields
2246 /// [Bits 3:0] Report the number of C-Box units with performance counters,
2247 /// including processor cores and processor graphics".
2250 UINT32 Reserved1
:28;
2251 UINT32 Reserved2
:32;
2254 /// All bit fields as a 32-bit value
2258 /// All bit fields as a 64-bit value
2261 } MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER
;
2265 Package. Uncore Arb unit, performance counter 0.
2267 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 (0x000003B0)
2268 @param EAX Lower 32-bits of MSR value.
2269 @param EDX Upper 32-bits of MSR value.
2271 <b>Example usage</b>
2275 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0);
2276 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0, Msr);
2278 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.
2280 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 0x000003B0
2284 Package. Uncore Arb unit, performance counter 1.
2286 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 (0x000003B1)
2287 @param EAX Lower 32-bits of MSR value.
2288 @param EDX Upper 32-bits of MSR value.
2290 <b>Example usage</b>
2294 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1);
2295 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1, Msr);
2297 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.
2299 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 0x000003B1
2303 Package. Uncore Arb unit, counter 0 event select MSR.
2305 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 (0x000003B2)
2306 @param EAX Lower 32-bits of MSR value.
2307 @param EDX Upper 32-bits of MSR value.
2309 <b>Example usage</b>
2313 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0);
2314 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0, Msr);
2316 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.
2318 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 0x000003B2
2322 Package. Uncore Arb unit, counter 1 event select MSR.
2324 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 (0x000003B3)
2325 @param EAX Lower 32-bits of MSR value.
2326 @param EDX Upper 32-bits of MSR value.
2328 <b>Example usage</b>
2332 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1);
2333 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1, Msr);
2335 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.
2337 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 0x000003B3
2341 Package. Package C7 Interrupt Response Limit (R/W) This MSR defines the
2342 budget allocated for the package to exit from C7 to a C0 state, where
2343 interrupt request can be delivered to the core and serviced. Additional
2344 core-exit latency amy be applicable depending on the actual C-state the core
2345 is in. Note: C-state values are processor specific C-state code names,
2346 unrelated to MWAIT extension C-state parameters or ACPI CStates.
2348 @param ECX MSR_SANDY_BRIDGE_PKGC7_IRTL (0x0000060C)
2349 @param EAX Lower 32-bits of MSR value.
2350 Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.
2351 @param EDX Upper 32-bits of MSR value.
2352 Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.
2354 <b>Example usage</b>
2356 MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER Msr;
2358 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL);
2359 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL, Msr.Uint64);
2361 @note MSR_SANDY_BRIDGE_PKGC7_IRTL is defined as MSR_PKGC7_IRTL in SDM.
2363 #define MSR_SANDY_BRIDGE_PKGC7_IRTL 0x0000060C
2366 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC7_IRTL
2370 /// Individual bit fields
2374 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
2375 /// that should be used to decide if the package should be put into a
2376 /// package C7 state.
2378 UINT32 TimeLimit
:10;
2380 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
2381 /// unit of the interrupt response time limit. The following time unit
2382 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
2383 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
2388 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
2389 /// valid and can be used by the processor for package C-sate management.
2392 UINT32 Reserved2
:16;
2393 UINT32 Reserved3
:32;
2396 /// All bit fields as a 32-bit value
2400 /// All bit fields as a 64-bit value
2403 } MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER
;
2407 Package. PP0 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
2410 @param ECX MSR_SANDY_BRIDGE_PP0_POLICY (0x0000063A)
2411 @param EAX Lower 32-bits of MSR value.
2412 @param EDX Upper 32-bits of MSR value.
2414 <b>Example usage</b>
2418 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY);
2419 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY, Msr);
2421 @note MSR_SANDY_BRIDGE_PP0_POLICY is defined as MSR_PP0_POLICY in SDM.
2423 #define MSR_SANDY_BRIDGE_PP0_POLICY 0x0000063A
2427 Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
2430 @param ECX MSR_SANDY_BRIDGE_PP1_POWER_LIMIT (0x00000640)
2431 @param EAX Lower 32-bits of MSR value.
2432 @param EDX Upper 32-bits of MSR value.
2434 <b>Example usage</b>
2438 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT);
2439 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT, Msr);
2441 @note MSR_SANDY_BRIDGE_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.
2443 #define MSR_SANDY_BRIDGE_PP1_POWER_LIMIT 0x00000640
2447 Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
2450 @param ECX MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS (0x00000641)
2451 @param EAX Lower 32-bits of MSR value.
2452 @param EDX Upper 32-bits of MSR value.
2454 <b>Example usage</b>
2458 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS);
2460 @note MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.
2462 #define MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS 0x00000641
2466 Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
2469 @param ECX MSR_SANDY_BRIDGE_PP1_POLICY (0x00000642)
2470 @param EAX Lower 32-bits of MSR value.
2471 @param EDX Upper 32-bits of MSR value.
2473 <b>Example usage</b>
2477 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY);
2478 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY, Msr);
2480 @note MSR_SANDY_BRIDGE_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.
2482 #define MSR_SANDY_BRIDGE_PP1_POLICY 0x00000642
2486 Package. Uncore C-Box 0, counter n event select MSR.
2488 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSELn
2489 @param EAX Lower 32-bits of MSR value.
2490 @param EDX Upper 32-bits of MSR value.
2492 <b>Example usage</b>
2496 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0);
2497 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0, Msr);
2499 @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.
2500 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.
2501 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 is defined as MSR_UNC_CBO_0_PERFEVTSEL2 in SDM.
2502 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 is defined as MSR_UNC_CBO_0_PERFEVTSEL3 in SDM.
2505 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 0x00000700
2506 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701
2507 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 0x00000702
2508 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 0x00000703
2513 Package. Uncore C-Box n, unit status for counter 0-3.
2515 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_n_UNIT_STATUS
2516 @param EAX Lower 32-bits of MSR value.
2517 @param EDX Upper 32-bits of MSR value.
2519 <b>Example usage</b>
2523 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS);
2524 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS, Msr);
2526 @note MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS is defined as MSR_UNC_CBO_0_UNIT_STATUS in SDM.
2527 MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS is defined as MSR_UNC_CBO_1_UNIT_STATUS in SDM.
2528 MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS is defined as MSR_UNC_CBO_2_UNIT_STATUS in SDM.
2529 MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS is defined as MSR_UNC_CBO_3_UNIT_STATUS in SDM.
2530 MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS is defined as MSR_UNC_CBO_4_UNIT_STATUS in SDM.
2533 #define MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS 0x00000705
2534 #define MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS 0x00000715
2535 #define MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS 0x00000725
2536 #define MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS 0x00000735
2537 #define MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS 0x00000745
2542 Package. Uncore C-Box 0, performance counter n.
2544 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTRn
2545 @param EAX Lower 32-bits of MSR value.
2546 @param EDX Upper 32-bits of MSR value.
2548 <b>Example usage</b>
2552 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0);
2553 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0, Msr);
2555 @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.
2556 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.
2557 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 is defined as MSR_UNC_CBO_0_PERFCTR2 in SDM.
2558 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 is defined as MSR_UNC_CBO_0_PERFCTR3 in SDM.
2561 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 0x00000706
2562 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 0x00000707
2563 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 0x00000708
2564 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 0x00000709
2569 Package. Uncore C-Box 1, counter n event select MSR.
2571 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSELn
2572 @param EAX Lower 32-bits of MSR value.
2573 @param EDX Upper 32-bits of MSR value.
2575 <b>Example usage</b>
2579 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0);
2580 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0, Msr);
2582 @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.
2583 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.
2584 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 is defined as MSR_UNC_CBO_1_PERFEVTSEL2 in SDM.
2585 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 is defined as MSR_UNC_CBO_1_PERFEVTSEL3 in SDM.
2588 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 0x00000710
2589 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 0x00000711
2590 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 0x00000712
2591 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 0x00000713
2596 Package. Uncore C-Box 1, performance counter n.
2598 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTRn
2599 @param EAX Lower 32-bits of MSR value.
2600 @param EDX Upper 32-bits of MSR value.
2602 <b>Example usage</b>
2606 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0);
2607 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0, Msr);
2609 @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.
2610 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.
2611 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 is defined as MSR_UNC_CBO_1_PERFCTR2 in SDM.
2612 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 is defined as MSR_UNC_CBO_1_PERFCTR3 in SDM.
2615 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 0x00000716
2616 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 0x00000717
2617 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 0x00000718
2618 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 0x00000719
2623 Package. Uncore C-Box 2, counter n event select MSR.
2625 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSELn
2626 @param EAX Lower 32-bits of MSR value.
2627 @param EDX Upper 32-bits of MSR value.
2629 <b>Example usage</b>
2633 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0);
2634 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0, Msr);
2636 @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.
2637 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.
2638 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 is defined as MSR_UNC_CBO_2_PERFEVTSEL2 in SDM.
2639 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 is defined as MSR_UNC_CBO_2_PERFEVTSEL3 in SDM.
2642 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 0x00000720
2643 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 0x00000721
2644 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 0x00000722
2645 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 0x00000723
2650 Package. Uncore C-Box 2, performance counter n.
2652 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTRn
2653 @param EAX Lower 32-bits of MSR value.
2654 @param EDX Upper 32-bits of MSR value.
2656 <b>Example usage</b>
2660 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0);
2661 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0, Msr);
2663 @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.
2664 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.
2665 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 is defined as MSR_UNC_CBO_2_PERFCTR2 in SDM.
2666 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 is defined as MSR_UNC_CBO_2_PERFCTR3 in SDM.
2669 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 0x00000726
2670 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 0x00000727
2671 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 0x00000728
2672 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 0x00000729
2677 Package. Uncore C-Box 3, counter n event select MSR.
2679 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSELn
2680 @param EAX Lower 32-bits of MSR value.
2681 @param EDX Upper 32-bits of MSR value.
2683 <b>Example usage</b>
2687 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0);
2688 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0, Msr);
2690 @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.
2691 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.
2692 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 is defined as MSR_UNC_CBO_3_PERFEVTSEL2 in SDM.
2693 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 is defined as MSR_UNC_CBO_3_PERFEVTSEL3 in SDM.
2696 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 0x00000730
2697 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731
2698 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 0x00000732
2699 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 0x00000733
2704 Package. Uncore C-Box 3, performance counter n.
2706 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTRn
2707 @param EAX Lower 32-bits of MSR value.
2708 @param EDX Upper 32-bits of MSR value.
2710 <b>Example usage</b>
2714 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0);
2715 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0, Msr);
2717 @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.
2718 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.
2719 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 is defined as MSR_UNC_CBO_3_PERFCTR2 in SDM.
2720 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 is defined as MSR_UNC_CBO_3_PERFCTR3 in SDM.
2723 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736
2724 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737
2725 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 0x00000738
2726 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 0x00000739
2731 Package. Uncore C-Box 4, counter n event select MSR.
2733 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSELn
2734 @param EAX Lower 32-bits of MSR value.
2735 @param EDX Upper 32-bits of MSR value.
2737 <b>Example usage</b>
2741 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0);
2742 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0, Msr);
2744 @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 is defined as MSR_UNC_CBO_4_PERFEVTSEL0 in SDM.
2745 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 is defined as MSR_UNC_CBO_4_PERFEVTSEL1 in SDM.
2746 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 is defined as MSR_UNC_CBO_4_PERFEVTSEL2 in SDM.
2747 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 is defined as MSR_UNC_CBO_4_PERFEVTSEL3 in SDM.
2750 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 0x00000740
2751 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 0x00000741
2752 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 0x00000742
2753 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 0x00000743
2758 Package. Uncore C-Box 4, performance counter n.
2760 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTRn
2761 @param EAX Lower 32-bits of MSR value.
2762 @param EDX Upper 32-bits of MSR value.
2764 <b>Example usage</b>
2768 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0);
2769 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0, Msr);
2771 @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 is defined as MSR_UNC_CBO_4_PERFCTR0 in SDM.
2772 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 is defined as MSR_UNC_CBO_4_PERFCTR1 in SDM.
2773 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 is defined as MSR_UNC_CBO_4_PERFCTR2 in SDM.
2774 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 is defined as MSR_UNC_CBO_4_PERFCTR3 in SDM.
2777 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 0x00000746
2778 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 0x00000747
2779 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 0x00000748
2780 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 0x00000749
2785 Package. MC Bank Error Configuration (R/W).
2787 @param ECX MSR_SANDY_BRIDGE_ERROR_CONTROL (0x0000017F)
2788 @param EAX Lower 32-bits of MSR value.
2789 Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.
2790 @param EDX Upper 32-bits of MSR value.
2791 Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.
2793 <b>Example usage</b>
2795 MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER Msr;
2797 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL);
2798 AsmWriteMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL, Msr.Uint64);
2800 @note MSR_SANDY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
2802 #define MSR_SANDY_BRIDGE_ERROR_CONTROL 0x0000017F
2805 MSR information returned for MSR index #MSR_SANDY_BRIDGE_ERROR_CONTROL
2809 /// Individual bit fields
2814 /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank
2815 /// to log additional info in bits 36:32.
2817 UINT32 MemErrorLogEnable
:1;
2818 UINT32 Reserved2
:30;
2819 UINT32 Reserved3
:32;
2822 /// All bit fields as a 32-bit value
2826 /// All bit fields as a 64-bit value
2829 } MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER
;
2835 @param ECX MSR_SANDY_BRIDGE_PEBS_NUM_ALT (0x0000039C)
2836 @param EAX Lower 32-bits of MSR value.
2837 Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.
2838 @param EDX Upper 32-bits of MSR value.
2839 Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.
2841 <b>Example usage</b>
2843 MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER Msr;
2845 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT);
2846 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT, Msr.Uint64);
2848 @note MSR_SANDY_BRIDGE_PEBS_NUM_ALT is defined as MSR_PEBS_NUM_ALT in SDM.
2850 #define MSR_SANDY_BRIDGE_PEBS_NUM_ALT 0x0000039C
2853 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_NUM_ALT
2857 /// Individual bit fields
2861 /// [Bit 0] ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS
2862 /// counting logic for specific events requiring additional configuration,
2863 /// see Table 19-17.
2865 UINT32 ENABLE_PEBS_NUM_ALT
:1;
2866 UINT32 Reserved1
:31;
2867 UINT32 Reserved2
:32;
2870 /// All bit fields as a 32-bit value
2874 /// All bit fields as a 64-bit value
2877 } MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER
;
2881 Package. Package RAPL Perf Status (R/O).
2883 @param ECX MSR_SANDY_BRIDGE_PKG_PERF_STATUS (0x00000613)
2884 @param EAX Lower 32-bits of MSR value.
2885 @param EDX Upper 32-bits of MSR value.
2887 <b>Example usage</b>
2891 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_PERF_STATUS);
2893 @note MSR_SANDY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
2895 #define MSR_SANDY_BRIDGE_PKG_PERF_STATUS 0x00000613
2899 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
2902 @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)
2903 @param EAX Lower 32-bits of MSR value.
2904 @param EDX Upper 32-bits of MSR value.
2906 <b>Example usage</b>
2910 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT);
2911 AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT, Msr);
2913 @note MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
2915 #define MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT 0x00000618
2919 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
2921 @param ECX MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)
2922 @param EAX Lower 32-bits of MSR value.
2923 @param EDX Upper 32-bits of MSR value.
2925 <b>Example usage</b>
2929 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS);
2931 @note MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
2933 #define MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619
2937 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
2940 @param ECX MSR_SANDY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)
2941 @param EAX Lower 32-bits of MSR value.
2942 @param EDX Upper 32-bits of MSR value.
2944 <b>Example usage</b>
2948 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_PERF_STATUS);
2950 @note MSR_SANDY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
2952 #define MSR_SANDY_BRIDGE_DRAM_PERF_STATUS 0x0000061B
2956 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
2958 @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_INFO (0x0000061C)
2959 @param EAX Lower 32-bits of MSR value.
2960 @param EDX Upper 32-bits of MSR value.
2962 <b>Example usage</b>
2966 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO);
2967 AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO, Msr);
2969 @note MSR_SANDY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
2971 #define MSR_SANDY_BRIDGE_DRAM_POWER_INFO 0x0000061C
2975 Package. Uncore U-box UCLK fixed counter control.
2977 @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL (0x00000C08)
2978 @param EAX Lower 32-bits of MSR value.
2979 @param EDX Upper 32-bits of MSR value.
2981 <b>Example usage</b>
2985 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL);
2986 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL, Msr);
2988 @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.
2990 #define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL 0x00000C08
2994 Package. Uncore U-box UCLK fixed counter.
2996 @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR (0x00000C09)
2997 @param EAX Lower 32-bits of MSR value.
2998 @param EDX Upper 32-bits of MSR value.
3000 <b>Example usage</b>
3004 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR);
3005 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR, Msr);
3007 @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.
3009 #define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR 0x00000C09
3013 Package. Uncore U-box perfmon event select for U-box counter 0.
3015 @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 (0x00000C10)
3016 @param EAX Lower 32-bits of MSR value.
3017 @param EDX Upper 32-bits of MSR value.
3019 <b>Example usage</b>
3023 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0);
3024 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0, Msr);
3026 @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.
3028 #define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 0x00000C10
3032 Package. Uncore U-box perfmon event select for U-box counter 1.
3034 @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 (0x00000C11)
3035 @param EAX Lower 32-bits of MSR value.
3036 @param EDX Upper 32-bits of MSR value.
3038 <b>Example usage</b>
3042 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1);
3043 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1, Msr);
3045 @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.
3047 #define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 0x00000C11
3051 Package. Uncore U-box perfmon counter 0.
3053 @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR0 (0x00000C16)
3054 @param EAX Lower 32-bits of MSR value.
3055 @param EDX Upper 32-bits of MSR value.
3057 <b>Example usage</b>
3061 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0);
3062 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0, Msr);
3064 @note MSR_SANDY_BRIDGE_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.
3066 #define MSR_SANDY_BRIDGE_U_PMON_CTR0 0x00000C16
3070 Package. Uncore U-box perfmon counter 1.
3072 @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR1 (0x00000C17)
3073 @param EAX Lower 32-bits of MSR value.
3074 @param EDX Upper 32-bits of MSR value.
3076 <b>Example usage</b>
3080 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1);
3081 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1, Msr);
3083 @note MSR_SANDY_BRIDGE_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.
3085 #define MSR_SANDY_BRIDGE_U_PMON_CTR1 0x00000C17
3089 Package. Uncore PCU perfmon for PCU-box-wide control.
3091 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL (0x00000C24)
3092 @param EAX Lower 32-bits of MSR value.
3093 @param EDX Upper 32-bits of MSR value.
3095 <b>Example usage</b>
3099 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL);
3100 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL, Msr);
3102 @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.
3104 #define MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL 0x00000C24
3108 Package. Uncore PCU perfmon event select for PCU counter 0.
3110 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 (0x00000C30)
3111 @param EAX Lower 32-bits of MSR value.
3112 @param EDX Upper 32-bits of MSR value.
3114 <b>Example usage</b>
3118 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0);
3119 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0, Msr);
3121 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.
3123 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 0x00000C30
3127 Package. Uncore PCU perfmon event select for PCU counter 1.
3129 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 (0x00000C31)
3130 @param EAX Lower 32-bits of MSR value.
3131 @param EDX Upper 32-bits of MSR value.
3133 <b>Example usage</b>
3137 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1);
3138 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1, Msr);
3140 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.
3142 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 0x00000C31
3146 Package. Uncore PCU perfmon event select for PCU counter 2.
3148 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 (0x00000C32)
3149 @param EAX Lower 32-bits of MSR value.
3150 @param EDX Upper 32-bits of MSR value.
3152 <b>Example usage</b>
3156 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2);
3157 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2, Msr);
3159 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.
3161 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 0x00000C32
3165 Package. Uncore PCU perfmon event select for PCU counter 3.
3167 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 (0x00000C33)
3168 @param EAX Lower 32-bits of MSR value.
3169 @param EDX Upper 32-bits of MSR value.
3171 <b>Example usage</b>
3175 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3);
3176 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3, Msr);
3178 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.
3180 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 0x00000C33
3184 Package. Uncore PCU perfmon box-wide filter.
3186 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER (0x00000C34)
3187 @param EAX Lower 32-bits of MSR value.
3188 @param EDX Upper 32-bits of MSR value.
3190 <b>Example usage</b>
3194 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER);
3195 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER, Msr);
3197 @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.
3199 #define MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER 0x00000C34
3203 Package. Uncore PCU perfmon counter 0.
3205 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR0 (0x00000C36)
3206 @param EAX Lower 32-bits of MSR value.
3207 @param EDX Upper 32-bits of MSR value.
3209 <b>Example usage</b>
3213 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0);
3214 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0, Msr);
3216 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.
3218 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR0 0x00000C36
3222 Package. Uncore PCU perfmon counter 1.
3224 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR1 (0x00000C37)
3225 @param EAX Lower 32-bits of MSR value.
3226 @param EDX Upper 32-bits of MSR value.
3228 <b>Example usage</b>
3232 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1);
3233 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1, Msr);
3235 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.
3237 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR1 0x00000C37
3241 Package. Uncore PCU perfmon counter 2.
3243 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR2 (0x00000C38)
3244 @param EAX Lower 32-bits of MSR value.
3245 @param EDX Upper 32-bits of MSR value.
3247 <b>Example usage</b>
3251 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2);
3252 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2, Msr);
3254 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.
3256 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR2 0x00000C38
3260 Package. Uncore PCU perfmon counter 3.
3262 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR3 (0x00000C39)
3263 @param EAX Lower 32-bits of MSR value.
3264 @param EDX Upper 32-bits of MSR value.
3266 <b>Example usage</b>
3270 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3);
3271 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3, Msr);
3273 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.
3275 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR3 0x00000C39
3279 Package. Uncore C-box 0 perfmon local box wide control.
3281 @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL (0x00000D04)
3282 @param EAX Lower 32-bits of MSR value.
3283 @param EDX Upper 32-bits of MSR value.
3285 <b>Example usage</b>
3289 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL);
3290 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL, Msr);
3292 @note MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.
3294 #define MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL 0x00000D04
3298 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.
3300 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 (0x00000D10)
3301 @param EAX Lower 32-bits of MSR value.
3302 @param EDX Upper 32-bits of MSR value.
3304 <b>Example usage</b>
3308 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0);
3309 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0, Msr);
3311 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.
3313 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 0x00000D10
3317 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.
3319 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 (0x00000D11)
3320 @param EAX Lower 32-bits of MSR value.
3321 @param EDX Upper 32-bits of MSR value.
3323 <b>Example usage</b>
3327 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1);
3328 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1, Msr);
3330 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.
3332 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 0x00000D11
3336 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.
3338 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 (0x00000D12)
3339 @param EAX Lower 32-bits of MSR value.
3340 @param EDX Upper 32-bits of MSR value.
3342 <b>Example usage</b>
3346 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2);
3347 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2, Msr);
3349 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.
3351 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 0x00000D12
3355 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.
3357 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 (0x00000D13)
3358 @param EAX Lower 32-bits of MSR value.
3359 @param EDX Upper 32-bits of MSR value.
3361 <b>Example usage</b>
3365 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3);
3366 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3, Msr);
3368 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.
3370 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 0x00000D13
3374 Package. Uncore C-box 0 perfmon box wide filter.
3376 @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER (0x00000D14)
3377 @param EAX Lower 32-bits of MSR value.
3378 @param EDX Upper 32-bits of MSR value.
3380 <b>Example usage</b>
3384 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER);
3385 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER, Msr);
3387 @note MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER is defined as MSR_C0_PMON_BOX_FILTER in SDM.
3389 #define MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER 0x00000D14
3393 Package. Uncore C-box 0 perfmon counter 0.
3395 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR0 (0x00000D16)
3396 @param EAX Lower 32-bits of MSR value.
3397 @param EDX Upper 32-bits of MSR value.
3399 <b>Example usage</b>
3403 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0);
3404 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0, Msr);
3406 @note MSR_SANDY_BRIDGE_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
3408 #define MSR_SANDY_BRIDGE_C0_PMON_CTR0 0x00000D16
3412 Package. Uncore C-box 0 perfmon counter 1.
3414 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR1 (0x00000D17)
3415 @param EAX Lower 32-bits of MSR value.
3416 @param EDX Upper 32-bits of MSR value.
3418 <b>Example usage</b>
3422 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1);
3423 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1, Msr);
3425 @note MSR_SANDY_BRIDGE_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
3427 #define MSR_SANDY_BRIDGE_C0_PMON_CTR1 0x00000D17
3431 Package. Uncore C-box 0 perfmon counter 2.
3433 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR2 (0x00000D18)
3434 @param EAX Lower 32-bits of MSR value.
3435 @param EDX Upper 32-bits of MSR value.
3437 <b>Example usage</b>
3441 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2);
3442 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2, Msr);
3444 @note MSR_SANDY_BRIDGE_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
3446 #define MSR_SANDY_BRIDGE_C0_PMON_CTR2 0x00000D18
3450 Package. Uncore C-box 0 perfmon counter 3.
3452 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR3 (0x00000D19)
3453 @param EAX Lower 32-bits of MSR value.
3454 @param EDX Upper 32-bits of MSR value.
3456 <b>Example usage</b>
3460 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3);
3461 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3, Msr);
3463 @note MSR_SANDY_BRIDGE_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
3465 #define MSR_SANDY_BRIDGE_C0_PMON_CTR3 0x00000D19
3469 Package. Uncore C-box 1 perfmon local box wide control.
3471 @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL (0x00000D24)
3472 @param EAX Lower 32-bits of MSR value.
3473 @param EDX Upper 32-bits of MSR value.
3475 <b>Example usage</b>
3479 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL);
3480 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL, Msr);
3482 @note MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.
3484 #define MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL 0x00000D24
3488 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.
3490 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 (0x00000D30)
3491 @param EAX Lower 32-bits of MSR value.
3492 @param EDX Upper 32-bits of MSR value.
3494 <b>Example usage</b>
3498 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0);
3499 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0, Msr);
3501 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.
3503 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 0x00000D30
3507 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.
3509 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 (0x00000D31)
3510 @param EAX Lower 32-bits of MSR value.
3511 @param EDX Upper 32-bits of MSR value.
3513 <b>Example usage</b>
3517 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1);
3518 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1, Msr);
3520 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.
3522 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 0x00000D31
3526 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.
3528 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 (0x00000D32)
3529 @param EAX Lower 32-bits of MSR value.
3530 @param EDX Upper 32-bits of MSR value.
3532 <b>Example usage</b>
3536 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2);
3537 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2, Msr);
3539 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.
3541 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 0x00000D32
3545 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.
3547 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 (0x00000D33)
3548 @param EAX Lower 32-bits of MSR value.
3549 @param EDX Upper 32-bits of MSR value.
3551 <b>Example usage</b>
3555 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3);
3556 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3, Msr);
3558 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.
3560 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 0x00000D33
3564 Package. Uncore C-box 1 perfmon box wide filter.
3566 @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER (0x00000D34)
3567 @param EAX Lower 32-bits of MSR value.
3568 @param EDX Upper 32-bits of MSR value.
3570 <b>Example usage</b>
3574 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER);
3575 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER, Msr);
3577 @note MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER is defined as MSR_C1_PMON_BOX_FILTER in SDM.
3579 #define MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER 0x00000D34
3583 Package. Uncore C-box 1 perfmon counter 0.
3585 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR0 (0x00000D36)
3586 @param EAX Lower 32-bits of MSR value.
3587 @param EDX Upper 32-bits of MSR value.
3589 <b>Example usage</b>
3593 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0);
3594 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0, Msr);
3596 @note MSR_SANDY_BRIDGE_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
3598 #define MSR_SANDY_BRIDGE_C1_PMON_CTR0 0x00000D36
3602 Package. Uncore C-box 1 perfmon counter 1.
3604 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR1 (0x00000D37)
3605 @param EAX Lower 32-bits of MSR value.
3606 @param EDX Upper 32-bits of MSR value.
3608 <b>Example usage</b>
3612 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1);
3613 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1, Msr);
3615 @note MSR_SANDY_BRIDGE_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
3617 #define MSR_SANDY_BRIDGE_C1_PMON_CTR1 0x00000D37
3621 Package. Uncore C-box 1 perfmon counter 2.
3623 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR2 (0x00000D38)
3624 @param EAX Lower 32-bits of MSR value.
3625 @param EDX Upper 32-bits of MSR value.
3627 <b>Example usage</b>
3631 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2);
3632 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2, Msr);
3634 @note MSR_SANDY_BRIDGE_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
3636 #define MSR_SANDY_BRIDGE_C1_PMON_CTR2 0x00000D38
3640 Package. Uncore C-box 1 perfmon counter 3.
3642 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR3 (0x00000D39)
3643 @param EAX Lower 32-bits of MSR value.
3644 @param EDX Upper 32-bits of MSR value.
3646 <b>Example usage</b>
3650 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3);
3651 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3, Msr);
3653 @note MSR_SANDY_BRIDGE_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
3655 #define MSR_SANDY_BRIDGE_C1_PMON_CTR3 0x00000D39
3659 Package. Uncore C-box 2 perfmon local box wide control.
3661 @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL (0x00000D44)
3662 @param EAX Lower 32-bits of MSR value.
3663 @param EDX Upper 32-bits of MSR value.
3665 <b>Example usage</b>
3669 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL);
3670 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL, Msr);
3672 @note MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.
3674 #define MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL 0x00000D44
3678 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.
3680 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 (0x00000D50)
3681 @param EAX Lower 32-bits of MSR value.
3682 @param EDX Upper 32-bits of MSR value.
3684 <b>Example usage</b>
3688 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0);
3689 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0, Msr);
3691 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.
3693 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 0x00000D50
3697 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.
3699 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 (0x00000D51)
3700 @param EAX Lower 32-bits of MSR value.
3701 @param EDX Upper 32-bits of MSR value.
3703 <b>Example usage</b>
3707 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1);
3708 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1, Msr);
3710 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.
3712 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 0x00000D51
3716 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.
3718 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 (0x00000D52)
3719 @param EAX Lower 32-bits of MSR value.
3720 @param EDX Upper 32-bits of MSR value.
3722 <b>Example usage</b>
3726 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2);
3727 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2, Msr);
3729 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.
3731 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 0x00000D52
3735 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.
3737 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 (0x00000D53)
3738 @param EAX Lower 32-bits of MSR value.
3739 @param EDX Upper 32-bits of MSR value.
3741 <b>Example usage</b>
3745 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3);
3746 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3, Msr);
3748 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.
3750 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 0x00000D53
3754 Package. Uncore C-box 2 perfmon box wide filter.
3756 @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER (0x00000D54)
3757 @param EAX Lower 32-bits of MSR value.
3758 @param EDX Upper 32-bits of MSR value.
3760 <b>Example usage</b>
3764 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER);
3765 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER, Msr);
3767 @note MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER is defined as MSR_C2_PMON_BOX_FILTER in SDM.
3769 #define MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER 0x00000D54
3773 Package. Uncore C-box 2 perfmon counter 0.
3775 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR0 (0x00000D56)
3776 @param EAX Lower 32-bits of MSR value.
3777 @param EDX Upper 32-bits of MSR value.
3779 <b>Example usage</b>
3783 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0);
3784 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0, Msr);
3786 @note MSR_SANDY_BRIDGE_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
3788 #define MSR_SANDY_BRIDGE_C2_PMON_CTR0 0x00000D56
3792 Package. Uncore C-box 2 perfmon counter 1.
3794 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR1 (0x00000D57)
3795 @param EAX Lower 32-bits of MSR value.
3796 @param EDX Upper 32-bits of MSR value.
3798 <b>Example usage</b>
3802 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1);
3803 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1, Msr);
3805 @note MSR_SANDY_BRIDGE_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
3807 #define MSR_SANDY_BRIDGE_C2_PMON_CTR1 0x00000D57
3811 Package. Uncore C-box 2 perfmon counter 2.
3813 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR2 (0x00000D58)
3814 @param EAX Lower 32-bits of MSR value.
3815 @param EDX Upper 32-bits of MSR value.
3817 <b>Example usage</b>
3821 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2);
3822 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2, Msr);
3824 @note MSR_SANDY_BRIDGE_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
3826 #define MSR_SANDY_BRIDGE_C2_PMON_CTR2 0x00000D58
3830 Package. Uncore C-box 2 perfmon counter 3.
3832 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR3 (0x00000D59)
3833 @param EAX Lower 32-bits of MSR value.
3834 @param EDX Upper 32-bits of MSR value.
3836 <b>Example usage</b>
3840 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3);
3841 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3, Msr);
3843 @note MSR_SANDY_BRIDGE_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
3845 #define MSR_SANDY_BRIDGE_C2_PMON_CTR3 0x00000D59
3849 Package. Uncore C-box 3 perfmon local box wide control.
3851 @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL (0x00000D64)
3852 @param EAX Lower 32-bits of MSR value.
3853 @param EDX Upper 32-bits of MSR value.
3855 <b>Example usage</b>
3859 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL);
3860 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL, Msr);
3862 @note MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.
3864 #define MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL 0x00000D64
3868 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.
3870 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 (0x00000D70)
3871 @param EAX Lower 32-bits of MSR value.
3872 @param EDX Upper 32-bits of MSR value.
3874 <b>Example usage</b>
3878 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0);
3879 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0, Msr);
3881 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.
3883 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 0x00000D70
3887 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.
3889 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 (0x00000D71)
3890 @param EAX Lower 32-bits of MSR value.
3891 @param EDX Upper 32-bits of MSR value.
3893 <b>Example usage</b>
3897 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1);
3898 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1, Msr);
3900 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.
3902 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 0x00000D71
3906 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.
3908 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 (0x00000D72)
3909 @param EAX Lower 32-bits of MSR value.
3910 @param EDX Upper 32-bits of MSR value.
3912 <b>Example usage</b>
3916 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2);
3917 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2, Msr);
3919 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.
3921 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 0x00000D72
3925 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.
3927 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 (0x00000D73)
3928 @param EAX Lower 32-bits of MSR value.
3929 @param EDX Upper 32-bits of MSR value.
3931 <b>Example usage</b>
3935 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3);
3936 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3, Msr);
3938 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.
3940 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 0x00000D73
3944 Package. Uncore C-box 3 perfmon box wide filter.
3946 @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER (0x00000D74)
3947 @param EAX Lower 32-bits of MSR value.
3948 @param EDX Upper 32-bits of MSR value.
3950 <b>Example usage</b>
3954 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER);
3955 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER, Msr);
3957 @note MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER is defined as MSR_C3_PMON_BOX_FILTER in SDM.
3959 #define MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER 0x00000D74
3963 Package. Uncore C-box 3 perfmon counter 0.
3965 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR0 (0x00000D76)
3966 @param EAX Lower 32-bits of MSR value.
3967 @param EDX Upper 32-bits of MSR value.
3969 <b>Example usage</b>
3973 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0);
3974 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0, Msr);
3976 @note MSR_SANDY_BRIDGE_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
3978 #define MSR_SANDY_BRIDGE_C3_PMON_CTR0 0x00000D76
3982 Package. Uncore C-box 3 perfmon counter 1.
3984 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR1 (0x00000D77)
3985 @param EAX Lower 32-bits of MSR value.
3986 @param EDX Upper 32-bits of MSR value.
3988 <b>Example usage</b>
3992 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1);
3993 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1, Msr);
3995 @note MSR_SANDY_BRIDGE_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
3997 #define MSR_SANDY_BRIDGE_C3_PMON_CTR1 0x00000D77
4001 Package. Uncore C-box 3 perfmon counter 2.
4003 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR2 (0x00000D78)
4004 @param EAX Lower 32-bits of MSR value.
4005 @param EDX Upper 32-bits of MSR value.
4007 <b>Example usage</b>
4011 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2);
4012 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2, Msr);
4014 @note MSR_SANDY_BRIDGE_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
4016 #define MSR_SANDY_BRIDGE_C3_PMON_CTR2 0x00000D78
4020 Package. Uncore C-box 3 perfmon counter 3.
4022 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR3 (0x00000D79)
4023 @param EAX Lower 32-bits of MSR value.
4024 @param EDX Upper 32-bits of MSR value.
4026 <b>Example usage</b>
4030 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3);
4031 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3, Msr);
4033 @note MSR_SANDY_BRIDGE_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
4035 #define MSR_SANDY_BRIDGE_C3_PMON_CTR3 0x00000D79
4039 Package. Uncore C-box 4 perfmon local box wide control.
4041 @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL (0x00000D84)
4042 @param EAX Lower 32-bits of MSR value.
4043 @param EDX Upper 32-bits of MSR value.
4045 <b>Example usage</b>
4049 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL);
4050 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL, Msr);
4052 @note MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.
4054 #define MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL 0x00000D84
4058 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.
4060 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 (0x00000D90)
4061 @param EAX Lower 32-bits of MSR value.
4062 @param EDX Upper 32-bits of MSR value.
4064 <b>Example usage</b>
4068 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0);
4069 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0, Msr);
4071 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.
4073 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 0x00000D90
4077 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.
4079 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 (0x00000D91)
4080 @param EAX Lower 32-bits of MSR value.
4081 @param EDX Upper 32-bits of MSR value.
4083 <b>Example usage</b>
4087 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1);
4088 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1, Msr);
4090 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.
4092 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 0x00000D91
4096 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.
4098 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 (0x00000D92)
4099 @param EAX Lower 32-bits of MSR value.
4100 @param EDX Upper 32-bits of MSR value.
4102 <b>Example usage</b>
4106 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2);
4107 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2, Msr);
4109 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.
4111 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 0x00000D92
4115 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.
4117 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 (0x00000D93)
4118 @param EAX Lower 32-bits of MSR value.
4119 @param EDX Upper 32-bits of MSR value.
4121 <b>Example usage</b>
4125 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3);
4126 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3, Msr);
4128 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.
4130 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 0x00000D93
4134 Package. Uncore C-box 4 perfmon box wide filter.
4136 @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER (0x00000D94)
4137 @param EAX Lower 32-bits of MSR value.
4138 @param EDX Upper 32-bits of MSR value.
4140 <b>Example usage</b>
4144 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER);
4145 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER, Msr);
4147 @note MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER is defined as MSR_C4_PMON_BOX_FILTER in SDM.
4149 #define MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER 0x00000D94
4153 Package. Uncore C-box 4 perfmon counter 0.
4155 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR0 (0x00000D96)
4156 @param EAX Lower 32-bits of MSR value.
4157 @param EDX Upper 32-bits of MSR value.
4159 <b>Example usage</b>
4163 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0);
4164 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0, Msr);
4166 @note MSR_SANDY_BRIDGE_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
4168 #define MSR_SANDY_BRIDGE_C4_PMON_CTR0 0x00000D96
4172 Package. Uncore C-box 4 perfmon counter 1.
4174 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR1 (0x00000D97)
4175 @param EAX Lower 32-bits of MSR value.
4176 @param EDX Upper 32-bits of MSR value.
4178 <b>Example usage</b>
4182 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1);
4183 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1, Msr);
4185 @note MSR_SANDY_BRIDGE_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
4187 #define MSR_SANDY_BRIDGE_C4_PMON_CTR1 0x00000D97
4191 Package. Uncore C-box 4 perfmon counter 2.
4193 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR2 (0x00000D98)
4194 @param EAX Lower 32-bits of MSR value.
4195 @param EDX Upper 32-bits of MSR value.
4197 <b>Example usage</b>
4201 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2);
4202 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2, Msr);
4204 @note MSR_SANDY_BRIDGE_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
4206 #define MSR_SANDY_BRIDGE_C4_PMON_CTR2 0x00000D98
4210 Package. Uncore C-box 4 perfmon counter 3.
4212 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR3 (0x00000D99)
4213 @param EAX Lower 32-bits of MSR value.
4214 @param EDX Upper 32-bits of MSR value.
4216 <b>Example usage</b>
4220 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3);
4221 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3, Msr);
4223 @note MSR_SANDY_BRIDGE_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
4225 #define MSR_SANDY_BRIDGE_C4_PMON_CTR3 0x00000D99
4229 Package. Uncore C-box 5 perfmon local box wide control.
4231 @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL (0x00000DA4)
4232 @param EAX Lower 32-bits of MSR value.
4233 @param EDX Upper 32-bits of MSR value.
4235 <b>Example usage</b>
4239 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL);
4240 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL, Msr);
4242 @note MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.
4244 #define MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL 0x00000DA4
4248 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.
4250 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 (0x00000DB0)
4251 @param EAX Lower 32-bits of MSR value.
4252 @param EDX Upper 32-bits of MSR value.
4254 <b>Example usage</b>
4258 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0);
4259 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0, Msr);
4261 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.
4263 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 0x00000DB0
4267 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.
4269 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 (0x00000DB1)
4270 @param EAX Lower 32-bits of MSR value.
4271 @param EDX Upper 32-bits of MSR value.
4273 <b>Example usage</b>
4277 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1);
4278 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1, Msr);
4280 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.
4282 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 0x00000DB1
4286 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.
4288 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 (0x00000DB2)
4289 @param EAX Lower 32-bits of MSR value.
4290 @param EDX Upper 32-bits of MSR value.
4292 <b>Example usage</b>
4296 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2);
4297 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2, Msr);
4299 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.
4301 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 0x00000DB2
4305 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.
4307 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 (0x00000DB3)
4308 @param EAX Lower 32-bits of MSR value.
4309 @param EDX Upper 32-bits of MSR value.
4311 <b>Example usage</b>
4315 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3);
4316 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3, Msr);
4318 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.
4320 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 0x00000DB3
4324 Package. Uncore C-box 5 perfmon box wide filter.
4326 @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER (0x00000DB4)
4327 @param EAX Lower 32-bits of MSR value.
4328 @param EDX Upper 32-bits of MSR value.
4330 <b>Example usage</b>
4334 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER);
4335 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER, Msr);
4337 @note MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER is defined as MSR_C5_PMON_BOX_FILTER in SDM.
4339 #define MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER 0x00000DB4
4343 Package. Uncore C-box 5 perfmon counter 0.
4345 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR0 (0x00000DB6)
4346 @param EAX Lower 32-bits of MSR value.
4347 @param EDX Upper 32-bits of MSR value.
4349 <b>Example usage</b>
4353 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0);
4354 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0, Msr);
4356 @note MSR_SANDY_BRIDGE_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
4358 #define MSR_SANDY_BRIDGE_C5_PMON_CTR0 0x00000DB6
4362 Package. Uncore C-box 5 perfmon counter 1.
4364 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR1 (0x00000DB7)
4365 @param EAX Lower 32-bits of MSR value.
4366 @param EDX Upper 32-bits of MSR value.
4368 <b>Example usage</b>
4372 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1);
4373 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1, Msr);
4375 @note MSR_SANDY_BRIDGE_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
4377 #define MSR_SANDY_BRIDGE_C5_PMON_CTR1 0x00000DB7
4381 Package. Uncore C-box 5 perfmon counter 2.
4383 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR2 (0x00000DB8)
4384 @param EAX Lower 32-bits of MSR value.
4385 @param EDX Upper 32-bits of MSR value.
4387 <b>Example usage</b>
4391 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2);
4392 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2, Msr);
4394 @note MSR_SANDY_BRIDGE_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
4396 #define MSR_SANDY_BRIDGE_C5_PMON_CTR2 0x00000DB8
4400 Package. Uncore C-box 5 perfmon counter 3.
4402 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR3 (0x00000DB9)
4403 @param EAX Lower 32-bits of MSR value.
4404 @param EDX Upper 32-bits of MSR value.
4406 <b>Example usage</b>
4410 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3);
4411 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3, Msr);
4413 @note MSR_SANDY_BRIDGE_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
4415 #define MSR_SANDY_BRIDGE_C5_PMON_CTR3 0x00000DB9
4419 Package. Uncore C-box 6 perfmon local box wide control.
4421 @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL (0x00000DC4)
4422 @param EAX Lower 32-bits of MSR value.
4423 @param EDX Upper 32-bits of MSR value.
4425 <b>Example usage</b>
4429 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL);
4430 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL, Msr);
4432 @note MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.
4434 #define MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL 0x00000DC4
4438 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.
4440 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 (0x00000DD0)
4441 @param EAX Lower 32-bits of MSR value.
4442 @param EDX Upper 32-bits of MSR value.
4444 <b>Example usage</b>
4448 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0);
4449 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0, Msr);
4451 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.
4453 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 0x00000DD0
4457 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.
4459 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 (0x00000DD1)
4460 @param EAX Lower 32-bits of MSR value.
4461 @param EDX Upper 32-bits of MSR value.
4463 <b>Example usage</b>
4467 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1);
4468 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1, Msr);
4470 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.
4472 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 0x00000DD1
4476 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.
4478 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 (0x00000DD2)
4479 @param EAX Lower 32-bits of MSR value.
4480 @param EDX Upper 32-bits of MSR value.
4482 <b>Example usage</b>
4486 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2);
4487 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2, Msr);
4489 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.
4491 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 0x00000DD2
4495 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.
4497 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 (0x00000DD3)
4498 @param EAX Lower 32-bits of MSR value.
4499 @param EDX Upper 32-bits of MSR value.
4501 <b>Example usage</b>
4505 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3);
4506 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3, Msr);
4508 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.
4510 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 0x00000DD3
4514 Package. Uncore C-box 6 perfmon box wide filter.
4516 @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER (0x00000DD4)
4517 @param EAX Lower 32-bits of MSR value.
4518 @param EDX Upper 32-bits of MSR value.
4520 <b>Example usage</b>
4524 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER);
4525 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER, Msr);
4527 @note MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER is defined as MSR_C6_PMON_BOX_FILTER in SDM.
4529 #define MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER 0x00000DD4
4533 Package. Uncore C-box 6 perfmon counter 0.
4535 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR0 (0x00000DD6)
4536 @param EAX Lower 32-bits of MSR value.
4537 @param EDX Upper 32-bits of MSR value.
4539 <b>Example usage</b>
4543 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0);
4544 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0, Msr);
4546 @note MSR_SANDY_BRIDGE_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
4548 #define MSR_SANDY_BRIDGE_C6_PMON_CTR0 0x00000DD6
4552 Package. Uncore C-box 6 perfmon counter 1.
4554 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR1 (0x00000DD7)
4555 @param EAX Lower 32-bits of MSR value.
4556 @param EDX Upper 32-bits of MSR value.
4558 <b>Example usage</b>
4562 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1);
4563 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1, Msr);
4565 @note MSR_SANDY_BRIDGE_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
4567 #define MSR_SANDY_BRIDGE_C6_PMON_CTR1 0x00000DD7
4571 Package. Uncore C-box 6 perfmon counter 2.
4573 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR2 (0x00000DD8)
4574 @param EAX Lower 32-bits of MSR value.
4575 @param EDX Upper 32-bits of MSR value.
4577 <b>Example usage</b>
4581 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2);
4582 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2, Msr);
4584 @note MSR_SANDY_BRIDGE_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
4586 #define MSR_SANDY_BRIDGE_C6_PMON_CTR2 0x00000DD8
4590 Package. Uncore C-box 6 perfmon counter 3.
4592 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR3 (0x00000DD9)
4593 @param EAX Lower 32-bits of MSR value.
4594 @param EDX Upper 32-bits of MSR value.
4596 <b>Example usage</b>
4600 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3);
4601 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3, Msr);
4603 @note MSR_SANDY_BRIDGE_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
4605 #define MSR_SANDY_BRIDGE_C6_PMON_CTR3 0x00000DD9
4609 Package. Uncore C-box 7 perfmon local box wide control.
4611 @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL (0x00000DE4)
4612 @param EAX Lower 32-bits of MSR value.
4613 @param EDX Upper 32-bits of MSR value.
4615 <b>Example usage</b>
4619 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL);
4620 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL, Msr);
4622 @note MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.
4624 #define MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL 0x00000DE4
4628 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.
4630 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 (0x00000DF0)
4631 @param EAX Lower 32-bits of MSR value.
4632 @param EDX Upper 32-bits of MSR value.
4634 <b>Example usage</b>
4638 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0);
4639 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0, Msr);
4641 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.
4643 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 0x00000DF0
4647 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.
4649 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 (0x00000DF1)
4650 @param EAX Lower 32-bits of MSR value.
4651 @param EDX Upper 32-bits of MSR value.
4653 <b>Example usage</b>
4657 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1);
4658 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1, Msr);
4660 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.
4662 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 0x00000DF1
4666 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.
4668 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 (0x00000DF2)
4669 @param EAX Lower 32-bits of MSR value.
4670 @param EDX Upper 32-bits of MSR value.
4672 <b>Example usage</b>
4676 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2);
4677 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2, Msr);
4679 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.
4681 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 0x00000DF2
4685 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.
4687 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 (0x00000DF3)
4688 @param EAX Lower 32-bits of MSR value.
4689 @param EDX Upper 32-bits of MSR value.
4691 <b>Example usage</b>
4695 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3);
4696 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3, Msr);
4698 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.
4700 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 0x00000DF3
4704 Package. Uncore C-box 7 perfmon box wide filter.
4706 @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER (0x00000DF4)
4707 @param EAX Lower 32-bits of MSR value.
4708 @param EDX Upper 32-bits of MSR value.
4710 <b>Example usage</b>
4714 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER);
4715 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER, Msr);
4717 @note MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER is defined as MSR_C7_PMON_BOX_FILTER in SDM.
4719 #define MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER 0x00000DF4
4723 Package. Uncore C-box 7 perfmon counter 0.
4725 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR0 (0x00000DF6)
4726 @param EAX Lower 32-bits of MSR value.
4727 @param EDX Upper 32-bits of MSR value.
4729 <b>Example usage</b>
4733 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0);
4734 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0, Msr);
4736 @note MSR_SANDY_BRIDGE_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
4738 #define MSR_SANDY_BRIDGE_C7_PMON_CTR0 0x00000DF6
4742 Package. Uncore C-box 7 perfmon counter 1.
4744 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR1 (0x00000DF7)
4745 @param EAX Lower 32-bits of MSR value.
4746 @param EDX Upper 32-bits of MSR value.
4748 <b>Example usage</b>
4752 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1);
4753 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1, Msr);
4755 @note MSR_SANDY_BRIDGE_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
4757 #define MSR_SANDY_BRIDGE_C7_PMON_CTR1 0x00000DF7
4761 Package. Uncore C-box 7 perfmon counter 2.
4763 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR2 (0x00000DF8)
4764 @param EAX Lower 32-bits of MSR value.
4765 @param EDX Upper 32-bits of MSR value.
4767 <b>Example usage</b>
4771 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2);
4772 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2, Msr);
4774 @note MSR_SANDY_BRIDGE_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
4776 #define MSR_SANDY_BRIDGE_C7_PMON_CTR2 0x00000DF8
4780 Package. Uncore C-box 7 perfmon counter 3.
4782 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR3 (0x00000DF9)
4783 @param EAX Lower 32-bits of MSR value.
4784 @param EDX Upper 32-bits of MSR value.
4786 <b>Example usage</b>
4790 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3);
4791 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3, Msr);
4793 @note MSR_SANDY_BRIDGE_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
4795 #define MSR_SANDY_BRIDGE_C7_PMON_CTR3 0x00000DF9