2 MSR Definitions for Intel processors based on the Sandy Bridge microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-8.
24 #ifndef __SANDY_BRIDGE_MSR_H__
25 #define __SANDY_BRIDGE_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Thread. SMI Counter (R/O).
32 @param ECX MSR_SANDY_BRIDGE_SMI_COUNT (0x00000034)
33 @param EAX Lower 32-bits of MSR value.
34 Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.
35 @param EDX Upper 32-bits of MSR value.
36 Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.
40 MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER Msr;
42 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_SMI_COUNT);
44 @note MSR_SANDY_BRIDGE_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
46 #define MSR_SANDY_BRIDGE_SMI_COUNT 0x00000034
49 MSR information returned for MSR index #MSR_SANDY_BRIDGE_SMI_COUNT
53 /// Individual bit fields
57 /// [Bits 31:0] SMI Count (R/O) Count SMIs.
63 /// All bit fields as a 32-bit value
67 /// All bit fields as a 64-bit value
70 } MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER
;
74 Package. See http://biosbits.org.
76 @param ECX MSR_SANDY_BRIDGE_PLATFORM_INFO (0x000000CE)
77 @param EAX Lower 32-bits of MSR value.
78 Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.
79 @param EDX Upper 32-bits of MSR value.
80 Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.
84 MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER Msr;
86 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO);
87 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
89 @note MSR_SANDY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
91 #define MSR_SANDY_BRIDGE_PLATFORM_INFO 0x000000CE
94 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PLATFORM_INFO
98 /// Individual bit fields
103 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
104 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
107 UINT32 MaximumNonTurboRatio
:8;
110 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
111 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
112 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
113 /// Turbo mode is disabled.
117 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
118 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
119 /// and when set to 0, indicates TDP Limit for Turbo mode is not
126 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
127 /// minimum ratio (maximum efficiency) that the processor can operates, in
130 UINT32 MaximumEfficiencyRatio
:8;
134 /// All bit fields as a 64-bit value
137 } MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER
;
141 Core. C-State Configuration Control (R/W) Note: C-state values are
142 processor specific C-state code names, unrelated to MWAIT extension C-state
143 parameters or ACPI CStates. See http://biosbits.org.
145 @param ECX MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)
146 @param EAX Lower 32-bits of MSR value.
147 Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
148 @param EDX Upper 32-bits of MSR value.
149 Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
153 MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
155 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL);
156 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
158 @note MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
160 #define MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2
163 MSR information returned for MSR index
164 #MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL
168 /// Individual bit fields
172 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
173 /// processor-specific C-state code name (consuming the least power). for
174 /// the package. The default is set as factory-configured package C-state
175 /// limit. The following C-state code name encodings are supported: 000b:
176 /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:
177 /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:
178 /// This field cannot be used to limit package C-state to C3.
183 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
184 /// IO_read instructions sent to IO register specified by
185 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
190 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
191 /// until next reset.
196 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor
197 /// will conditionally demote C6/C7 requests to C3 based on uncore
198 /// auto-demote information.
200 UINT32 C3AutoDemotion
:1;
202 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor
203 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
204 /// auto-demote information.
206 UINT32 C1AutoDemotion
:1;
208 /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from
211 UINT32 C3Undemotion
:1;
213 /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from
216 UINT32 C1Undemotion
:1;
221 /// All bit fields as a 32-bit value
225 /// All bit fields as a 64-bit value
228 } MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER
;
232 Core. Power Management IO Redirection in C-state (R/W) See
235 @param ECX MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE (0x000000E4)
236 @param EAX Lower 32-bits of MSR value.
237 Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.
238 @param EDX Upper 32-bits of MSR value.
239 Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.
243 MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER Msr;
245 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE);
246 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE, Msr.Uint64);
248 @note MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
250 #define MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE 0x000000E4
253 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE
257 /// Individual bit fields
261 /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address
262 /// visible to software for IO redirection. If IO MWAIT Redirection is
263 /// enabled, reads to this address will be consumed by the power
264 /// management logic and decoded to MWAIT instructions. When IO port
265 /// address redirection is enabled, this is the IO port address reported
266 /// to the OS/software.
270 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
271 /// maximum C-State code name to be included when IO read to MWAIT
272 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3
273 /// is the max C-State to include 001b - C6 is the max C-State to include
274 /// 010b - C7 is the max C-State to include.
276 UINT32 CStateRange
:3;
281 /// All bit fields as a 32-bit value
285 /// All bit fields as a 64-bit value
288 } MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER
;
292 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
293 handler to handle unsuccessful read of this MSR.
295 @param ECX MSR_SANDY_BRIDGE_FEATURE_CONFIG (0x0000013C)
296 @param EAX Lower 32-bits of MSR value.
297 Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.
298 @param EDX Upper 32-bits of MSR value.
299 Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.
303 MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER Msr;
305 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);
306 AsmWriteMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG, Msr.Uint64);
308 @note MSR_SANDY_BRIDGE_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
310 #define MSR_SANDY_BRIDGE_FEATURE_CONFIG 0x0000013C
313 MSR information returned for MSR index #MSR_SANDY_BRIDGE_FEATURE_CONFIG
317 /// Individual bit fields
321 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
322 /// MSR, the configuration of AES instruction set availability is as
323 /// follows: 11b: AES instructions are not available until next RESET.
324 /// otherwise, AES instructions are available. Note, AES instruction set
325 /// is not available if read is unsuccessful. If the configuration is not
326 /// 01b, AES instruction can be mis-configured if a privileged agent
327 /// unintentionally writes 11b.
329 UINT32 AESConfiguration
:2;
334 /// All bit fields as a 32-bit value
338 /// All bit fields as a 64-bit value
341 } MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER
;
345 Core. See Table 35-2; If CPUID.0AH:EAX[15:8] = 8.
347 @param ECX MSR_SANDY_BRIDGE_IA32_PERFEVTSELn
348 @param EAX Lower 32-bits of MSR value.
349 @param EDX Upper 32-bits of MSR value.
355 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4);
356 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4, Msr);
358 @note MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 is defined as IA32_PERFEVTSEL4 in SDM.
359 MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 is defined as IA32_PERFEVTSEL5 in SDM.
360 MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 is defined as IA32_PERFEVTSEL6 in SDM.
361 MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 is defined as IA32_PERFEVTSEL7 in SDM.
364 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 0x0000018A
365 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 0x0000018B
366 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 0x0000018C
367 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 0x0000018D
374 @param ECX MSR_SANDY_BRIDGE_PERF_STATUS (0x00000198)
375 @param EAX Lower 32-bits of MSR value.
376 Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.
377 @param EDX Upper 32-bits of MSR value.
378 Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.
382 MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER Msr;
384 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS);
385 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS, Msr.Uint64);
387 @note MSR_SANDY_BRIDGE_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
389 #define MSR_SANDY_BRIDGE_PERF_STATUS 0x00000198
392 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PERF_STATUS
396 /// Individual bit fields
401 /// [Bits 47:32] Core Voltage (R/O) P-state core voltage can be computed
402 /// by MSR_PERF_STATUS[37:32] * (float) 1/(2^13).
404 UINT32 CoreVoltage
:16;
408 /// All bit fields as a 64-bit value
411 } MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER
;
415 Thread. Clock Modulation (R/W) See Table 35-2 IA32_CLOCK_MODULATION MSR was
416 originally named IA32_THERM_CONTROL MSR.
418 @param ECX MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION (0x0000019A)
419 @param EAX Lower 32-bits of MSR value.
420 Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.
421 @param EDX Upper 32-bits of MSR value.
422 Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.
426 MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER Msr;
428 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION);
429 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, Msr.Uint64);
431 @note MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.
433 #define MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION 0x0000019A
436 MSR information returned for MSR index
437 #MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION
441 /// Individual bit fields
445 /// [Bits 3:0] On demand Clock Modulation Duty Cycle (R/W) In 6.25%
448 UINT32 OnDemandClockModulationDutyCycle
:4;
450 /// [Bit 4] On demand Clock Modulation Enable (R/W).
452 UINT32 OnDemandClockModulationEnable
:1;
457 /// All bit fields as a 32-bit value
461 /// All bit fields as a 64-bit value
464 } MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER
;
468 Enable Misc. Processor Features (R/W) Allows a variety of processor
469 functions to be enabled and disabled.
471 @param ECX MSR_SANDY_BRIDGE_IA32_MISC_ENABLE (0x000001A0)
472 @param EAX Lower 32-bits of MSR value.
473 Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.
474 @param EDX Upper 32-bits of MSR value.
475 Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.
479 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER Msr;
481 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE);
482 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE, Msr.Uint64);
484 @note MSR_SANDY_BRIDGE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
486 #define MSR_SANDY_BRIDGE_IA32_MISC_ENABLE 0x000001A0
489 MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MISC_ENABLE
493 /// Individual bit fields
497 /// [Bit 0] Thread. Fast-Strings Enable See Table 35-2.
499 UINT32 FastStrings
:1;
502 /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 35-2.
504 UINT32 PerformanceMonitoring
:1;
507 /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 35-2.
511 /// [Bit 12] Thread. Precise Event Based Sampling Unavailable (RO) See
517 /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
523 /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 35-2.
528 /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 35-2.
530 UINT32 LimitCpuidMaxval
:1;
532 /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 35-2.
534 UINT32 xTPR_Message_Disable
:1;
538 /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 35-2.
543 /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors
544 /// that support Intel Turbo Boost Technology, the turbo mode feature is
545 /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
546 /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
547 /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
548 /// the power-on default value is used by BIOS to detect hardware support
549 /// of turbo mode. If power-on default value is 1, turbo mode is available
550 /// in the processor. If power-on default value is 0, turbo mode is not
553 UINT32 TurboModeDisable
:1;
557 /// All bit fields as a 64-bit value
560 } MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER
;
566 @param ECX MSR_SANDY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)
567 @param EAX Lower 32-bits of MSR value.
568 Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
569 @param EDX Upper 32-bits of MSR value.
570 Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
574 MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr;
576 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET);
577 AsmWriteMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);
579 @note MSR_SANDY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
581 #define MSR_SANDY_BRIDGE_TEMPERATURE_TARGET 0x000001A2
584 MSR information returned for MSR index #MSR_SANDY_BRIDGE_TEMPERATURE_TARGET
588 /// Individual bit fields
593 /// [Bits 23:16] Temperature Target (R) The minimum temperature at which
594 /// PROCHOT# will be asserted. The value is degree C.
596 UINT32 TemperatureTarget
:8;
601 /// All bit fields as a 32-bit value
605 /// All bit fields as a 64-bit value
608 } MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER
;
612 Miscellaneous Feature Control (R/W).
614 @param ECX MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL (0x000001A4)
615 @param EAX Lower 32-bits of MSR value.
616 Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.
617 @param EDX Upper 32-bits of MSR value.
618 Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.
622 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER Msr;
624 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL);
625 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL, Msr.Uint64);
627 @note MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
629 #define MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL 0x000001A4
632 MSR information returned for MSR index #MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL
636 /// Individual bit fields
640 /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
641 /// L2 hardware prefetcher, which fetches additional lines of code or data
642 /// into the L2 cache.
644 UINT32 L2HardwarePrefetcherDisable
:1;
646 /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,
647 /// disables the adjacent cache line prefetcher, which fetches the cache
648 /// line that comprises a cache line pair (128 bytes).
650 UINT32 L2AdjacentCacheLinePrefetcherDisable
:1;
652 /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables
653 /// the L1 data cache prefetcher, which fetches the next cache line into
656 UINT32 DCUHardwarePrefetcherDisable
:1;
658 /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1
659 /// data cache IP prefetcher, which uses sequential load history (based on
660 /// instruction Pointer of previous loads) to determine whether to
661 /// prefetch additional lines.
663 UINT32 DCUIPPrefetcherDisable
:1;
668 /// All bit fields as a 32-bit value
672 /// All bit fields as a 64-bit value
675 } MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER
;
679 Thread. Offcore Response Event Select Register (R/W).
681 @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_0 (0x000001A6)
682 @param EAX Lower 32-bits of MSR value.
683 @param EDX Upper 32-bits of MSR value.
689 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0);
690 AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0, Msr);
692 @note MSR_SANDY_BRIDGE_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
694 #define MSR_SANDY_BRIDGE_OFFCORE_RSP_0 0x000001A6
698 Thread. Offcore Response Event Select Register (R/W).
700 @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_1 (0x000001A7)
701 @param EAX Lower 32-bits of MSR value.
702 @param EDX Upper 32-bits of MSR value.
708 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1);
709 AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1, Msr);
711 @note MSR_SANDY_BRIDGE_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
713 #define MSR_SANDY_BRIDGE_OFFCORE_RSP_1 0x000001A7
717 See http://biosbits.org.
719 @param ECX MSR_SANDY_BRIDGE_MISC_PWR_MGMT (0x000001AA)
720 @param EAX Lower 32-bits of MSR value.
721 @param EDX Upper 32-bits of MSR value.
727 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT);
728 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT, Msr);
730 @note MSR_SANDY_BRIDGE_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.
732 #define MSR_SANDY_BRIDGE_MISC_PWR_MGMT 0x000001AA
736 Thread. Last Branch Record Filtering Select Register (R/W) See Section
737 17.6.2, "Filtering of Last Branch Records.".
739 @param ECX MSR_SANDY_BRIDGE_LBR_SELECT (0x000001C8)
740 @param EAX Lower 32-bits of MSR value.
741 Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.
742 @param EDX Upper 32-bits of MSR value.
743 Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.
747 MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER Msr;
749 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT);
750 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT, Msr.Uint64);
752 @note MSR_SANDY_BRIDGE_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
754 #define MSR_SANDY_BRIDGE_LBR_SELECT 0x000001C8
757 MSR information returned for MSR index #MSR_SANDY_BRIDGE_LBR_SELECT
761 /// Individual bit fields
765 /// [Bit 0] CPL_EQ_0.
769 /// [Bit 1] CPL_NEQ_0.
777 /// [Bit 3] NEAR_REL_CALL.
779 UINT32 NEAR_REL_CALL
:1;
781 /// [Bit 4] NEAR_IND_CALL.
783 UINT32 NEAR_IND_CALL
:1;
785 /// [Bit 5] NEAR_RET.
789 /// [Bit 6] NEAR_IND_JMP.
791 UINT32 NEAR_IND_JMP
:1;
793 /// [Bit 7] NEAR_REL_JMP.
795 UINT32 NEAR_REL_JMP
:1;
797 /// [Bit 8] FAR_BRANCH.
804 /// All bit fields as a 32-bit value
808 /// All bit fields as a 64-bit value
811 } MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER
;
815 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
816 that points to the MSR containing the most recent branch record. See
817 MSR_LASTBRANCH_0_FROM_IP (at 680H).
819 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_TOS (0x000001C9)
820 @param EAX Lower 32-bits of MSR value.
821 @param EDX Upper 32-bits of MSR value.
827 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS);
828 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS, Msr);
830 @note MSR_SANDY_BRIDGE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
832 #define MSR_SANDY_BRIDGE_LASTBRANCH_TOS 0x000001C9
836 Thread. Last Exception Record From Linear IP (R) Contains a pointer to the
837 last branch instruction that the processor executed prior to the last
838 exception that was generated or the last interrupt that was handled.
840 @param ECX MSR_SANDY_BRIDGE_LER_FROM_LIP (0x000001DD)
841 @param EAX Lower 32-bits of MSR value.
842 @param EDX Upper 32-bits of MSR value.
848 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_FROM_LIP);
850 @note MSR_SANDY_BRIDGE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
852 #define MSR_SANDY_BRIDGE_LER_FROM_LIP 0x000001DD
856 Thread. Last Exception Record To Linear IP (R) This area contains a pointer
857 to the target of the last branch instruction that the processor executed
858 prior to the last exception that was generated or the last interrupt that
861 @param ECX MSR_SANDY_BRIDGE_LER_TO_LIP (0x000001DE)
862 @param EAX Lower 32-bits of MSR value.
863 @param EDX Upper 32-bits of MSR value.
869 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_TO_LIP);
871 @note MSR_SANDY_BRIDGE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
873 #define MSR_SANDY_BRIDGE_LER_TO_LIP 0x000001DE
877 Core. See http://biosbits.org.
879 @param ECX MSR_SANDY_BRIDGE_POWER_CTL (0x000001FC)
880 @param EAX Lower 32-bits of MSR value.
881 @param EDX Upper 32-bits of MSR value.
887 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_POWER_CTL);
888 AsmWriteMsr64 (MSR_SANDY_BRIDGE_POWER_CTL, Msr);
890 @note MSR_SANDY_BRIDGE_POWER_CTL is defined as MSR_POWER_CTL in SDM.
892 #define MSR_SANDY_BRIDGE_POWER_CTL 0x000001FC
896 Package. Always 0 (CMCI not supported).
898 @param ECX MSR_SANDY_BRIDGE_MC4_CTL2 (0x00000284)
899 @param EAX Lower 32-bits of MSR value.
900 @param EDX Upper 32-bits of MSR value.
906 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC4_CTL2);
907 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC4_CTL2, Msr);
909 @note MSR_SANDY_BRIDGE_MC4_CTL2 is defined as MSR_MC4_CTL2 in SDM.
911 #define MSR_SANDY_BRIDGE_MC4_CTL2 0x00000284
915 See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.".
917 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS (0x0000038E)
918 @param EAX Lower 32-bits of MSR value.
919 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER.
920 @param EDX Upper 32-bits of MSR value.
921 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER.
925 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER Msr;
927 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS);
928 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);
930 @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
932 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS 0x0000038E
935 MSR information returned for MSR index
936 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS
940 /// Individual bit fields
944 /// [Bit 0] Thread. Ovf_PMC0.
948 /// [Bit 1] Thread. Ovf_PMC1.
952 /// [Bit 2] Thread. Ovf_PMC2.
956 /// [Bit 3] Thread. Ovf_PMC3.
960 /// [Bit 4] Core. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
964 /// [Bit 5] Core. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
968 /// [Bit 6] Core. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
972 /// [Bit 7] Core. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
977 /// [Bit 32] Thread. Ovf_FixedCtr0.
979 UINT32 Ovf_FixedCtr0
:1;
981 /// [Bit 33] Thread. Ovf_FixedCtr1.
983 UINT32 Ovf_FixedCtr1
:1;
985 /// [Bit 34] Thread. Ovf_FixedCtr2.
987 UINT32 Ovf_FixedCtr2
:1;
990 /// [Bit 61] Thread. Ovf_Uncore.
994 /// [Bit 62] Thread. Ovf_BufDSSAVE.
996 UINT32 Ovf_BufDSSAVE
:1;
998 /// [Bit 63] Thread. CondChgd.
1003 /// All bit fields as a 64-bit value
1006 } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER
;
1010 Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control
1013 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL (0x0000038F)
1014 @param EAX Lower 32-bits of MSR value.
1015 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.
1016 @param EDX Upper 32-bits of MSR value.
1017 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.
1019 <b>Example usage</b>
1021 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;
1023 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL);
1024 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);
1026 @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.
1028 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL 0x0000038F
1031 MSR information returned for MSR index
1032 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL
1036 /// Individual bit fields
1040 /// [Bit 0] Thread. Set 1 to enable PMC0 to count.
1044 /// [Bit 1] Thread. Set 1 to enable PMC1 to count.
1048 /// [Bit 2] Thread. Set 1 to enable PMC2 to count.
1052 /// [Bit 3] Thread. Set 1 to enable PMC3 to count.
1056 /// [Bit 4] Core. Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] >
1061 /// [Bit 5] Core. Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] >
1066 /// [Bit 6] Core. Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] >
1071 /// [Bit 7] Core. Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] >
1075 UINT32 Reserved1
:24;
1077 /// [Bit 32] Thread. Set 1 to enable FixedCtr0 to count.
1079 UINT32 FIXED_CTR0
:1;
1081 /// [Bit 33] Thread. Set 1 to enable FixedCtr1 to count.
1083 UINT32 FIXED_CTR1
:1;
1085 /// [Bit 34] Thread. Set 1 to enable FixedCtr2 to count.
1087 UINT32 FIXED_CTR2
:1;
1088 UINT32 Reserved2
:29;
1091 /// All bit fields as a 64-bit value
1094 } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
;
1098 See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.".
1100 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)
1101 @param EAX Lower 32-bits of MSR value.
1102 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
1103 @param EDX Upper 32-bits of MSR value.
1104 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
1106 <b>Example usage</b>
1108 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;
1110 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL);
1111 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
1113 @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.
1115 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
1118 MSR information returned for MSR index
1119 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL
1123 /// Individual bit fields
1127 /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.
1131 /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.
1135 /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.
1139 /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.
1143 /// [Bit 4] Core. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
1147 /// [Bit 5] Core. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
1151 /// [Bit 6] Core. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
1155 /// [Bit 7] Core. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
1158 UINT32 Reserved1
:24;
1160 /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.
1162 UINT32 Ovf_FixedCtr0
:1;
1164 /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.
1166 UINT32 Ovf_FixedCtr1
:1;
1168 /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.
1170 UINT32 Ovf_FixedCtr2
:1;
1171 UINT32 Reserved2
:26;
1173 /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.
1175 UINT32 Ovf_Uncore
:1;
1177 /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.
1179 UINT32 Ovf_BufDSSAVE
:1;
1181 /// [Bit 63] Thread. Set 1 to clear CondChgd.
1186 /// All bit fields as a 64-bit value
1189 } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER
;
1193 Thread. See Section 18.7.1.1, "Precise Event Based Sampling (PEBS).".
1195 @param ECX MSR_SANDY_BRIDGE_PEBS_ENABLE (0x000003F1)
1196 @param EAX Lower 32-bits of MSR value.
1197 Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.
1198 @param EDX Upper 32-bits of MSR value.
1199 Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.
1201 <b>Example usage</b>
1203 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER Msr;
1205 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE);
1206 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE, Msr.Uint64);
1208 @note MSR_SANDY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1210 #define MSR_SANDY_BRIDGE_PEBS_ENABLE 0x000003F1
1213 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_ENABLE
1217 /// Individual bit fields
1221 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
1223 UINT32 PEBS_EN_PMC0
:1;
1225 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
1227 UINT32 PEBS_EN_PMC1
:1;
1229 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
1231 UINT32 PEBS_EN_PMC2
:1;
1233 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
1235 UINT32 PEBS_EN_PMC3
:1;
1236 UINT32 Reserved1
:28;
1238 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
1240 UINT32 LL_EN_PMC0
:1;
1242 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
1244 UINT32 LL_EN_PMC1
:1;
1246 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
1248 UINT32 LL_EN_PMC2
:1;
1250 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
1252 UINT32 LL_EN_PMC3
:1;
1253 UINT32 Reserved2
:27;
1255 /// [Bit 63] Enable Precise Store. (R/W).
1260 /// All bit fields as a 64-bit value
1263 } MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
;
1267 Thread. see See Section 18.7.1.2, "Load Latency Performance Monitoring
1270 @param ECX MSR_SANDY_BRIDGE_PEBS_LD_LAT (0x000003F6)
1271 @param EAX Lower 32-bits of MSR value.
1272 Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.
1273 @param EDX Upper 32-bits of MSR value.
1274 Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.
1276 <b>Example usage</b>
1278 MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER Msr;
1280 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT);
1281 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT, Msr.Uint64);
1283 @note MSR_SANDY_BRIDGE_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.
1285 #define MSR_SANDY_BRIDGE_PEBS_LD_LAT 0x000003F6
1288 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_LD_LAT
1292 /// Individual bit fields
1296 /// [Bits 15:0] Minimum threshold latency value of tagged load operation
1297 /// that will be counted. (R/W).
1299 UINT32 MinimumThreshold
:16;
1300 UINT32 Reserved1
:16;
1301 UINT32 Reserved2
:32;
1304 /// All bit fields as a 32-bit value
1308 /// All bit fields as a 64-bit value
1311 } MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER
;
1315 Package. Note: C-state values are processor specific C-state code names,
1316 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3
1317 Residency Counter. (R/O) Value since last reset that this package is in
1318 processor-specific C3 states. Count at the same frequency as the TSC.
1320 @param ECX MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY (0x000003F8)
1321 @param EAX Lower 32-bits of MSR value.
1322 @param EDX Upper 32-bits of MSR value.
1324 <b>Example usage</b>
1328 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY);
1329 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY, Msr);
1331 @note MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
1333 #define MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY 0x000003F8
1337 Package. Note: C-state values are processor specific C-state code names,
1338 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
1339 Residency Counter. (R/O) Value since last reset that this package is in
1340 processor-specific C6 states. Count at the same frequency as the TSC.
1342 @param ECX MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY (0x000003F9)
1343 @param EAX Lower 32-bits of MSR value.
1344 @param EDX Upper 32-bits of MSR value.
1346 <b>Example usage</b>
1350 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY);
1351 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY, Msr);
1353 @note MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
1355 #define MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY 0x000003F9
1359 Package. Note: C-state values are processor specific C-state code names,
1360 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7
1361 Residency Counter. (R/O) Value since last reset that this package is in
1362 processor-specific C7 states. Count at the same frequency as the TSC.
1364 @param ECX MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY (0x000003FA)
1365 @param EAX Lower 32-bits of MSR value.
1366 @param EDX Upper 32-bits of MSR value.
1368 <b>Example usage</b>
1372 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY);
1373 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY, Msr);
1375 @note MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
1377 #define MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY 0x000003FA
1381 Core. Note: C-state values are processor specific C-state code names,
1382 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3
1383 Residency Counter. (R/O) Value since last reset that this core is in
1384 processor-specific C3 states. Count at the same frequency as the TSC.
1386 @param ECX MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY (0x000003FC)
1387 @param EAX Lower 32-bits of MSR value.
1388 @param EDX Upper 32-bits of MSR value.
1390 <b>Example usage</b>
1394 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY);
1395 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY, Msr);
1397 @note MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.
1399 #define MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY 0x000003FC
1403 Core. Note: C-state values are processor specific C-state code names,
1404 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6
1405 Residency Counter. (R/O) Value since last reset that this core is in
1406 processor-specific C6 states. Count at the same frequency as the TSC.
1408 @param ECX MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY (0x000003FD)
1409 @param EAX Lower 32-bits of MSR value.
1410 @param EDX Upper 32-bits of MSR value.
1412 <b>Example usage</b>
1416 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY);
1417 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY, Msr);
1419 @note MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
1421 #define MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY 0x000003FD
1425 Core. Note: C-state values are processor specific C-state code names,
1426 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C7
1427 Residency Counter. (R/O) Value since last reset that this core is in
1428 processor-specific C7 states. Count at the same frequency as the TSC.
1430 @param ECX MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY (0x000003FE)
1431 @param EAX Lower 32-bits of MSR value.
1432 @param EDX Upper 32-bits of MSR value.
1434 <b>Example usage</b>
1438 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY);
1439 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY, Msr);
1441 @note MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY is defined as MSR_CORE_C7_RESIDENCY in SDM.
1443 #define MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY 0x000003FE
1447 Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
1449 @param ECX MSR_SANDY_BRIDGE_MC4_CTL (0x00000410)
1450 @param EAX Lower 32-bits of MSR value.
1451 Described by the type MSR_SANDY_BRIDGE_MC4_CTL_REGISTER.
1452 @param EDX Upper 32-bits of MSR value.
1453 Described by the type MSR_SANDY_BRIDGE_MC4_CTL_REGISTER.
1455 <b>Example usage</b>
1457 MSR_SANDY_BRIDGE_MC4_CTL_REGISTER Msr;
1459 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC4_CTL);
1460 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC4_CTL, Msr.Uint64);
1462 @note MSR_SANDY_BRIDGE_MC4_CTL is defined as MSR_MC4_CTL in SDM.
1464 #define MSR_SANDY_BRIDGE_MC4_CTL 0x00000410
1467 MSR information returned for MSR index #MSR_SANDY_BRIDGE_MC4_CTL
1471 /// Individual bit fields
1475 /// [Bit 0] PCU Hardware Error (R/W) When set, enables signaling of PCU
1476 /// hardware detected errors.
1478 UINT32 PCUHardwareError
:1;
1480 /// [Bit 1] PCU Controller Error (R/W) When set, enables signaling of PCU
1481 /// controller detected errors.
1483 UINT32 PCUControllerError
:1;
1485 /// [Bit 2] PCU Firmware Error (R/W) When set, enables signaling of PCU
1486 /// firmware detected errors.
1488 UINT32 PCUFirmwareError
:1;
1489 UINT32 Reserved1
:29;
1490 UINT32 Reserved2
:32;
1493 /// All bit fields as a 32-bit value
1497 /// All bit fields as a 64-bit value
1500 } MSR_SANDY_BRIDGE_MC4_CTL_REGISTER
;
1504 Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.
1506 @param ECX MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
1507 @param EAX Lower 32-bits of MSR value.
1508 @param EDX Upper 32-bits of MSR value.
1510 <b>Example usage</b>
1514 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM);
1516 @note MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
1518 #define MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM 0x0000048C
1522 Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,
1525 @param ECX MSR_SANDY_BRIDGE_RAPL_POWER_UNIT (0x00000606)
1526 @param EAX Lower 32-bits of MSR value.
1527 @param EDX Upper 32-bits of MSR value.
1529 <b>Example usage</b>
1533 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_RAPL_POWER_UNIT);
1535 @note MSR_SANDY_BRIDGE_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
1537 #define MSR_SANDY_BRIDGE_RAPL_POWER_UNIT 0x00000606
1541 Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are
1542 processor specific C-state code names, unrelated to MWAIT extension C-state
1543 parameters or ACPI CStates.
1545 @param ECX MSR_SANDY_BRIDGE_PKGC3_IRTL (0x0000060A)
1546 @param EAX Lower 32-bits of MSR value.
1547 Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.
1548 @param EDX Upper 32-bits of MSR value.
1549 Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.
1551 <b>Example usage</b>
1553 MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER Msr;
1555 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL);
1556 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL, Msr.Uint64);
1558 @note MSR_SANDY_BRIDGE_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.
1560 #define MSR_SANDY_BRIDGE_PKGC3_IRTL 0x0000060A
1563 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC3_IRTL
1567 /// Individual bit fields
1571 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
1572 /// that should be used to decide if the package should be put into a
1573 /// package C3 state.
1575 UINT32 TimeLimit
:10;
1577 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
1578 /// unit of the interrupt response time limit. The following time unit
1579 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
1580 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
1585 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
1586 /// valid and can be used by the processor for package C-sate management.
1589 UINT32 Reserved2
:16;
1590 UINT32 Reserved3
:32;
1593 /// All bit fields as a 32-bit value
1597 /// All bit fields as a 64-bit value
1600 } MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER
;
1604 Package. Package C6 Interrupt Response Limit (R/W) This MSR defines the
1605 budget allocated for the package to exit from C6 to a C0 state, where
1606 interrupt request can be delivered to the core and serviced. Additional
1607 core-exit latency amy be applicable depending on the actual C-state the core
1608 is in. Note: C-state values are processor specific C-state code names,
1609 unrelated to MWAIT extension C-state parameters or ACPI CStates.
1611 @param ECX MSR_SANDY_BRIDGE_PKGC6_IRTL (0x0000060B)
1612 @param EAX Lower 32-bits of MSR value.
1613 Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.
1614 @param EDX Upper 32-bits of MSR value.
1615 Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.
1617 <b>Example usage</b>
1619 MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER Msr;
1621 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL);
1622 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL, Msr.Uint64);
1624 @note MSR_SANDY_BRIDGE_PKGC6_IRTL is defined as MSR_PKGC6_IRTL in SDM.
1626 #define MSR_SANDY_BRIDGE_PKGC6_IRTL 0x0000060B
1629 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC6_IRTL
1633 /// Individual bit fields
1637 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
1638 /// that should be used to decide if the package should be put into a
1639 /// package C6 state.
1641 UINT32 TimeLimit
:10;
1643 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
1644 /// unit of the interrupt response time limit. The following time unit
1645 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
1646 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
1651 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
1652 /// valid and can be used by the processor for package C-sate management.
1655 UINT32 Reserved2
:16;
1656 UINT32 Reserved3
:32;
1659 /// All bit fields as a 32-bit value
1663 /// All bit fields as a 64-bit value
1666 } MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER
;
1670 Package. Note: C-state values are processor specific C-state code names,
1671 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2
1672 Residency Counter. (R/O) Value since last reset that this package is in
1673 processor-specific C2 states. Count at the same frequency as the TSC.
1675 @param ECX MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY (0x0000060D)
1676 @param EAX Lower 32-bits of MSR value.
1677 @param EDX Upper 32-bits of MSR value.
1679 <b>Example usage</b>
1683 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY);
1684 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY, Msr);
1686 @note MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
1688 #define MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY 0x0000060D
1692 Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
1695 @param ECX MSR_SANDY_BRIDGE_PKG_POWER_LIMIT (0x00000610)
1696 @param EAX Lower 32-bits of MSR value.
1697 @param EDX Upper 32-bits of MSR value.
1699 <b>Example usage</b>
1703 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT);
1704 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT, Msr);
1706 @note MSR_SANDY_BRIDGE_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
1708 #define MSR_SANDY_BRIDGE_PKG_POWER_LIMIT 0x00000610
1712 Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1714 @param ECX MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS (0x00000611)
1715 @param EAX Lower 32-bits of MSR value.
1716 @param EDX Upper 32-bits of MSR value.
1718 <b>Example usage</b>
1722 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS);
1724 @note MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
1726 #define MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS 0x00000611
1730 Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL
1733 @param ECX MSR_SANDY_BRIDGE_PKG_POWER_INFO (0x00000614)
1734 @param EAX Lower 32-bits of MSR value.
1735 @param EDX Upper 32-bits of MSR value.
1737 <b>Example usage</b>
1741 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO);
1742 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO, Msr);
1744 @note MSR_SANDY_BRIDGE_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
1746 #define MSR_SANDY_BRIDGE_PKG_POWER_INFO 0x00000614
1750 Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
1753 @param ECX MSR_SANDY_BRIDGE_PP0_POWER_LIMIT (0x00000638)
1754 @param EAX Lower 32-bits of MSR value.
1755 @param EDX Upper 32-bits of MSR value.
1757 <b>Example usage</b>
1761 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT);
1762 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT, Msr);
1764 @note MSR_SANDY_BRIDGE_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
1766 #define MSR_SANDY_BRIDGE_PP0_POWER_LIMIT 0x00000638
1770 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1773 @param ECX MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)
1774 @param EAX Lower 32-bits of MSR value.
1775 @param EDX Upper 32-bits of MSR value.
1777 <b>Example usage</b>
1781 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS);
1783 @note MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
1785 #define MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS 0x00000639
1789 Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last
1790 branch record registers on the last branch record stack. This part of the
1791 stack contains pointers to the source instruction. See also: - Last Branch
1792 Record Stack TOS at 1C9H - Section 17.6.1, "LBR Stack.".
1794 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_FROM_IP
1795 @param EAX Lower 32-bits of MSR value.
1796 @param EDX Upper 32-bits of MSR value.
1798 <b>Example usage</b>
1802 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP);
1803 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP, Msr);
1805 @note MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
1806 MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
1807 MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
1808 MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
1809 MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
1810 MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
1811 MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
1812 MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
1813 MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.
1814 MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.
1815 MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.
1816 MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.
1817 MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.
1818 MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.
1819 MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.
1820 MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.
1823 #define MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP 0x00000680
1824 #define MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP 0x00000681
1825 #define MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP 0x00000682
1826 #define MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP 0x00000683
1827 #define MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP 0x00000684
1828 #define MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP 0x00000685
1829 #define MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP 0x00000686
1830 #define MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP 0x00000687
1831 #define MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP 0x00000688
1832 #define MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP 0x00000689
1833 #define MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP 0x0000068A
1834 #define MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP 0x0000068B
1835 #define MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP 0x0000068C
1836 #define MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP 0x0000068D
1837 #define MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP 0x0000068E
1838 #define MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP 0x0000068F
1843 Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch
1844 record registers on the last branch record stack. This part of the stack
1845 contains pointers to the destination instruction.
1847 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_TO_IP
1848 @param EAX Lower 32-bits of MSR value.
1849 @param EDX Upper 32-bits of MSR value.
1851 <b>Example usage</b>
1855 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP);
1856 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP, Msr);
1858 @note MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
1859 MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
1860 MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
1861 MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
1862 MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
1863 MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
1864 MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
1865 MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
1866 MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.
1867 MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.
1868 MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.
1869 MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.
1870 MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.
1871 MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.
1872 MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.
1873 MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.
1876 #define MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP 0x000006C0
1877 #define MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP 0x000006C1
1878 #define MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP 0x000006C2
1879 #define MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP 0x000006C3
1880 #define MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP 0x000006C4
1881 #define MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP 0x000006C5
1882 #define MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP 0x000006C6
1883 #define MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP 0x000006C7
1884 #define MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP 0x000006C8
1885 #define MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP 0x000006C9
1886 #define MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP 0x000006CA
1887 #define MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP 0x000006CB
1888 #define MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP 0x000006CC
1889 #define MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP 0x000006CD
1890 #define MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP 0x000006CE
1891 #define MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP 0x000006CF
1896 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
1897 RW if MSR_PLATFORM_INFO.[28] = 1.
1899 @param ECX MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT (0x000001AD)
1900 @param EAX Lower 32-bits of MSR value.
1901 Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.
1902 @param EDX Upper 32-bits of MSR value.
1903 Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.
1905 <b>Example usage</b>
1907 MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER Msr;
1909 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT);
1911 @note MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
1913 #define MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT 0x000001AD
1916 MSR information returned for MSR index #MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT
1920 /// Individual bit fields
1924 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
1925 /// limit of 1 core active.
1929 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
1930 /// limit of 2 core active.
1934 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
1935 /// limit of 3 core active.
1939 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
1940 /// limit of 4 core active.
1944 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
1945 /// limit of 5 core active.
1949 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
1950 /// limit of 6 core active.
1954 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
1955 /// limit of 7 core active.
1959 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
1960 /// limit of 8 core active.
1965 /// All bit fields as a 64-bit value
1968 } MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER
;
1972 Package. Uncore PMU global control.
1974 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL (0x00000391)
1975 @param EAX Lower 32-bits of MSR value.
1976 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.
1977 @param EDX Upper 32-bits of MSR value.
1978 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.
1980 <b>Example usage</b>
1982 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;
1984 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL);
1985 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);
1987 @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.
1989 #define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL 0x00000391
1992 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL
1996 /// Individual bit fields
2000 /// [Bit 0] Core 0 select.
2002 UINT32 PMI_Sel_Core0
:1;
2004 /// [Bit 1] Core 1 select.
2006 UINT32 PMI_Sel_Core1
:1;
2008 /// [Bit 2] Core 2 select.
2010 UINT32 PMI_Sel_Core2
:1;
2012 /// [Bit 3] Core 3 select.
2014 UINT32 PMI_Sel_Core3
:1;
2015 UINT32 Reserved1
:15;
2016 UINT32 Reserved2
:10;
2018 /// [Bit 29] Enable all uncore counters.
2022 /// [Bit 30] Enable wake on PMI.
2026 /// [Bit 31] Enable Freezing counter when overflow.
2029 UINT32 Reserved3
:32;
2032 /// All bit fields as a 32-bit value
2036 /// All bit fields as a 64-bit value
2039 } MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER
;
2043 Package. Uncore PMU main status.
2045 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS (0x00000392)
2046 @param EAX Lower 32-bits of MSR value.
2047 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.
2048 @param EDX Upper 32-bits of MSR value.
2049 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.
2051 <b>Example usage</b>
2053 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;
2055 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS);
2056 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);
2058 @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.
2060 #define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS 0x00000392
2063 MSR information returned for MSR index
2064 #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS
2068 /// Individual bit fields
2072 /// [Bit 0] Fixed counter overflowed.
2076 /// [Bit 1] An ARB counter overflowed.
2081 /// [Bit 3] A CBox counter overflowed (on any slice).
2084 UINT32 Reserved2
:28;
2085 UINT32 Reserved3
:32;
2088 /// All bit fields as a 32-bit value
2092 /// All bit fields as a 64-bit value
2095 } MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER
;
2099 Package. Uncore fixed counter control (R/W).
2101 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL (0x00000394)
2102 @param EAX Lower 32-bits of MSR value.
2103 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.
2104 @param EDX Upper 32-bits of MSR value.
2105 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.
2107 <b>Example usage</b>
2109 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER Msr;
2111 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL);
2112 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL, Msr.Uint64);
2114 @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.
2116 #define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL 0x00000394
2119 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL
2123 /// Individual bit fields
2126 UINT32 Reserved1
:20;
2128 /// [Bit 20] Enable overflow propagation.
2130 UINT32 EnableOverflow
:1;
2133 /// [Bit 22] Enable counting.
2135 UINT32 EnableCounting
:1;
2137 UINT32 Reserved4
:32;
2140 /// All bit fields as a 32-bit value
2144 /// All bit fields as a 64-bit value
2147 } MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER
;
2151 Package. Uncore fixed counter.
2153 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR (0x00000395)
2154 @param EAX Lower 32-bits of MSR value.
2155 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.
2156 @param EDX Upper 32-bits of MSR value.
2157 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.
2159 <b>Example usage</b>
2161 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER Msr;
2163 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR);
2164 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR, Msr.Uint64);
2166 @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.
2168 #define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR 0x00000395
2171 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR
2175 /// Individual bit fields
2179 /// [Bits 31:0] Current count.
2181 UINT32 CurrentCount
:32;
2183 /// [Bits 47:32] Current count.
2185 UINT32 CurrentCountHi
:16;
2189 /// All bit fields as a 64-bit value
2192 } MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER
;
2196 Package. Uncore C-Box configuration information (R/O).
2198 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_CONFIG (0x00000396)
2199 @param EAX Lower 32-bits of MSR value.
2200 Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.
2201 @param EDX Upper 32-bits of MSR value.
2202 Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.
2204 <b>Example usage</b>
2206 MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER Msr;
2208 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_CONFIG);
2210 @note MSR_SANDY_BRIDGE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.
2212 #define MSR_SANDY_BRIDGE_UNC_CBO_CONFIG 0x00000396
2215 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_CBO_CONFIG
2219 /// Individual bit fields
2223 /// [Bits 3:0] Encoded number of C-Box, derive value by "-1".
2226 UINT32 Reserved1
:28;
2227 UINT32 Reserved2
:32;
2230 /// All bit fields as a 32-bit value
2234 /// All bit fields as a 64-bit value
2237 } MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER
;
2241 Package. Uncore Arb unit, performance counter 0.
2243 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 (0x000003B0)
2244 @param EAX Lower 32-bits of MSR value.
2245 @param EDX Upper 32-bits of MSR value.
2247 <b>Example usage</b>
2251 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0);
2252 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0, Msr);
2254 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.
2256 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 0x000003B0
2260 Package. Uncore Arb unit, performance counter 1.
2262 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 (0x000003B1)
2263 @param EAX Lower 32-bits of MSR value.
2264 @param EDX Upper 32-bits of MSR value.
2266 <b>Example usage</b>
2270 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1);
2271 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1, Msr);
2273 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.
2275 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 0x000003B1
2279 Package. Uncore Arb unit, counter 0 event select MSR.
2281 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 (0x000003B2)
2282 @param EAX Lower 32-bits of MSR value.
2283 @param EDX Upper 32-bits of MSR value.
2285 <b>Example usage</b>
2289 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0);
2290 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0, Msr);
2292 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.
2294 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 0x000003B2
2298 Package. Uncore Arb unit, counter 1 event select MSR.
2300 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 (0x000003B3)
2301 @param EAX Lower 32-bits of MSR value.
2302 @param EDX Upper 32-bits of MSR value.
2304 <b>Example usage</b>
2308 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1);
2309 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1, Msr);
2311 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.
2313 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 0x000003B3
2317 Package. Package C7 Interrupt Response Limit (R/W) This MSR defines the
2318 budget allocated for the package to exit from C7 to a C0 state, where
2319 interrupt request can be delivered to the core and serviced. Additional
2320 core-exit latency amy be applicable depending on the actual C-state the core
2321 is in. Note: C-state values are processor specific C-state code names,
2322 unrelated to MWAIT extension C-state parameters or ACPI CStates.
2324 @param ECX MSR_SANDY_BRIDGE_PKGC7_IRTL (0x0000060C)
2325 @param EAX Lower 32-bits of MSR value.
2326 Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.
2327 @param EDX Upper 32-bits of MSR value.
2328 Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.
2330 <b>Example usage</b>
2332 MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER Msr;
2334 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL);
2335 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL, Msr.Uint64);
2337 @note MSR_SANDY_BRIDGE_PKGC7_IRTL is defined as MSR_PKGC7_IRTL in SDM.
2339 #define MSR_SANDY_BRIDGE_PKGC7_IRTL 0x0000060C
2342 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC7_IRTL
2346 /// Individual bit fields
2350 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
2351 /// that should be used to decide if the package should be put into a
2352 /// package C7 state.
2354 UINT32 TimeLimit
:10;
2356 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
2357 /// unit of the interrupt response time limit. The following time unit
2358 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
2359 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
2364 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
2365 /// valid and can be used by the processor for package C-sate management.
2368 UINT32 Reserved2
:16;
2369 UINT32 Reserved3
:32;
2372 /// All bit fields as a 32-bit value
2376 /// All bit fields as a 64-bit value
2379 } MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER
;
2383 Package. PP0 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
2386 @param ECX MSR_SANDY_BRIDGE_PP0_POLICY (0x0000063A)
2387 @param EAX Lower 32-bits of MSR value.
2388 @param EDX Upper 32-bits of MSR value.
2390 <b>Example usage</b>
2394 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY);
2395 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY, Msr);
2397 @note MSR_SANDY_BRIDGE_PP0_POLICY is defined as MSR_PP0_POLICY in SDM.
2399 #define MSR_SANDY_BRIDGE_PP0_POLICY 0x0000063A
2403 Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
2406 @param ECX MSR_SANDY_BRIDGE_PP1_POWER_LIMIT (0x00000640)
2407 @param EAX Lower 32-bits of MSR value.
2408 @param EDX Upper 32-bits of MSR value.
2410 <b>Example usage</b>
2414 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT);
2415 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT, Msr);
2417 @note MSR_SANDY_BRIDGE_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.
2419 #define MSR_SANDY_BRIDGE_PP1_POWER_LIMIT 0x00000640
2423 Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
2426 @param ECX MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS (0x00000641)
2427 @param EAX Lower 32-bits of MSR value.
2428 @param EDX Upper 32-bits of MSR value.
2430 <b>Example usage</b>
2434 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS);
2436 @note MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.
2438 #define MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS 0x00000641
2442 Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
2445 @param ECX MSR_SANDY_BRIDGE_PP1_POLICY (0x00000642)
2446 @param EAX Lower 32-bits of MSR value.
2447 @param EDX Upper 32-bits of MSR value.
2449 <b>Example usage</b>
2453 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY);
2454 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY, Msr);
2456 @note MSR_SANDY_BRIDGE_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.
2458 #define MSR_SANDY_BRIDGE_PP1_POLICY 0x00000642
2462 Package. Uncore C-Box 0, counter 0 event select MSR.
2464 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 (0x00000700)
2465 @param EAX Lower 32-bits of MSR value.
2466 @param EDX Upper 32-bits of MSR value.
2468 <b>Example usage</b>
2472 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0);
2473 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0, Msr);
2475 @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.
2477 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 0x00000700
2481 Package. Uncore C-Box 0, counter 1 event select MSR.
2483 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 (0x00000701)
2484 @param EAX Lower 32-bits of MSR value.
2485 @param EDX Upper 32-bits of MSR value.
2487 <b>Example usage</b>
2491 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1);
2492 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1, Msr);
2494 @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.
2496 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701
2500 Package. Uncore C-Box 0, performance counter 0.
2502 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 (0x00000706)
2503 @param EAX Lower 32-bits of MSR value.
2504 @param EDX Upper 32-bits of MSR value.
2506 <b>Example usage</b>
2510 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0);
2511 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0, Msr);
2513 @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.
2515 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 0x00000706
2519 Package. Uncore C-Box 0, performance counter 1.
2521 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 (0x00000707)
2522 @param EAX Lower 32-bits of MSR value.
2523 @param EDX Upper 32-bits of MSR value.
2525 <b>Example usage</b>
2529 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1);
2530 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1, Msr);
2532 @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.
2534 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 0x00000707
2538 Package. Uncore C-Box 1, counter 0 event select MSR.
2540 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 (0x00000710)
2541 @param EAX Lower 32-bits of MSR value.
2542 @param EDX Upper 32-bits of MSR value.
2544 <b>Example usage</b>
2548 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0);
2549 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0, Msr);
2551 @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.
2553 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 0x00000710
2557 Package. Uncore C-Box 1, counter 1 event select MSR.
2559 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 (0x00000711)
2560 @param EAX Lower 32-bits of MSR value.
2561 @param EDX Upper 32-bits of MSR value.
2563 <b>Example usage</b>
2567 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1);
2568 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1, Msr);
2570 @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.
2572 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 0x00000711
2576 Package. Uncore C-Box 1, performance counter 0.
2578 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 (0x00000716)
2579 @param EAX Lower 32-bits of MSR value.
2580 @param EDX Upper 32-bits of MSR value.
2582 <b>Example usage</b>
2586 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0);
2587 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0, Msr);
2589 @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.
2591 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 0x00000716
2595 Package. Uncore C-Box 1, performance counter 1.
2597 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 (0x00000717)
2598 @param EAX Lower 32-bits of MSR value.
2599 @param EDX Upper 32-bits of MSR value.
2601 <b>Example usage</b>
2605 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1);
2606 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1, Msr);
2608 @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.
2610 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 0x00000717
2614 Package. Uncore C-Box 2, counter 0 event select MSR.
2616 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 (0x00000720)
2617 @param EAX Lower 32-bits of MSR value.
2618 @param EDX Upper 32-bits of MSR value.
2620 <b>Example usage</b>
2624 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0);
2625 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0, Msr);
2627 @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.
2629 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 0x00000720
2633 Package. Uncore C-Box 2, counter 1 event select MSR.
2635 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 (0x00000721)
2636 @param EAX Lower 32-bits of MSR value.
2637 @param EDX Upper 32-bits of MSR value.
2639 <b>Example usage</b>
2643 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1);
2644 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1, Msr);
2646 @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.
2648 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 0x00000721
2652 Package. Uncore C-Box 2, performance counter 0.
2654 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 (0x00000726)
2655 @param EAX Lower 32-bits of MSR value.
2656 @param EDX Upper 32-bits of MSR value.
2658 <b>Example usage</b>
2662 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0);
2663 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0, Msr);
2665 @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.
2667 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 0x00000726
2671 Package. Uncore C-Box 2, performance counter 1.
2673 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 (0x00000727)
2674 @param EAX Lower 32-bits of MSR value.
2675 @param EDX Upper 32-bits of MSR value.
2677 <b>Example usage</b>
2681 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1);
2682 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1, Msr);
2684 @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.
2686 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 0x00000727
2690 Package. Uncore C-Box 3, counter 0 event select MSR.
2692 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 (0x00000730)
2693 @param EAX Lower 32-bits of MSR value.
2694 @param EDX Upper 32-bits of MSR value.
2696 <b>Example usage</b>
2700 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0);
2701 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0, Msr);
2703 @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.
2705 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 0x00000730
2709 Package. Uncore C-Box 3, counter 1 event select MSR.
2711 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 (0x00000731)
2712 @param EAX Lower 32-bits of MSR value.
2713 @param EDX Upper 32-bits of MSR value.
2715 <b>Example usage</b>
2719 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1);
2720 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1, Msr);
2722 @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.
2724 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731
2728 Package. Uncore C-Box 3, performance counter 0.
2730 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 (0x00000736)
2731 @param EAX Lower 32-bits of MSR value.
2732 @param EDX Upper 32-bits of MSR value.
2734 <b>Example usage</b>
2738 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0);
2739 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0, Msr);
2741 @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.
2743 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736
2747 Package. Uncore C-Box 3, performance counter 1.
2749 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 (0x00000737)
2750 @param EAX Lower 32-bits of MSR value.
2751 @param EDX Upper 32-bits of MSR value.
2753 <b>Example usage</b>
2757 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1);
2758 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1, Msr);
2760 @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.
2762 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737
2766 Package. MC Bank Error Configuration (R/W).
2768 @param ECX MSR_SANDY_BRIDGE_ERROR_CONTROL (0x0000017F)
2769 @param EAX Lower 32-bits of MSR value.
2770 Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.
2771 @param EDX Upper 32-bits of MSR value.
2772 Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.
2774 <b>Example usage</b>
2776 MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER Msr;
2778 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL);
2779 AsmWriteMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL, Msr.Uint64);
2781 @note MSR_SANDY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
2783 #define MSR_SANDY_BRIDGE_ERROR_CONTROL 0x0000017F
2786 MSR information returned for MSR index #MSR_SANDY_BRIDGE_ERROR_CONTROL
2790 /// Individual bit fields
2795 /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank
2796 /// to log additional info in bits 36:32.
2798 UINT32 MemErrorLogEnable
:1;
2799 UINT32 Reserved2
:30;
2800 UINT32 Reserved3
:32;
2803 /// All bit fields as a 32-bit value
2807 /// All bit fields as a 64-bit value
2810 } MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER
;
2816 @param ECX MSR_SANDY_BRIDGE_PEBS_NUM_ALT (0x0000039C)
2817 @param EAX Lower 32-bits of MSR value.
2818 Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.
2819 @param EDX Upper 32-bits of MSR value.
2820 Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.
2822 <b>Example usage</b>
2824 MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER Msr;
2826 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT);
2827 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT, Msr.Uint64);
2829 @note MSR_SANDY_BRIDGE_PEBS_NUM_ALT is defined as MSR_PEBS_NUM_ALT in SDM.
2831 #define MSR_SANDY_BRIDGE_PEBS_NUM_ALT 0x0000039C
2834 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_NUM_ALT
2838 /// Individual bit fields
2842 /// [Bit 0] ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS
2843 /// counting logic for specific events requiring additional configuration,
2846 UINT32 ENABLE_PEBS_NUM_ALT
:1;
2847 UINT32 Reserved1
:31;
2848 UINT32 Reserved2
:32;
2851 /// All bit fields as a 32-bit value
2855 /// All bit fields as a 64-bit value
2858 } MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER
;
2862 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
2864 @param ECX MSR_SANDY_BRIDGE_MCi_CTL
2865 @param EAX Lower 32-bits of MSR value.
2866 @param EDX Upper 32-bits of MSR value.
2868 <b>Example usage</b>
2872 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_CTL);
2873 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_CTL, Msr);
2875 @note MSR_SANDY_BRIDGE_MC5_CTL is defined as MSR_MC5_CTL in SDM.
2876 MSR_SANDY_BRIDGE_MC6_CTL is defined as MSR_MC6_CTL in SDM.
2877 MSR_SANDY_BRIDGE_MC7_CTL is defined as MSR_MC7_CTL in SDM.
2878 MSR_SANDY_BRIDGE_MC8_CTL is defined as MSR_MC8_CTL in SDM.
2879 MSR_SANDY_BRIDGE_MC9_CTL is defined as MSR_MC9_CTL in SDM.
2880 MSR_SANDY_BRIDGE_MC10_CTL is defined as MSR_MC10_CTL in SDM.
2881 MSR_SANDY_BRIDGE_MC11_CTL is defined as MSR_MC11_CTL in SDM.
2882 MSR_SANDY_BRIDGE_MC12_CTL is defined as MSR_MC12_CTL in SDM.
2883 MSR_SANDY_BRIDGE_MC13_CTL is defined as MSR_MC13_CTL in SDM.
2884 MSR_SANDY_BRIDGE_MC14_CTL is defined as MSR_MC14_CTL in SDM.
2885 MSR_SANDY_BRIDGE_MC15_CTL is defined as MSR_MC15_CTL in SDM.
2886 MSR_SANDY_BRIDGE_MC16_CTL is defined as MSR_MC16_CTL in SDM.
2887 MSR_SANDY_BRIDGE_MC17_CTL is defined as MSR_MC17_CTL in SDM.
2888 MSR_SANDY_BRIDGE_MC18_CTL is defined as MSR_MC18_CTL in SDM.
2889 MSR_SANDY_BRIDGE_MC19_CTL is defined as MSR_MC19_CTL in SDM.
2892 #define MSR_SANDY_BRIDGE_MC5_CTL 0x00000414
2893 #define MSR_SANDY_BRIDGE_MC6_CTL 0x00000418
2894 #define MSR_SANDY_BRIDGE_MC7_CTL 0x0000041C
2895 #define MSR_SANDY_BRIDGE_MC8_CTL 0x00000420
2896 #define MSR_SANDY_BRIDGE_MC9_CTL 0x00000424
2897 #define MSR_SANDY_BRIDGE_MC10_CTL 0x00000428
2898 #define MSR_SANDY_BRIDGE_MC11_CTL 0x0000042C
2899 #define MSR_SANDY_BRIDGE_MC12_CTL 0x00000430
2900 #define MSR_SANDY_BRIDGE_MC13_CTL 0x00000434
2901 #define MSR_SANDY_BRIDGE_MC14_CTL 0x00000438
2902 #define MSR_SANDY_BRIDGE_MC15_CTL 0x0000043C
2903 #define MSR_SANDY_BRIDGE_MC16_CTL 0x00000440
2904 #define MSR_SANDY_BRIDGE_MC17_CTL 0x00000444
2905 #define MSR_SANDY_BRIDGE_MC18_CTL 0x00000448
2906 #define MSR_SANDY_BRIDGE_MC19_CTL 0x0000044C
2911 Package. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS," and Chapter 16.
2913 @param ECX MSR_SANDY_BRIDGE_MCi_STATUS
2914 @param EAX Lower 32-bits of MSR value.
2915 @param EDX Upper 32-bits of MSR value.
2917 <b>Example usage</b>
2921 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_STATUS);
2922 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_STATUS, Msr);
2924 @note MSR_SANDY_BRIDGE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
2925 MSR_SANDY_BRIDGE_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.
2926 MSR_SANDY_BRIDGE_MC7_STATUS is defined as MSR_MC7_STATUS in SDM.
2927 MSR_SANDY_BRIDGE_MC8_STATUS is defined as MSR_MC8_STATUS in SDM.
2928 MSR_SANDY_BRIDGE_MC9_STATUS is defined as MSR_MC9_STATUS in SDM.
2929 MSR_SANDY_BRIDGE_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.
2930 MSR_SANDY_BRIDGE_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.
2931 MSR_SANDY_BRIDGE_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.
2932 MSR_SANDY_BRIDGE_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.
2933 MSR_SANDY_BRIDGE_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.
2934 MSR_SANDY_BRIDGE_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.
2935 MSR_SANDY_BRIDGE_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.
2936 MSR_SANDY_BRIDGE_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.
2937 MSR_SANDY_BRIDGE_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.
2938 MSR_SANDY_BRIDGE_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.
2941 #define MSR_SANDY_BRIDGE_MC5_STATUS 0x00000415
2942 #define MSR_SANDY_BRIDGE_MC6_STATUS 0x00000419
2943 #define MSR_SANDY_BRIDGE_MC7_STATUS 0x0000041D
2944 #define MSR_SANDY_BRIDGE_MC8_STATUS 0x00000421
2945 #define MSR_SANDY_BRIDGE_MC9_STATUS 0x00000425
2946 #define MSR_SANDY_BRIDGE_MC10_STATUS 0x00000429
2947 #define MSR_SANDY_BRIDGE_MC11_STATUS 0x0000042D
2948 #define MSR_SANDY_BRIDGE_MC12_STATUS 0x00000431
2949 #define MSR_SANDY_BRIDGE_MC13_STATUS 0x00000435
2950 #define MSR_SANDY_BRIDGE_MC14_STATUS 0x00000439
2951 #define MSR_SANDY_BRIDGE_MC15_STATUS 0x0000043D
2952 #define MSR_SANDY_BRIDGE_MC16_STATUS 0x00000441
2953 #define MSR_SANDY_BRIDGE_MC17_STATUS 0x00000445
2954 #define MSR_SANDY_BRIDGE_MC18_STATUS 0x00000449
2955 #define MSR_SANDY_BRIDGE_MC19_STATUS 0x0000044D
2960 Package. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs.".
2962 @param ECX MSR_SANDY_BRIDGE_MCi_ADDR
2963 @param EAX Lower 32-bits of MSR value.
2964 @param EDX Upper 32-bits of MSR value.
2966 <b>Example usage</b>
2970 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_ADDR);
2971 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_ADDR, Msr);
2973 @note MSR_SANDY_BRIDGE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
2974 MSR_SANDY_BRIDGE_MC6_ADDR is defined as MSR_MC6_ADDR in SDM.
2975 MSR_SANDY_BRIDGE_MC7_ADDR is defined as MSR_MC7_ADDR in SDM.
2976 MSR_SANDY_BRIDGE_MC8_ADDR is defined as MSR_MC8_ADDR in SDM.
2977 MSR_SANDY_BRIDGE_MC9_ADDR is defined as MSR_MC9_ADDR in SDM.
2978 MSR_SANDY_BRIDGE_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.
2979 MSR_SANDY_BRIDGE_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.
2980 MSR_SANDY_BRIDGE_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.
2981 MSR_SANDY_BRIDGE_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.
2982 MSR_SANDY_BRIDGE_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.
2983 MSR_SANDY_BRIDGE_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.
2984 MSR_SANDY_BRIDGE_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.
2985 MSR_SANDY_BRIDGE_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.
2986 MSR_SANDY_BRIDGE_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.
2987 MSR_SANDY_BRIDGE_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.
2990 #define MSR_SANDY_BRIDGE_MC5_ADDR 0x00000416
2991 #define MSR_SANDY_BRIDGE_MC6_ADDR 0x0000041A
2992 #define MSR_SANDY_BRIDGE_MC7_ADDR 0x0000041E
2993 #define MSR_SANDY_BRIDGE_MC8_ADDR 0x00000422
2994 #define MSR_SANDY_BRIDGE_MC9_ADDR 0x00000426
2995 #define MSR_SANDY_BRIDGE_MC10_ADDR 0x0000042A
2996 #define MSR_SANDY_BRIDGE_MC11_ADDR 0x0000042E
2997 #define MSR_SANDY_BRIDGE_MC12_ADDR 0x00000432
2998 #define MSR_SANDY_BRIDGE_MC13_ADDR 0x00000436
2999 #define MSR_SANDY_BRIDGE_MC14_ADDR 0x0000043A
3000 #define MSR_SANDY_BRIDGE_MC15_ADDR 0x0000043E
3001 #define MSR_SANDY_BRIDGE_MC16_ADDR 0x00000442
3002 #define MSR_SANDY_BRIDGE_MC17_ADDR 0x00000446
3003 #define MSR_SANDY_BRIDGE_MC18_ADDR 0x0000044A
3004 #define MSR_SANDY_BRIDGE_MC19_ADDR 0x0000044E
3009 Package. See Section 15.3.2.4, "IA32_MCi_MISC MSRs.".
3011 @param ECX MSR_SANDY_BRIDGE_MCi_MISC
3012 @param EAX Lower 32-bits of MSR value.
3013 @param EDX Upper 32-bits of MSR value.
3015 <b>Example usage</b>
3019 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_MISC);
3020 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_MISC, Msr);
3022 @note MSR_SANDY_BRIDGE_MC5_MISC is defined as MSR_MC5_MISC in SDM.
3023 MSR_SANDY_BRIDGE_MC6_MISC is defined as MSR_MC6_MISC in SDM.
3024 MSR_SANDY_BRIDGE_MC7_MISC is defined as MSR_MC7_MISC in SDM.
3025 MSR_SANDY_BRIDGE_MC8_MISC is defined as MSR_MC8_MISC in SDM.
3026 MSR_SANDY_BRIDGE_MC9_MISC is defined as MSR_MC9_MISC in SDM.
3027 MSR_SANDY_BRIDGE_MC10_MISC is defined as MSR_MC10_MISC in SDM.
3028 MSR_SANDY_BRIDGE_MC11_MISC is defined as MSR_MC11_MISC in SDM.
3029 MSR_SANDY_BRIDGE_MC12_MISC is defined as MSR_MC12_MISC in SDM.
3030 MSR_SANDY_BRIDGE_MC13_MISC is defined as MSR_MC13_MISC in SDM.
3031 MSR_SANDY_BRIDGE_MC14_MISC is defined as MSR_MC14_MISC in SDM.
3032 MSR_SANDY_BRIDGE_MC15_MISC is defined as MSR_MC15_MISC in SDM.
3033 MSR_SANDY_BRIDGE_MC16_MISC is defined as MSR_MC16_MISC in SDM.
3034 MSR_SANDY_BRIDGE_MC17_MISC is defined as MSR_MC17_MISC in SDM.
3035 MSR_SANDY_BRIDGE_MC18_MISC is defined as MSR_MC18_MISC in SDM.
3036 MSR_SANDY_BRIDGE_MC19_MISC is defined as MSR_MC19_MISC in SDM.
3039 #define MSR_SANDY_BRIDGE_MC5_MISC 0x00000417
3040 #define MSR_SANDY_BRIDGE_MC6_MISC 0x0000041B
3041 #define MSR_SANDY_BRIDGE_MC7_MISC 0x0000041F
3042 #define MSR_SANDY_BRIDGE_MC8_MISC 0x00000423
3043 #define MSR_SANDY_BRIDGE_MC9_MISC 0x00000427
3044 #define MSR_SANDY_BRIDGE_MC10_MISC 0x0000042B
3045 #define MSR_SANDY_BRIDGE_MC11_MISC 0x0000042F
3046 #define MSR_SANDY_BRIDGE_MC12_MISC 0x00000433
3047 #define MSR_SANDY_BRIDGE_MC13_MISC 0x00000437
3048 #define MSR_SANDY_BRIDGE_MC14_MISC 0x0000043B
3049 #define MSR_SANDY_BRIDGE_MC15_MISC 0x0000043F
3050 #define MSR_SANDY_BRIDGE_MC16_MISC 0x00000443
3051 #define MSR_SANDY_BRIDGE_MC17_MISC 0x00000447
3052 #define MSR_SANDY_BRIDGE_MC18_MISC 0x0000044B
3053 #define MSR_SANDY_BRIDGE_MC19_MISC 0x0000044F
3058 Package. Package RAPL Perf Status (R/O).
3060 @param ECX MSR_SANDY_BRIDGE_PKG_PERF_STATUS (0x00000613)
3061 @param EAX Lower 32-bits of MSR value.
3062 @param EDX Upper 32-bits of MSR value.
3064 <b>Example usage</b>
3068 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_PERF_STATUS);
3070 @note MSR_SANDY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
3072 #define MSR_SANDY_BRIDGE_PKG_PERF_STATUS 0x00000613
3076 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
3079 @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)
3080 @param EAX Lower 32-bits of MSR value.
3081 @param EDX Upper 32-bits of MSR value.
3083 <b>Example usage</b>
3087 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT);
3088 AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT, Msr);
3090 @note MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
3092 #define MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT 0x00000618
3096 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
3098 @param ECX MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)
3099 @param EAX Lower 32-bits of MSR value.
3100 @param EDX Upper 32-bits of MSR value.
3102 <b>Example usage</b>
3106 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS);
3108 @note MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
3110 #define MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619
3114 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
3117 @param ECX MSR_SANDY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)
3118 @param EAX Lower 32-bits of MSR value.
3119 @param EDX Upper 32-bits of MSR value.
3121 <b>Example usage</b>
3125 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_PERF_STATUS);
3127 @note MSR_SANDY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
3129 #define MSR_SANDY_BRIDGE_DRAM_PERF_STATUS 0x0000061B
3133 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
3135 @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_INFO (0x0000061C)
3136 @param EAX Lower 32-bits of MSR value.
3137 @param EDX Upper 32-bits of MSR value.
3139 <b>Example usage</b>
3143 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO);
3144 AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO, Msr);
3146 @note MSR_SANDY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
3148 #define MSR_SANDY_BRIDGE_DRAM_POWER_INFO 0x0000061C
3152 Package. Uncore U-box UCLK fixed counter control.
3154 @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL (0x00000C08)
3155 @param EAX Lower 32-bits of MSR value.
3156 @param EDX Upper 32-bits of MSR value.
3158 <b>Example usage</b>
3162 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL);
3163 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL, Msr);
3165 @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.
3167 #define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL 0x00000C08
3171 Package. Uncore U-box UCLK fixed counter.
3173 @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR (0x00000C09)
3174 @param EAX Lower 32-bits of MSR value.
3175 @param EDX Upper 32-bits of MSR value.
3177 <b>Example usage</b>
3181 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR);
3182 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR, Msr);
3184 @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.
3186 #define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR 0x00000C09
3190 Package. Uncore U-box perfmon event select for U-box counter 0.
3192 @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 (0x00000C10)
3193 @param EAX Lower 32-bits of MSR value.
3194 @param EDX Upper 32-bits of MSR value.
3196 <b>Example usage</b>
3200 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0);
3201 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0, Msr);
3203 @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.
3205 #define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 0x00000C10
3209 Package. Uncore U-box perfmon event select for U-box counter 1.
3211 @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 (0x00000C11)
3212 @param EAX Lower 32-bits of MSR value.
3213 @param EDX Upper 32-bits of MSR value.
3215 <b>Example usage</b>
3219 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1);
3220 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1, Msr);
3222 @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.
3224 #define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 0x00000C11
3228 Package. Uncore U-box perfmon counter 0.
3230 @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR0 (0x00000C16)
3231 @param EAX Lower 32-bits of MSR value.
3232 @param EDX Upper 32-bits of MSR value.
3234 <b>Example usage</b>
3238 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0);
3239 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0, Msr);
3241 @note MSR_SANDY_BRIDGE_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.
3243 #define MSR_SANDY_BRIDGE_U_PMON_CTR0 0x00000C16
3247 Package. Uncore U-box perfmon counter 1.
3249 @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR1 (0x00000C17)
3250 @param EAX Lower 32-bits of MSR value.
3251 @param EDX Upper 32-bits of MSR value.
3253 <b>Example usage</b>
3257 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1);
3258 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1, Msr);
3260 @note MSR_SANDY_BRIDGE_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.
3262 #define MSR_SANDY_BRIDGE_U_PMON_CTR1 0x00000C17
3266 Package. Uncore PCU perfmon for PCU-box-wide control.
3268 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL (0x00000C24)
3269 @param EAX Lower 32-bits of MSR value.
3270 @param EDX Upper 32-bits of MSR value.
3272 <b>Example usage</b>
3276 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL);
3277 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL, Msr);
3279 @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.
3281 #define MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL 0x00000C24
3285 Package. Uncore PCU perfmon event select for PCU counter 0.
3287 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 (0x00000C30)
3288 @param EAX Lower 32-bits of MSR value.
3289 @param EDX Upper 32-bits of MSR value.
3291 <b>Example usage</b>
3295 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0);
3296 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0, Msr);
3298 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.
3300 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 0x00000C30
3304 Package. Uncore PCU perfmon event select for PCU counter 1.
3306 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 (0x00000C31)
3307 @param EAX Lower 32-bits of MSR value.
3308 @param EDX Upper 32-bits of MSR value.
3310 <b>Example usage</b>
3314 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1);
3315 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1, Msr);
3317 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.
3319 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 0x00000C31
3323 Package. Uncore PCU perfmon event select for PCU counter 2.
3325 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 (0x00000C32)
3326 @param EAX Lower 32-bits of MSR value.
3327 @param EDX Upper 32-bits of MSR value.
3329 <b>Example usage</b>
3333 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2);
3334 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2, Msr);
3336 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.
3338 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 0x00000C32
3342 Package. Uncore PCU perfmon event select for PCU counter 3.
3344 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 (0x00000C33)
3345 @param EAX Lower 32-bits of MSR value.
3346 @param EDX Upper 32-bits of MSR value.
3348 <b>Example usage</b>
3352 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3);
3353 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3, Msr);
3355 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.
3357 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 0x00000C33
3361 Package. Uncore PCU perfmon box-wide filter.
3363 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER (0x00000C34)
3364 @param EAX Lower 32-bits of MSR value.
3365 @param EDX Upper 32-bits of MSR value.
3367 <b>Example usage</b>
3371 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER);
3372 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER, Msr);
3374 @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.
3376 #define MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER 0x00000C34
3380 Package. Uncore PCU perfmon counter 0.
3382 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR0 (0x00000C36)
3383 @param EAX Lower 32-bits of MSR value.
3384 @param EDX Upper 32-bits of MSR value.
3386 <b>Example usage</b>
3390 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0);
3391 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0, Msr);
3393 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.
3395 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR0 0x00000C36
3399 Package. Uncore PCU perfmon counter 1.
3401 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR1 (0x00000C37)
3402 @param EAX Lower 32-bits of MSR value.
3403 @param EDX Upper 32-bits of MSR value.
3405 <b>Example usage</b>
3409 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1);
3410 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1, Msr);
3412 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.
3414 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR1 0x00000C37
3418 Package. Uncore PCU perfmon counter 2.
3420 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR2 (0x00000C38)
3421 @param EAX Lower 32-bits of MSR value.
3422 @param EDX Upper 32-bits of MSR value.
3424 <b>Example usage</b>
3428 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2);
3429 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2, Msr);
3431 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.
3433 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR2 0x00000C38
3437 Package. Uncore PCU perfmon counter 3.
3439 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR3 (0x00000C39)
3440 @param EAX Lower 32-bits of MSR value.
3441 @param EDX Upper 32-bits of MSR value.
3443 <b>Example usage</b>
3447 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3);
3448 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3, Msr);
3450 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.
3452 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR3 0x00000C39
3456 Package. Uncore C-box 0 perfmon local box wide control.
3458 @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL (0x00000D04)
3459 @param EAX Lower 32-bits of MSR value.
3460 @param EDX Upper 32-bits of MSR value.
3462 <b>Example usage</b>
3466 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL);
3467 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL, Msr);
3469 @note MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.
3471 #define MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL 0x00000D04
3475 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.
3477 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 (0x00000D10)
3478 @param EAX Lower 32-bits of MSR value.
3479 @param EDX Upper 32-bits of MSR value.
3481 <b>Example usage</b>
3485 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0);
3486 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0, Msr);
3488 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.
3490 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 0x00000D10
3494 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.
3496 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 (0x00000D11)
3497 @param EAX Lower 32-bits of MSR value.
3498 @param EDX Upper 32-bits of MSR value.
3500 <b>Example usage</b>
3504 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1);
3505 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1, Msr);
3507 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.
3509 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 0x00000D11
3513 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.
3515 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 (0x00000D12)
3516 @param EAX Lower 32-bits of MSR value.
3517 @param EDX Upper 32-bits of MSR value.
3519 <b>Example usage</b>
3523 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2);
3524 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2, Msr);
3526 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.
3528 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 0x00000D12
3532 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.
3534 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 (0x00000D13)
3535 @param EAX Lower 32-bits of MSR value.
3536 @param EDX Upper 32-bits of MSR value.
3538 <b>Example usage</b>
3542 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3);
3543 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3, Msr);
3545 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.
3547 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 0x00000D13
3551 Package. Uncore C-box 0 perfmon box wide filter.
3553 @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER (0x00000D14)
3554 @param EAX Lower 32-bits of MSR value.
3555 @param EDX Upper 32-bits of MSR value.
3557 <b>Example usage</b>
3561 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER);
3562 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER, Msr);
3564 @note MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER is defined as MSR_C0_PMON_BOX_FILTER in SDM.
3566 #define MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER 0x00000D14
3570 Package. Uncore C-box 0 perfmon counter 0.
3572 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR0 (0x00000D16)
3573 @param EAX Lower 32-bits of MSR value.
3574 @param EDX Upper 32-bits of MSR value.
3576 <b>Example usage</b>
3580 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0);
3581 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0, Msr);
3583 @note MSR_SANDY_BRIDGE_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
3585 #define MSR_SANDY_BRIDGE_C0_PMON_CTR0 0x00000D16
3589 Package. Uncore C-box 0 perfmon counter 1.
3591 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR1 (0x00000D17)
3592 @param EAX Lower 32-bits of MSR value.
3593 @param EDX Upper 32-bits of MSR value.
3595 <b>Example usage</b>
3599 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1);
3600 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1, Msr);
3602 @note MSR_SANDY_BRIDGE_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
3604 #define MSR_SANDY_BRIDGE_C0_PMON_CTR1 0x00000D17
3608 Package. Uncore C-box 0 perfmon counter 2.
3610 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR2 (0x00000D18)
3611 @param EAX Lower 32-bits of MSR value.
3612 @param EDX Upper 32-bits of MSR value.
3614 <b>Example usage</b>
3618 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2);
3619 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2, Msr);
3621 @note MSR_SANDY_BRIDGE_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
3623 #define MSR_SANDY_BRIDGE_C0_PMON_CTR2 0x00000D18
3627 Package. Uncore C-box 0 perfmon counter 3.
3629 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR3 (0x00000D19)
3630 @param EAX Lower 32-bits of MSR value.
3631 @param EDX Upper 32-bits of MSR value.
3633 <b>Example usage</b>
3637 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3);
3638 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3, Msr);
3640 @note MSR_SANDY_BRIDGE_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
3642 #define MSR_SANDY_BRIDGE_C0_PMON_CTR3 0x00000D19
3646 Package. Uncore C-box 1 perfmon local box wide control.
3648 @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL (0x00000D24)
3649 @param EAX Lower 32-bits of MSR value.
3650 @param EDX Upper 32-bits of MSR value.
3652 <b>Example usage</b>
3656 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL);
3657 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL, Msr);
3659 @note MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.
3661 #define MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL 0x00000D24
3665 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.
3667 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 (0x00000D30)
3668 @param EAX Lower 32-bits of MSR value.
3669 @param EDX Upper 32-bits of MSR value.
3671 <b>Example usage</b>
3675 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0);
3676 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0, Msr);
3678 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.
3680 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 0x00000D30
3684 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.
3686 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 (0x00000D31)
3687 @param EAX Lower 32-bits of MSR value.
3688 @param EDX Upper 32-bits of MSR value.
3690 <b>Example usage</b>
3694 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1);
3695 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1, Msr);
3697 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.
3699 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 0x00000D31
3703 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.
3705 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 (0x00000D32)
3706 @param EAX Lower 32-bits of MSR value.
3707 @param EDX Upper 32-bits of MSR value.
3709 <b>Example usage</b>
3713 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2);
3714 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2, Msr);
3716 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.
3718 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 0x00000D32
3722 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.
3724 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 (0x00000D33)
3725 @param EAX Lower 32-bits of MSR value.
3726 @param EDX Upper 32-bits of MSR value.
3728 <b>Example usage</b>
3732 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3);
3733 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3, Msr);
3735 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.
3737 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 0x00000D33
3741 Package. Uncore C-box 1 perfmon box wide filter.
3743 @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER (0x00000D34)
3744 @param EAX Lower 32-bits of MSR value.
3745 @param EDX Upper 32-bits of MSR value.
3747 <b>Example usage</b>
3751 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER);
3752 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER, Msr);
3754 @note MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER is defined as MSR_C1_PMON_BOX_FILTER in SDM.
3756 #define MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER 0x00000D34
3760 Package. Uncore C-box 1 perfmon counter 0.
3762 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR0 (0x00000D36)
3763 @param EAX Lower 32-bits of MSR value.
3764 @param EDX Upper 32-bits of MSR value.
3766 <b>Example usage</b>
3770 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0);
3771 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0, Msr);
3773 @note MSR_SANDY_BRIDGE_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
3775 #define MSR_SANDY_BRIDGE_C1_PMON_CTR0 0x00000D36
3779 Package. Uncore C-box 1 perfmon counter 1.
3781 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR1 (0x00000D37)
3782 @param EAX Lower 32-bits of MSR value.
3783 @param EDX Upper 32-bits of MSR value.
3785 <b>Example usage</b>
3789 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1);
3790 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1, Msr);
3792 @note MSR_SANDY_BRIDGE_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
3794 #define MSR_SANDY_BRIDGE_C1_PMON_CTR1 0x00000D37
3798 Package. Uncore C-box 1 perfmon counter 2.
3800 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR2 (0x00000D38)
3801 @param EAX Lower 32-bits of MSR value.
3802 @param EDX Upper 32-bits of MSR value.
3804 <b>Example usage</b>
3808 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2);
3809 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2, Msr);
3811 @note MSR_SANDY_BRIDGE_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
3813 #define MSR_SANDY_BRIDGE_C1_PMON_CTR2 0x00000D38
3817 Package. Uncore C-box 1 perfmon counter 3.
3819 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR3 (0x00000D39)
3820 @param EAX Lower 32-bits of MSR value.
3821 @param EDX Upper 32-bits of MSR value.
3823 <b>Example usage</b>
3827 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3);
3828 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3, Msr);
3830 @note MSR_SANDY_BRIDGE_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
3832 #define MSR_SANDY_BRIDGE_C1_PMON_CTR3 0x00000D39
3836 Package. Uncore C-box 2 perfmon local box wide control.
3838 @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL (0x00000D44)
3839 @param EAX Lower 32-bits of MSR value.
3840 @param EDX Upper 32-bits of MSR value.
3842 <b>Example usage</b>
3846 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL);
3847 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL, Msr);
3849 @note MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.
3851 #define MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL 0x00000D44
3855 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.
3857 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 (0x00000D50)
3858 @param EAX Lower 32-bits of MSR value.
3859 @param EDX Upper 32-bits of MSR value.
3861 <b>Example usage</b>
3865 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0);
3866 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0, Msr);
3868 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.
3870 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 0x00000D50
3874 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.
3876 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 (0x00000D51)
3877 @param EAX Lower 32-bits of MSR value.
3878 @param EDX Upper 32-bits of MSR value.
3880 <b>Example usage</b>
3884 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1);
3885 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1, Msr);
3887 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.
3889 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 0x00000D51
3893 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.
3895 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 (0x00000D52)
3896 @param EAX Lower 32-bits of MSR value.
3897 @param EDX Upper 32-bits of MSR value.
3899 <b>Example usage</b>
3903 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2);
3904 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2, Msr);
3906 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.
3908 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 0x00000D52
3912 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.
3914 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 (0x00000D53)
3915 @param EAX Lower 32-bits of MSR value.
3916 @param EDX Upper 32-bits of MSR value.
3918 <b>Example usage</b>
3922 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3);
3923 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3, Msr);
3925 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.
3927 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 0x00000D53
3931 Package. Uncore C-box 2 perfmon box wide filter.
3933 @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER (0x00000D54)
3934 @param EAX Lower 32-bits of MSR value.
3935 @param EDX Upper 32-bits of MSR value.
3937 <b>Example usage</b>
3941 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER);
3942 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER, Msr);
3944 @note MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER is defined as MSR_C2_PMON_BOX_FILTER in SDM.
3946 #define MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER 0x00000D54
3950 Package. Uncore C-box 2 perfmon counter 0.
3952 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR0 (0x00000D56)
3953 @param EAX Lower 32-bits of MSR value.
3954 @param EDX Upper 32-bits of MSR value.
3956 <b>Example usage</b>
3960 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0);
3961 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0, Msr);
3963 @note MSR_SANDY_BRIDGE_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
3965 #define MSR_SANDY_BRIDGE_C2_PMON_CTR0 0x00000D56
3969 Package. Uncore C-box 2 perfmon counter 1.
3971 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR1 (0x00000D57)
3972 @param EAX Lower 32-bits of MSR value.
3973 @param EDX Upper 32-bits of MSR value.
3975 <b>Example usage</b>
3979 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1);
3980 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1, Msr);
3982 @note MSR_SANDY_BRIDGE_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
3984 #define MSR_SANDY_BRIDGE_C2_PMON_CTR1 0x00000D57
3988 Package. Uncore C-box 2 perfmon counter 2.
3990 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR2 (0x00000D58)
3991 @param EAX Lower 32-bits of MSR value.
3992 @param EDX Upper 32-bits of MSR value.
3994 <b>Example usage</b>
3998 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2);
3999 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2, Msr);
4001 @note MSR_SANDY_BRIDGE_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
4003 #define MSR_SANDY_BRIDGE_C2_PMON_CTR2 0x00000D58
4007 Package. Uncore C-box 2 perfmon counter 3.
4009 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR3 (0x00000D59)
4010 @param EAX Lower 32-bits of MSR value.
4011 @param EDX Upper 32-bits of MSR value.
4013 <b>Example usage</b>
4017 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3);
4018 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3, Msr);
4020 @note MSR_SANDY_BRIDGE_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
4022 #define MSR_SANDY_BRIDGE_C2_PMON_CTR3 0x00000D59
4026 Package. Uncore C-box 3 perfmon local box wide control.
4028 @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL (0x00000D64)
4029 @param EAX Lower 32-bits of MSR value.
4030 @param EDX Upper 32-bits of MSR value.
4032 <b>Example usage</b>
4036 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL);
4037 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL, Msr);
4039 @note MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.
4041 #define MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL 0x00000D64
4045 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.
4047 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 (0x00000D70)
4048 @param EAX Lower 32-bits of MSR value.
4049 @param EDX Upper 32-bits of MSR value.
4051 <b>Example usage</b>
4055 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0);
4056 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0, Msr);
4058 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.
4060 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 0x00000D70
4064 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.
4066 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 (0x00000D71)
4067 @param EAX Lower 32-bits of MSR value.
4068 @param EDX Upper 32-bits of MSR value.
4070 <b>Example usage</b>
4074 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1);
4075 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1, Msr);
4077 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.
4079 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 0x00000D71
4083 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.
4085 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 (0x00000D72)
4086 @param EAX Lower 32-bits of MSR value.
4087 @param EDX Upper 32-bits of MSR value.
4089 <b>Example usage</b>
4093 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2);
4094 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2, Msr);
4096 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.
4098 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 0x00000D72
4102 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.
4104 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 (0x00000D73)
4105 @param EAX Lower 32-bits of MSR value.
4106 @param EDX Upper 32-bits of MSR value.
4108 <b>Example usage</b>
4112 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3);
4113 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3, Msr);
4115 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.
4117 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 0x00000D73
4121 Package. Uncore C-box 3 perfmon box wide filter.
4123 @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER (0x00000D74)
4124 @param EAX Lower 32-bits of MSR value.
4125 @param EDX Upper 32-bits of MSR value.
4127 <b>Example usage</b>
4131 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER);
4132 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER, Msr);
4134 @note MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER is defined as MSR_C3_PMON_BOX_FILTER in SDM.
4136 #define MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER 0x00000D74
4140 Package. Uncore C-box 3 perfmon counter 0.
4142 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR0 (0x00000D76)
4143 @param EAX Lower 32-bits of MSR value.
4144 @param EDX Upper 32-bits of MSR value.
4146 <b>Example usage</b>
4150 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0);
4151 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0, Msr);
4153 @note MSR_SANDY_BRIDGE_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
4155 #define MSR_SANDY_BRIDGE_C3_PMON_CTR0 0x00000D76
4159 Package. Uncore C-box 3 perfmon counter 1.
4161 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR1 (0x00000D77)
4162 @param EAX Lower 32-bits of MSR value.
4163 @param EDX Upper 32-bits of MSR value.
4165 <b>Example usage</b>
4169 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1);
4170 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1, Msr);
4172 @note MSR_SANDY_BRIDGE_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
4174 #define MSR_SANDY_BRIDGE_C3_PMON_CTR1 0x00000D77
4178 Package. Uncore C-box 3 perfmon counter 2.
4180 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR2 (0x00000D78)
4181 @param EAX Lower 32-bits of MSR value.
4182 @param EDX Upper 32-bits of MSR value.
4184 <b>Example usage</b>
4188 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2);
4189 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2, Msr);
4191 @note MSR_SANDY_BRIDGE_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
4193 #define MSR_SANDY_BRIDGE_C3_PMON_CTR2 0x00000D78
4197 Package. Uncore C-box 3 perfmon counter 3.
4199 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR3 (0x00000D79)
4200 @param EAX Lower 32-bits of MSR value.
4201 @param EDX Upper 32-bits of MSR value.
4203 <b>Example usage</b>
4207 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3);
4208 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3, Msr);
4210 @note MSR_SANDY_BRIDGE_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
4212 #define MSR_SANDY_BRIDGE_C3_PMON_CTR3 0x00000D79
4216 Package. Uncore C-box 4 perfmon local box wide control.
4218 @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL (0x00000D84)
4219 @param EAX Lower 32-bits of MSR value.
4220 @param EDX Upper 32-bits of MSR value.
4222 <b>Example usage</b>
4226 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL);
4227 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL, Msr);
4229 @note MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.
4231 #define MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL 0x00000D84
4235 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.
4237 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 (0x00000D90)
4238 @param EAX Lower 32-bits of MSR value.
4239 @param EDX Upper 32-bits of MSR value.
4241 <b>Example usage</b>
4245 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0);
4246 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0, Msr);
4248 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.
4250 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 0x00000D90
4254 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.
4256 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 (0x00000D91)
4257 @param EAX Lower 32-bits of MSR value.
4258 @param EDX Upper 32-bits of MSR value.
4260 <b>Example usage</b>
4264 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1);
4265 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1, Msr);
4267 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.
4269 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 0x00000D91
4273 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.
4275 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 (0x00000D92)
4276 @param EAX Lower 32-bits of MSR value.
4277 @param EDX Upper 32-bits of MSR value.
4279 <b>Example usage</b>
4283 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2);
4284 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2, Msr);
4286 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.
4288 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 0x00000D92
4292 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.
4294 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 (0x00000D93)
4295 @param EAX Lower 32-bits of MSR value.
4296 @param EDX Upper 32-bits of MSR value.
4298 <b>Example usage</b>
4302 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3);
4303 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3, Msr);
4305 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.
4307 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 0x00000D93
4311 Package. Uncore C-box 4 perfmon box wide filter.
4313 @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER (0x00000D94)
4314 @param EAX Lower 32-bits of MSR value.
4315 @param EDX Upper 32-bits of MSR value.
4317 <b>Example usage</b>
4321 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER);
4322 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER, Msr);
4324 @note MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER is defined as MSR_C4_PMON_BOX_FILTER in SDM.
4326 #define MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER 0x00000D94
4330 Package. Uncore C-box 4 perfmon counter 0.
4332 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR0 (0x00000D96)
4333 @param EAX Lower 32-bits of MSR value.
4334 @param EDX Upper 32-bits of MSR value.
4336 <b>Example usage</b>
4340 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0);
4341 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0, Msr);
4343 @note MSR_SANDY_BRIDGE_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
4345 #define MSR_SANDY_BRIDGE_C4_PMON_CTR0 0x00000D96
4349 Package. Uncore C-box 4 perfmon counter 1.
4351 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR1 (0x00000D97)
4352 @param EAX Lower 32-bits of MSR value.
4353 @param EDX Upper 32-bits of MSR value.
4355 <b>Example usage</b>
4359 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1);
4360 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1, Msr);
4362 @note MSR_SANDY_BRIDGE_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
4364 #define MSR_SANDY_BRIDGE_C4_PMON_CTR1 0x00000D97
4368 Package. Uncore C-box 4 perfmon counter 2.
4370 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR2 (0x00000D98)
4371 @param EAX Lower 32-bits of MSR value.
4372 @param EDX Upper 32-bits of MSR value.
4374 <b>Example usage</b>
4378 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2);
4379 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2, Msr);
4381 @note MSR_SANDY_BRIDGE_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
4383 #define MSR_SANDY_BRIDGE_C4_PMON_CTR2 0x00000D98
4387 Package. Uncore C-box 4 perfmon counter 3.
4389 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR3 (0x00000D99)
4390 @param EAX Lower 32-bits of MSR value.
4391 @param EDX Upper 32-bits of MSR value.
4393 <b>Example usage</b>
4397 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3);
4398 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3, Msr);
4400 @note MSR_SANDY_BRIDGE_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
4402 #define MSR_SANDY_BRIDGE_C4_PMON_CTR3 0x00000D99
4406 Package. Uncore C-box 5 perfmon local box wide control.
4408 @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL (0x00000DA4)
4409 @param EAX Lower 32-bits of MSR value.
4410 @param EDX Upper 32-bits of MSR value.
4412 <b>Example usage</b>
4416 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL);
4417 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL, Msr);
4419 @note MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.
4421 #define MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL 0x00000DA4
4425 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.
4427 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 (0x00000DB0)
4428 @param EAX Lower 32-bits of MSR value.
4429 @param EDX Upper 32-bits of MSR value.
4431 <b>Example usage</b>
4435 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0);
4436 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0, Msr);
4438 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.
4440 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 0x00000DB0
4444 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.
4446 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 (0x00000DB1)
4447 @param EAX Lower 32-bits of MSR value.
4448 @param EDX Upper 32-bits of MSR value.
4450 <b>Example usage</b>
4454 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1);
4455 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1, Msr);
4457 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.
4459 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 0x00000DB1
4463 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.
4465 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 (0x00000DB2)
4466 @param EAX Lower 32-bits of MSR value.
4467 @param EDX Upper 32-bits of MSR value.
4469 <b>Example usage</b>
4473 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2);
4474 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2, Msr);
4476 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.
4478 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 0x00000DB2
4482 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.
4484 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 (0x00000DB3)
4485 @param EAX Lower 32-bits of MSR value.
4486 @param EDX Upper 32-bits of MSR value.
4488 <b>Example usage</b>
4492 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3);
4493 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3, Msr);
4495 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.
4497 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 0x00000DB3
4501 Package. Uncore C-box 5 perfmon box wide filter.
4503 @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER (0x00000DB4)
4504 @param EAX Lower 32-bits of MSR value.
4505 @param EDX Upper 32-bits of MSR value.
4507 <b>Example usage</b>
4511 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER);
4512 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER, Msr);
4514 @note MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER is defined as MSR_C5_PMON_BOX_FILTER in SDM.
4516 #define MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER 0x00000DB4
4520 Package. Uncore C-box 5 perfmon counter 0.
4522 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR0 (0x00000DB6)
4523 @param EAX Lower 32-bits of MSR value.
4524 @param EDX Upper 32-bits of MSR value.
4526 <b>Example usage</b>
4530 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0);
4531 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0, Msr);
4533 @note MSR_SANDY_BRIDGE_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
4535 #define MSR_SANDY_BRIDGE_C5_PMON_CTR0 0x00000DB6
4539 Package. Uncore C-box 5 perfmon counter 1.
4541 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR1 (0x00000DB7)
4542 @param EAX Lower 32-bits of MSR value.
4543 @param EDX Upper 32-bits of MSR value.
4545 <b>Example usage</b>
4549 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1);
4550 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1, Msr);
4552 @note MSR_SANDY_BRIDGE_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
4554 #define MSR_SANDY_BRIDGE_C5_PMON_CTR1 0x00000DB7
4558 Package. Uncore C-box 5 perfmon counter 2.
4560 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR2 (0x00000DB8)
4561 @param EAX Lower 32-bits of MSR value.
4562 @param EDX Upper 32-bits of MSR value.
4564 <b>Example usage</b>
4568 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2);
4569 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2, Msr);
4571 @note MSR_SANDY_BRIDGE_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
4573 #define MSR_SANDY_BRIDGE_C5_PMON_CTR2 0x00000DB8
4577 Package. Uncore C-box 5 perfmon counter 3.
4579 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR3 (0x00000DB9)
4580 @param EAX Lower 32-bits of MSR value.
4581 @param EDX Upper 32-bits of MSR value.
4583 <b>Example usage</b>
4587 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3);
4588 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3, Msr);
4590 @note MSR_SANDY_BRIDGE_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
4592 #define MSR_SANDY_BRIDGE_C5_PMON_CTR3 0x00000DB9
4596 Package. Uncore C-box 6 perfmon local box wide control.
4598 @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL (0x00000DC4)
4599 @param EAX Lower 32-bits of MSR value.
4600 @param EDX Upper 32-bits of MSR value.
4602 <b>Example usage</b>
4606 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL);
4607 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL, Msr);
4609 @note MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.
4611 #define MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL 0x00000DC4
4615 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.
4617 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 (0x00000DD0)
4618 @param EAX Lower 32-bits of MSR value.
4619 @param EDX Upper 32-bits of MSR value.
4621 <b>Example usage</b>
4625 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0);
4626 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0, Msr);
4628 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.
4630 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 0x00000DD0
4634 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.
4636 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 (0x00000DD1)
4637 @param EAX Lower 32-bits of MSR value.
4638 @param EDX Upper 32-bits of MSR value.
4640 <b>Example usage</b>
4644 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1);
4645 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1, Msr);
4647 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.
4649 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 0x00000DD1
4653 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.
4655 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 (0x00000DD2)
4656 @param EAX Lower 32-bits of MSR value.
4657 @param EDX Upper 32-bits of MSR value.
4659 <b>Example usage</b>
4663 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2);
4664 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2, Msr);
4666 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.
4668 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 0x00000DD2
4672 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.
4674 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 (0x00000DD3)
4675 @param EAX Lower 32-bits of MSR value.
4676 @param EDX Upper 32-bits of MSR value.
4678 <b>Example usage</b>
4682 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3);
4683 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3, Msr);
4685 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.
4687 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 0x00000DD3
4691 Package. Uncore C-box 6 perfmon box wide filter.
4693 @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER (0x00000DD4)
4694 @param EAX Lower 32-bits of MSR value.
4695 @param EDX Upper 32-bits of MSR value.
4697 <b>Example usage</b>
4701 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER);
4702 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER, Msr);
4704 @note MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER is defined as MSR_C6_PMON_BOX_FILTER in SDM.
4706 #define MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER 0x00000DD4
4710 Package. Uncore C-box 6 perfmon counter 0.
4712 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR0 (0x00000DD6)
4713 @param EAX Lower 32-bits of MSR value.
4714 @param EDX Upper 32-bits of MSR value.
4716 <b>Example usage</b>
4720 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0);
4721 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0, Msr);
4723 @note MSR_SANDY_BRIDGE_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
4725 #define MSR_SANDY_BRIDGE_C6_PMON_CTR0 0x00000DD6
4729 Package. Uncore C-box 6 perfmon counter 1.
4731 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR1 (0x00000DD7)
4732 @param EAX Lower 32-bits of MSR value.
4733 @param EDX Upper 32-bits of MSR value.
4735 <b>Example usage</b>
4739 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1);
4740 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1, Msr);
4742 @note MSR_SANDY_BRIDGE_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
4744 #define MSR_SANDY_BRIDGE_C6_PMON_CTR1 0x00000DD7
4748 Package. Uncore C-box 6 perfmon counter 2.
4750 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR2 (0x00000DD8)
4751 @param EAX Lower 32-bits of MSR value.
4752 @param EDX Upper 32-bits of MSR value.
4754 <b>Example usage</b>
4758 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2);
4759 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2, Msr);
4761 @note MSR_SANDY_BRIDGE_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
4763 #define MSR_SANDY_BRIDGE_C6_PMON_CTR2 0x00000DD8
4767 Package. Uncore C-box 6 perfmon counter 3.
4769 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR3 (0x00000DD9)
4770 @param EAX Lower 32-bits of MSR value.
4771 @param EDX Upper 32-bits of MSR value.
4773 <b>Example usage</b>
4777 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3);
4778 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3, Msr);
4780 @note MSR_SANDY_BRIDGE_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
4782 #define MSR_SANDY_BRIDGE_C6_PMON_CTR3 0x00000DD9
4786 Package. Uncore C-box 7 perfmon local box wide control.
4788 @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL (0x00000DE4)
4789 @param EAX Lower 32-bits of MSR value.
4790 @param EDX Upper 32-bits of MSR value.
4792 <b>Example usage</b>
4796 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL);
4797 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL, Msr);
4799 @note MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.
4801 #define MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL 0x00000DE4
4805 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.
4807 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 (0x00000DF0)
4808 @param EAX Lower 32-bits of MSR value.
4809 @param EDX Upper 32-bits of MSR value.
4811 <b>Example usage</b>
4815 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0);
4816 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0, Msr);
4818 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.
4820 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 0x00000DF0
4824 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.
4826 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 (0x00000DF1)
4827 @param EAX Lower 32-bits of MSR value.
4828 @param EDX Upper 32-bits of MSR value.
4830 <b>Example usage</b>
4834 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1);
4835 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1, Msr);
4837 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.
4839 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 0x00000DF1
4843 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.
4845 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 (0x00000DF2)
4846 @param EAX Lower 32-bits of MSR value.
4847 @param EDX Upper 32-bits of MSR value.
4849 <b>Example usage</b>
4853 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2);
4854 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2, Msr);
4856 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.
4858 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 0x00000DF2
4862 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.
4864 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 (0x00000DF3)
4865 @param EAX Lower 32-bits of MSR value.
4866 @param EDX Upper 32-bits of MSR value.
4868 <b>Example usage</b>
4872 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3);
4873 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3, Msr);
4875 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.
4877 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 0x00000DF3
4881 Package. Uncore C-box 7 perfmon box wide filter.
4883 @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER (0x00000DF4)
4884 @param EAX Lower 32-bits of MSR value.
4885 @param EDX Upper 32-bits of MSR value.
4887 <b>Example usage</b>
4891 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER);
4892 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER, Msr);
4894 @note MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER is defined as MSR_C7_PMON_BOX_FILTER in SDM.
4896 #define MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER 0x00000DF4
4900 Package. Uncore C-box 7 perfmon counter 0.
4902 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR0 (0x00000DF6)
4903 @param EAX Lower 32-bits of MSR value.
4904 @param EDX Upper 32-bits of MSR value.
4906 <b>Example usage</b>
4910 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0);
4911 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0, Msr);
4913 @note MSR_SANDY_BRIDGE_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
4915 #define MSR_SANDY_BRIDGE_C7_PMON_CTR0 0x00000DF6
4919 Package. Uncore C-box 7 perfmon counter 1.
4921 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR1 (0x00000DF7)
4922 @param EAX Lower 32-bits of MSR value.
4923 @param EDX Upper 32-bits of MSR value.
4925 <b>Example usage</b>
4929 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1);
4930 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1, Msr);
4932 @note MSR_SANDY_BRIDGE_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
4934 #define MSR_SANDY_BRIDGE_C7_PMON_CTR1 0x00000DF7
4938 Package. Uncore C-box 7 perfmon counter 2.
4940 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR2 (0x00000DF8)
4941 @param EAX Lower 32-bits of MSR value.
4942 @param EDX Upper 32-bits of MSR value.
4944 <b>Example usage</b>
4948 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2);
4949 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2, Msr);
4951 @note MSR_SANDY_BRIDGE_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
4953 #define MSR_SANDY_BRIDGE_C7_PMON_CTR2 0x00000DF8
4957 Package. Uncore C-box 7 perfmon counter 3.
4959 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR3 (0x00000DF9)
4960 @param EAX Lower 32-bits of MSR value.
4961 @param EDX Upper 32-bits of MSR value.
4963 <b>Example usage</b>
4967 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3);
4968 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3, Msr);
4970 @note MSR_SANDY_BRIDGE_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
4972 #define MSR_SANDY_BRIDGE_C7_PMON_CTR3 0x00000DF9