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1 /** @file
2 MSR Definitions for Intel processors based on the Silvermont microarchitecture.
3
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
7 provided for that MSR.
8
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
14
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
20 May 2018, Volume 4: Model-Specific-Registers (MSR)
21
22 **/
23
24 #ifndef __SILVERMONT_MSR_H__
25 #define __SILVERMONT_MSR_H__
26
27 #include <Register/ArchitecturalMsr.h>
28
29 /**
30 Is Intel processors based on the Silvermont microarchitecture?
31
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
34
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
37 **/
38 #define IS_SILVERMONT_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
40 ( \
41 DisplayModel == 0x37 || \
42 DisplayModel == 0x4A || \
43 DisplayModel == 0x4D || \
44 DisplayModel == 0x5A || \
45 DisplayModel == 0x5D \
46 ) \
47 )
48
49 /**
50 Module. Model Specific Platform ID (R).
51
52 @param ECX MSR_SILVERMONT_PLATFORM_ID (0x00000017)
53 @param EAX Lower 32-bits of MSR value.
54 Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.
55 @param EDX Upper 32-bits of MSR value.
56 Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.
57
58 <b>Example usage</b>
59 @code
60 MSR_SILVERMONT_PLATFORM_ID_REGISTER Msr;
61
62 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_ID);
63 @endcode
64 @note MSR_SILVERMONT_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
65 **/
66 #define MSR_SILVERMONT_PLATFORM_ID 0x00000017
67
68 /**
69 MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_ID
70 **/
71 typedef union {
72 ///
73 /// Individual bit fields
74 ///
75 struct {
76 UINT32 Reserved1:8;
77 ///
78 /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.
79 ///
80 UINT32 MaximumQualifiedRatio:5;
81 UINT32 Reserved2:19;
82 UINT32 Reserved3:18;
83 ///
84 /// [Bits 52:50] See Table 2-2.
85 ///
86 UINT32 PlatformId:3;
87 UINT32 Reserved4:11;
88 } Bits;
89 ///
90 /// All bit fields as a 64-bit value
91 ///
92 UINT64 Uint64;
93 } MSR_SILVERMONT_PLATFORM_ID_REGISTER;
94
95
96 /**
97 Module. Processor Hard Power-On Configuration (R/W) Writes ignored.
98
99 @param ECX MSR_SILVERMONT_EBL_CR_POWERON (0x0000002A)
100 @param EAX Lower 32-bits of MSR value.
101 Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.
102 @param EDX Upper 32-bits of MSR value.
103 Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.
104
105 <b>Example usage</b>
106 @code
107 MSR_SILVERMONT_EBL_CR_POWERON_REGISTER Msr;
108
109 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_EBL_CR_POWERON);
110 AsmWriteMsr64 (MSR_SILVERMONT_EBL_CR_POWERON, Msr.Uint64);
111 @endcode
112 @note MSR_SILVERMONT_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
113 **/
114 #define MSR_SILVERMONT_EBL_CR_POWERON 0x0000002A
115
116 /**
117 MSR information returned for MSR index #MSR_SILVERMONT_EBL_CR_POWERON
118 **/
119 typedef union {
120 ///
121 /// Individual bit fields
122 ///
123 struct {
124 UINT32 Reserved1:32;
125 UINT32 Reserved2:32;
126 } Bits;
127 ///
128 /// All bit fields as a 32-bit value
129 ///
130 UINT32 Uint32;
131 ///
132 /// All bit fields as a 64-bit value
133 ///
134 UINT64 Uint64;
135 } MSR_SILVERMONT_EBL_CR_POWERON_REGISTER;
136
137
138 /**
139 Core. SMI Counter (R/O).
140
141 @param ECX MSR_SILVERMONT_SMI_COUNT (0x00000034)
142 @param EAX Lower 32-bits of MSR value.
143 Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.
144 @param EDX Upper 32-bits of MSR value.
145 Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.
146
147 <b>Example usage</b>
148 @code
149 MSR_SILVERMONT_SMI_COUNT_REGISTER Msr;
150
151 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_SMI_COUNT);
152 @endcode
153 @note MSR_SILVERMONT_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
154 **/
155 #define MSR_SILVERMONT_SMI_COUNT 0x00000034
156
157 /**
158 MSR information returned for MSR index #MSR_SILVERMONT_SMI_COUNT
159 **/
160 typedef union {
161 ///
162 /// Individual bit fields
163 ///
164 struct {
165 ///
166 /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last
167 /// RESET.
168 ///
169 UINT32 SMICount:32;
170 UINT32 Reserved:32;
171 } Bits;
172 ///
173 /// All bit fields as a 32-bit value
174 ///
175 UINT32 Uint32;
176 ///
177 /// All bit fields as a 64-bit value
178 ///
179 UINT64 Uint64;
180 } MSR_SILVERMONT_SMI_COUNT_REGISTER;
181
182
183 /**
184 Core. Control Features in Intel 64 Processor (R/W). See Table 2-2.
185
186 @param ECX MSR_IA32_SILVERMONT_FEATURE_CONTROL (0x0000003A)
187 @param EAX Lower 32-bits of MSR value.
188 Described by the type
189 MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER.
190 @param EDX Upper 32-bits of MSR value.
191 Described by the type
192 MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER.
193
194 <b>Example usage</b>
195 @code
196 MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER Msr;
197
198 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL);
199 AsmWriteMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL, Msr.Uint64);
200 @endcode
201 @note MSR_SILVERMONT_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
202 **/
203 #define MSR_SILVERMONT_IA32_FEATURE_CONTROL 0x0000003A
204
205 /**
206 MSR information returned for MSR index #MSR_SILVERMONT_IA32_FEATURE_CONTROL
207 **/
208 typedef union {
209 ///
210 /// Individual bit fields
211 ///
212 struct {
213 ///
214 /// [Bit 0] Lock (R/WL).
215 ///
216 UINT32 Lock:1;
217 UINT32 Reserved1:1;
218 ///
219 /// [Bit 2] Enable VMX outside SMX operation (R/WL).
220 ///
221 UINT32 EnableVmxOutsideSmx:1;
222 UINT32 Reserved2:29;
223 UINT32 Reserved3:32;
224 } Bits;
225 ///
226 /// All bit fields as a 32-bit value
227 ///
228 UINT32 Uint32;
229 ///
230 /// All bit fields as a 64-bit value
231 ///
232 UINT64 Uint64;
233 } MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER;
234
235
236 /**
237 Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch
238 record registers on the last branch record stack. The From_IP part of the
239 stack contains pointers to the source instruction. See also: - Last Branch
240 Record Stack TOS at 1C9H - Section 17.5 and record format in Section
241 17.4.8.1.
242
243 @param ECX MSR_SILVERMONT_LASTBRANCH_n_FROM_IP
244 @param EAX Lower 32-bits of MSR value.
245 @param EDX Upper 32-bits of MSR value.
246
247 <b>Example usage</b>
248 @code
249 UINT64 Msr;
250
251 Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);
252 AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);
253 @endcode
254 @note MSR_SILVERMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
255 MSR_SILVERMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
256 MSR_SILVERMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
257 MSR_SILVERMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
258 MSR_SILVERMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
259 MSR_SILVERMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
260 MSR_SILVERMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
261 MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
262 @{
263 **/
264 #define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP 0x00000040
265 #define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP 0x00000041
266 #define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP 0x00000042
267 #define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP 0x00000043
268 #define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP 0x00000044
269 #define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP 0x00000045
270 #define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP 0x00000046
271 #define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP 0x00000047
272 /// @}
273
274
275 /**
276 Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch
277 record registers on the last branch record stack. The To_IP part of the
278 stack contains pointers to the destination instruction.
279
280 @param ECX MSR_SILVERMONT_LASTBRANCH_n_TO_IP
281 @param EAX Lower 32-bits of MSR value.
282 @param EDX Upper 32-bits of MSR value.
283
284 <b>Example usage</b>
285 @code
286 UINT64 Msr;
287
288 Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);
289 AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);
290 @endcode
291 @note MSR_SILVERMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
292 MSR_SILVERMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
293 MSR_SILVERMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
294 MSR_SILVERMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
295 MSR_SILVERMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
296 MSR_SILVERMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
297 MSR_SILVERMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
298 MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
299 @{
300 **/
301 #define MSR_SILVERMONT_LASTBRANCH_0_TO_IP 0x00000060
302 #define MSR_SILVERMONT_LASTBRANCH_1_TO_IP 0x00000061
303 #define MSR_SILVERMONT_LASTBRANCH_2_TO_IP 0x00000062
304 #define MSR_SILVERMONT_LASTBRANCH_3_TO_IP 0x00000063
305 #define MSR_SILVERMONT_LASTBRANCH_4_TO_IP 0x00000064
306 #define MSR_SILVERMONT_LASTBRANCH_5_TO_IP 0x00000065
307 #define MSR_SILVERMONT_LASTBRANCH_6_TO_IP 0x00000066
308 #define MSR_SILVERMONT_LASTBRANCH_7_TO_IP 0x00000067
309 /// @}
310
311
312 /**
313 Module. Scalable Bus Speed(RO) This field indicates the intended scalable
314 bus clock speed for processors based on Silvermont microarchitecture:.
315
316 @param ECX MSR_SILVERMONT_FSB_FREQ (0x000000CD)
317 @param EAX Lower 32-bits of MSR value.
318 Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.
319 @param EDX Upper 32-bits of MSR value.
320 Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.
321
322 <b>Example usage</b>
323 @code
324 MSR_SILVERMONT_FSB_FREQ_REGISTER Msr;
325
326 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FSB_FREQ);
327 @endcode
328 @note MSR_SILVERMONT_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
329 **/
330 #define MSR_SILVERMONT_FSB_FREQ 0x000000CD
331
332 /**
333 MSR information returned for MSR index #MSR_SILVERMONT_FSB_FREQ
334 **/
335 typedef union {
336 ///
337 /// Individual bit fields
338 ///
339 struct {
340 ///
341 /// [Bits 3:0] Scalable Bus Speed
342 ///
343 /// Silvermont Processor Family
344 /// ---------------------------
345 /// 100B: 080.0 MHz
346 /// 000B: 083.3 MHz
347 /// 001B: 100.0 MHz
348 /// 010B: 133.3 MHz
349 /// 011B: 116.7 MHz
350 ///
351 /// Airmont Processor Family
352 /// ---------------------------
353 /// 0000B: 083.3 MHz
354 /// 0001B: 100.0 MHz
355 /// 0010B: 133.3 MHz
356 /// 0011B: 116.7 MHz
357 /// 0100B: 080.0 MHz
358 /// 0101B: 093.3 MHz
359 /// 0110B: 090.0 MHz
360 /// 0111B: 088.9 MHz
361 /// 1000B: 087.5 MHz
362 ///
363 UINT32 ScalableBusSpeed:4;
364 UINT32 Reserved1:28;
365 UINT32 Reserved2:32;
366 } Bits;
367 ///
368 /// All bit fields as a 32-bit value
369 ///
370 UINT32 Uint32;
371 ///
372 /// All bit fields as a 64-bit value
373 ///
374 UINT64 Uint64;
375 } MSR_SILVERMONT_FSB_FREQ_REGISTER;
376
377
378 /**
379 Package. Platform Information: Contains power management and other model
380 specific features enumeration. See http://biosbits.org.
381
382 @param ECX MSR_SILVERMONT_PLATFORM_INFO (0x000000CE)
383 @param EAX Lower 32-bits of MSR value.
384 Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER.
385 @param EDX Upper 32-bits of MSR value.
386 Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER.
387
388 <b>Example usage</b>
389 @code
390 MSR_SILVERMONT_PLATFORM_INFO_REGISTER Msr;
391
392 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_INFO);
393 AsmWriteMsr64 (MSR_SILVERMONT_PLATFORM_INFO, Msr.Uint64);
394 @endcode
395 **/
396 #define MSR_SILVERMONT_PLATFORM_INFO 0x000000CE
397
398 /**
399 MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_INFO
400 **/
401 typedef union {
402 ///
403 /// Individual bit fields
404 ///
405 struct {
406 UINT32 Reserved1:8;
407 ///
408 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) This is the ratio
409 /// of the maximum frequency that does not require turbo. Frequency =
410 /// ratio * Scalable Bus Frequency.
411 ///
412 UINT32 MaximumNon_TurboRatio:8;
413 UINT32 Reserved2:16;
414 UINT32 Reserved3:32;
415 } Bits;
416 ///
417 /// All bit fields as a 32-bit value
418 ///
419 UINT32 Uint32;
420 ///
421 /// All bit fields as a 64-bit value
422 ///
423 UINT64 Uint64;
424 } MSR_SILVERMONT_PLATFORM_INFO_REGISTER;
425
426 /**
427 Module. C-State Configuration Control (R/W) Note: C-state values are
428 processor specific C-state code names, unrelated to MWAIT extension C-state
429 parameters or ACPI CStates. See http://biosbits.org.
430
431 @param ECX MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)
432 @param EAX Lower 32-bits of MSR value.
433 Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
434 @param EDX Upper 32-bits of MSR value.
435 Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
436
437 <b>Example usage</b>
438 @code
439 MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
440
441 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL);
442 AsmWriteMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
443 @endcode
444 @note MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
445 **/
446 #define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL 0x000000E2
447
448 /**
449 MSR information returned for MSR index #MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL
450 **/
451 typedef union {
452 ///
453 /// Individual bit fields
454 ///
455 struct {
456 ///
457 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
458 /// processor-specific C-state code name (consuming the least power). for
459 /// the package. The default is set as factory-configured package C-state
460 /// limit. The following C-state code name encodings are supported: 000b:
461 /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)
462 /// 100b: C4 110b: C6 111b: C7 (Silvermont only).
463 ///
464 UINT32 Limit:3;
465 UINT32 Reserved1:7;
466 ///
467 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
468 /// IO_read instructions sent to IO register specified by
469 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
470 ///
471 UINT32 IO_MWAIT:1;
472 UINT32 Reserved2:4;
473 ///
474 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
475 /// until next reset.
476 ///
477 UINT32 CFGLock:1;
478 UINT32 Reserved3:16;
479 UINT32 Reserved4:32;
480 } Bits;
481 ///
482 /// All bit fields as a 32-bit value
483 ///
484 UINT32 Uint32;
485 ///
486 /// All bit fields as a 64-bit value
487 ///
488 UINT64 Uint64;
489 } MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER;
490
491
492 /**
493 Module. Power Management IO Redirection in C-state (R/W) See
494 http://biosbits.org.
495
496 @param ECX MSR_SILVERMONT_PMG_IO_CAPTURE_BASE (0x000000E4)
497 @param EAX Lower 32-bits of MSR value.
498 Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.
499 @param EDX Upper 32-bits of MSR value.
500 Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.
501
502 <b>Example usage</b>
503 @code
504 MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER Msr;
505
506 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE);
507 AsmWriteMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE, Msr.Uint64);
508 @endcode
509 @note MSR_SILVERMONT_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
510 **/
511 #define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE 0x000000E4
512
513 /**
514 MSR information returned for MSR index #MSR_SILVERMONT_PMG_IO_CAPTURE_BASE
515 **/
516 typedef union {
517 ///
518 /// Individual bit fields
519 ///
520 struct {
521 ///
522 /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address
523 /// visible to software for IO redirection. If IO MWAIT Redirection is
524 /// enabled, reads to this address will be consumed by the power
525 /// management logic and decoded to MWAIT instructions. When IO port
526 /// address redirection is enabled, this is the IO port address reported
527 /// to the OS/software.
528 ///
529 UINT32 Lvl2Base:16;
530 ///
531 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
532 /// maximum C-State code name to be included when IO read to MWAIT
533 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4
534 /// is the max C-State to include 110b - C6 is the max C-State to include
535 /// 111b - C7 is the max C-State to include.
536 ///
537 UINT32 CStateRange:3;
538 UINT32 Reserved1:13;
539 UINT32 Reserved2:32;
540 } Bits;
541 ///
542 /// All bit fields as a 32-bit value
543 ///
544 UINT32 Uint32;
545 ///
546 /// All bit fields as a 64-bit value
547 ///
548 UINT64 Uint64;
549 } MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER;
550
551
552 /**
553 Module.
554
555 @param ECX MSR_SILVERMONT_BBL_CR_CTL3 (0x0000011E)
556 @param EAX Lower 32-bits of MSR value.
557 Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.
558 @param EDX Upper 32-bits of MSR value.
559 Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.
560
561 <b>Example usage</b>
562 @code
563 MSR_SILVERMONT_BBL_CR_CTL3_REGISTER Msr;
564
565 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_BBL_CR_CTL3);
566 AsmWriteMsr64 (MSR_SILVERMONT_BBL_CR_CTL3, Msr.Uint64);
567 @endcode
568 @note MSR_SILVERMONT_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
569 **/
570 #define MSR_SILVERMONT_BBL_CR_CTL3 0x0000011E
571
572 /**
573 MSR information returned for MSR index #MSR_SILVERMONT_BBL_CR_CTL3
574 **/
575 typedef union {
576 ///
577 /// Individual bit fields
578 ///
579 struct {
580 ///
581 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
582 /// Indicates if the L2 is hardware-disabled.
583 ///
584 UINT32 L2HardwareEnabled:1;
585 UINT32 Reserved1:7;
586 ///
587 /// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =
588 /// Disabled (default) Until this bit is set the processor will not
589 /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
590 ///
591 UINT32 L2Enabled:1;
592 UINT32 Reserved2:14;
593 ///
594 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
595 ///
596 UINT32 L2NotPresent:1;
597 UINT32 Reserved3:8;
598 UINT32 Reserved4:32;
599 } Bits;
600 ///
601 /// All bit fields as a 32-bit value
602 ///
603 UINT32 Uint32;
604 ///
605 /// All bit fields as a 64-bit value
606 ///
607 UINT64 Uint64;
608 } MSR_SILVERMONT_BBL_CR_CTL3_REGISTER;
609
610
611 /**
612 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
613 handler to handle unsuccessful read of this MSR.
614
615 @param ECX MSR_SILVERMONT_FEATURE_CONFIG (0x0000013C)
616 @param EAX Lower 32-bits of MSR value.
617 Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.
618 @param EDX Upper 32-bits of MSR value.
619 Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.
620
621 <b>Example usage</b>
622 @code
623 MSR_SILVERMONT_FEATURE_CONFIG_REGISTER Msr;
624
625 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FEATURE_CONFIG);
626 AsmWriteMsr64 (MSR_SILVERMONT_FEATURE_CONFIG, Msr.Uint64);
627 @endcode
628 @note MSR_SILVERMONT_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
629 **/
630 #define MSR_SILVERMONT_FEATURE_CONFIG 0x0000013C
631
632 /**
633 MSR information returned for MSR index #MSR_SILVERMONT_FEATURE_CONFIG
634 **/
635 typedef union {
636 ///
637 /// Individual bit fields
638 ///
639 struct {
640 ///
641 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
642 /// MSR, the configuration of AES instruction set availability is as
643 /// follows: 11b: AES instructions are not available until next RESET.
644 /// otherwise, AES instructions are available. Note, AES instruction set
645 /// is not available if read is unsuccessful. If the configuration is not
646 /// 01b, AES instruction can be mis-configured if a privileged agent
647 /// unintentionally writes 11b.
648 ///
649 UINT32 AESConfiguration:2;
650 UINT32 Reserved1:30;
651 UINT32 Reserved2:32;
652 } Bits;
653 ///
654 /// All bit fields as a 32-bit value
655 ///
656 UINT32 Uint32;
657 ///
658 /// All bit fields as a 64-bit value
659 ///
660 UINT64 Uint64;
661 } MSR_SILVERMONT_FEATURE_CONFIG_REGISTER;
662
663
664 /**
665 Enable Misc. Processor Features (R/W) Allows a variety of processor
666 functions to be enabled and disabled.
667
668 @param ECX MSR_SILVERMONT_IA32_MISC_ENABLE (0x000001A0)
669 @param EAX Lower 32-bits of MSR value.
670 Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.
671 @param EDX Upper 32-bits of MSR value.
672 Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.
673
674 <b>Example usage</b>
675 @code
676 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER Msr;
677
678 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE);
679 AsmWriteMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE, Msr.Uint64);
680 @endcode
681 @note MSR_SILVERMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
682 **/
683 #define MSR_SILVERMONT_IA32_MISC_ENABLE 0x000001A0
684
685 /**
686 MSR information returned for MSR index #MSR_SILVERMONT_IA32_MISC_ENABLE
687 **/
688 typedef union {
689 ///
690 /// Individual bit fields
691 ///
692 struct {
693 ///
694 /// [Bit 0] Core. Fast-Strings Enable See Table 2-2.
695 ///
696 UINT32 FastStrings:1;
697 UINT32 Reserved1:2;
698 ///
699 /// [Bit 3] Module. Automatic Thermal Control Circuit Enable (R/W) See
700 /// Table 2-2. Default value is 0.
701 ///
702 UINT32 AutomaticThermalControlCircuit:1;
703 UINT32 Reserved2:3;
704 ///
705 /// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.
706 ///
707 UINT32 PerformanceMonitoring:1;
708 UINT32 Reserved3:3;
709 ///
710 /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.
711 ///
712 UINT32 BTS:1;
713 ///
714 /// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See
715 /// Table 2-2.
716 ///
717 UINT32 PEBS:1;
718 UINT32 Reserved4:3;
719 ///
720 /// [Bit 16] Module. Enhanced Intel SpeedStep Technology Enable (R/W) See
721 /// Table 2-2.
722 ///
723 UINT32 EIST:1;
724 UINT32 Reserved5:1;
725 ///
726 /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.
727 ///
728 UINT32 MONITOR:1;
729 UINT32 Reserved6:3;
730 ///
731 /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.
732 ///
733 UINT32 LimitCpuidMaxval:1;
734 ///
735 /// [Bit 23] Module. xTPR Message Disable (R/W) See Table 2-2.
736 ///
737 UINT32 xTPR_Message_Disable:1;
738 UINT32 Reserved7:8;
739 UINT32 Reserved8:2;
740 ///
741 /// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.
742 ///
743 UINT32 XD:1;
744 UINT32 Reserved9:3;
745 ///
746 /// [Bit 38] Module. Turbo Mode Disable (R/W) When set to 1 on processors
747 /// that support Intel Turbo Boost Technology, the turbo mode feature is
748 /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
749 /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
750 /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
751 /// the power-on default value is used by BIOS to detect hardware support
752 /// of turbo mode. If power-on default value is 1, turbo mode is available
753 /// in the processor. If power-on default value is 0, turbo mode is not
754 /// available.
755 ///
756 UINT32 TurboModeDisable:1;
757 UINT32 Reserved10:25;
758 } Bits;
759 ///
760 /// All bit fields as a 64-bit value
761 ///
762 UINT64 Uint64;
763 } MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER;
764
765
766 /**
767 Package.
768
769 @param ECX MSR_SILVERMONT_TEMPERATURE_TARGET (0x000001A2)
770 @param EAX Lower 32-bits of MSR value.
771 Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.
772 @param EDX Upper 32-bits of MSR value.
773 Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.
774
775 <b>Example usage</b>
776 @code
777 MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER Msr;
778
779 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET);
780 AsmWriteMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET, Msr.Uint64);
781 @endcode
782 @note MSR_SILVERMONT_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
783 **/
784 #define MSR_SILVERMONT_TEMPERATURE_TARGET 0x000001A2
785
786 /**
787 MSR information returned for MSR index #MSR_SILVERMONT_TEMPERATURE_TARGET
788 **/
789 typedef union {
790 ///
791 /// Individual bit fields
792 ///
793 struct {
794 UINT32 Reserved1:16;
795 ///
796 /// [Bits 23:16] Temperature Target (R) The default thermal throttling or
797 /// PROCHOT# activation temperature in degree C, The effective temperature
798 /// for thermal throttling or PROCHOT# activation is "Temperature Target"
799 /// + "Target Offset".
800 ///
801 UINT32 TemperatureTarget:8;
802 ///
803 /// [Bits 29:24] Target Offset (R/W) Specifies an offset in degrees C to
804 /// adjust the throttling and PROCHOT# activation temperature from the
805 /// default target specified in TEMPERATURE_TARGET (bits 23:16).
806 ///
807 UINT32 TargetOffset:6;
808 UINT32 Reserved2:2;
809 UINT32 Reserved3:32;
810 } Bits;
811 ///
812 /// All bit fields as a 32-bit value
813 ///
814 UINT32 Uint32;
815 ///
816 /// All bit fields as a 64-bit value
817 ///
818 UINT64 Uint64;
819 } MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER;
820
821
822 /**
823 Miscellaneous Feature Control (R/W).
824
825 @param ECX MSR_SILVERMONT_MISC_FEATURE_CONTROL (0x000001A4)
826 @param EAX Lower 32-bits of MSR value.
827 Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER.
828 @param EDX Upper 32-bits of MSR value.
829 Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER.
830
831 <b>Example usage</b>
832 @code
833 MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER Msr;
834
835 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL);
836 AsmWriteMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL, Msr.Uint64);
837 @endcode
838 @note MSR_SILVERMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
839 **/
840 #define MSR_SILVERMONT_MISC_FEATURE_CONTROL 0x000001A4
841
842 /**
843 MSR information returned for MSR index #MSR_SILVERMONT_MISC_FEATURE_CONTROL
844 **/
845 typedef union {
846 ///
847 /// Individual bit fields
848 ///
849 struct {
850 ///
851 /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
852 /// L2 hardware prefetcher, which fetches additional lines of code or data
853 /// into the L2 cache.
854 ///
855 UINT32 L2HardwarePrefetcherDisable:1;
856 UINT32 Reserved1:1;
857 ///
858 /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables
859 /// the L1 data cache prefetcher, which fetches the next cache line into
860 /// L1 data cache.
861 ///
862 UINT32 DCUHardwarePrefetcherDisable:1;
863 UINT32 Reserved2:29;
864 UINT32 Reserved3:32;
865 } Bits;
866 ///
867 /// All bit fields as a 32-bit value
868 ///
869 UINT32 Uint32;
870 ///
871 /// All bit fields as a 64-bit value
872 ///
873 UINT64 Uint64;
874 } MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER;
875
876
877 /**
878 Module. Offcore Response Event Select Register (R/W).
879
880 @param ECX MSR_SILVERMONT_OFFCORE_RSP_0 (0x000001A6)
881 @param EAX Lower 32-bits of MSR value.
882 @param EDX Upper 32-bits of MSR value.
883
884 <b>Example usage</b>
885 @code
886 UINT64 Msr;
887
888 Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0);
889 AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0, Msr);
890 @endcode
891 @note MSR_SILVERMONT_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
892 **/
893 #define MSR_SILVERMONT_OFFCORE_RSP_0 0x000001A6
894
895
896 /**
897 Module. Offcore Response Event Select Register (R/W).
898
899 @param ECX MSR_SILVERMONT_OFFCORE_RSP_1 (0x000001A7)
900 @param EAX Lower 32-bits of MSR value.
901 @param EDX Upper 32-bits of MSR value.
902
903 <b>Example usage</b>
904 @code
905 UINT64 Msr;
906
907 Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1);
908 AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1, Msr);
909 @endcode
910 @note MSR_SILVERMONT_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
911 **/
912 #define MSR_SILVERMONT_OFFCORE_RSP_1 0x000001A7
913
914
915 /**
916 Package. Maximum Ratio Limit of Turbo Mode (RW).
917
918 @param ECX MSR_SILVERMONT_TURBO_RATIO_LIMIT (0x000001AD)
919 @param EAX Lower 32-bits of MSR value.
920 Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.
921 @param EDX Upper 32-bits of MSR value.
922 Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.
923
924 <b>Example usage</b>
925 @code
926 MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER Msr;
927
928 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT);
929 AsmWriteMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT, Msr.Uint64);
930 @endcode
931 @note MSR_SILVERMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
932 **/
933 #define MSR_SILVERMONT_TURBO_RATIO_LIMIT 0x000001AD
934
935 /**
936 MSR information returned for MSR index #MSR_SILVERMONT_TURBO_RATIO_LIMIT
937 **/
938 typedef union {
939 ///
940 /// Individual bit fields
941 ///
942 struct {
943 ///
944 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
945 /// limit of 1 core active.
946 ///
947 UINT32 Maximum1C:8;
948 ///
949 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
950 /// limit of 2 core active.
951 ///
952 UINT32 Maximum2C:8;
953 ///
954 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
955 /// limit of 3 core active.
956 ///
957 UINT32 Maximum3C:8;
958 ///
959 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
960 /// limit of 4 core active.
961 ///
962 UINT32 Maximum4C:8;
963 ///
964 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
965 /// limit of 5 core active.
966 ///
967 UINT32 Maximum5C:8;
968 ///
969 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
970 /// limit of 6 core active.
971 ///
972 UINT32 Maximum6C:8;
973 ///
974 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
975 /// limit of 7 core active.
976 ///
977 UINT32 Maximum7C:8;
978 ///
979 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
980 /// limit of 8 core active.
981 ///
982 UINT32 Maximum8C:8;
983 } Bits;
984 ///
985 /// All bit fields as a 64-bit value
986 ///
987 UINT64 Uint64;
988 } MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER;
989
990
991 /**
992 Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,
993 "Filtering of Last Branch Records.".
994
995 @param ECX MSR_SILVERMONT_LBR_SELECT (0x000001C8)
996 @param EAX Lower 32-bits of MSR value.
997 Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER.
998 @param EDX Upper 32-bits of MSR value.
999 Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER.
1000
1001 <b>Example usage</b>
1002 @code
1003 MSR_SILVERMONT_LBR_SELECT_REGISTER Msr;
1004
1005 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_LBR_SELECT);
1006 AsmWriteMsr64 (MSR_SILVERMONT_LBR_SELECT, Msr.Uint64);
1007 @endcode
1008 @note MSR_SILVERMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
1009 **/
1010 #define MSR_SILVERMONT_LBR_SELECT 0x000001C8
1011
1012 /**
1013 MSR information returned for MSR index #MSR_SILVERMONT_LBR_SELECT
1014 **/
1015 typedef union {
1016 ///
1017 /// Individual bit fields
1018 ///
1019 struct {
1020 ///
1021 /// [Bit 0] CPL_EQ_0.
1022 ///
1023 UINT32 CPL_EQ_0:1;
1024 ///
1025 /// [Bit 1] CPL_NEQ_0.
1026 ///
1027 UINT32 CPL_NEQ_0:1;
1028 ///
1029 /// [Bit 2] JCC.
1030 ///
1031 UINT32 JCC:1;
1032 ///
1033 /// [Bit 3] NEAR_REL_CALL.
1034 ///
1035 UINT32 NEAR_REL_CALL:1;
1036 ///
1037 /// [Bit 4] NEAR_IND_CALL.
1038 ///
1039 UINT32 NEAR_IND_CALL:1;
1040 ///
1041 /// [Bit 5] NEAR_RET.
1042 ///
1043 UINT32 NEAR_RET:1;
1044 ///
1045 /// [Bit 6] NEAR_IND_JMP.
1046 ///
1047 UINT32 NEAR_IND_JMP:1;
1048 ///
1049 /// [Bit 7] NEAR_REL_JMP.
1050 ///
1051 UINT32 NEAR_REL_JMP:1;
1052 ///
1053 /// [Bit 8] FAR_BRANCH.
1054 ///
1055 UINT32 FAR_BRANCH:1;
1056 UINT32 Reserved1:23;
1057 UINT32 Reserved2:32;
1058 } Bits;
1059 ///
1060 /// All bit fields as a 32-bit value
1061 ///
1062 UINT32 Uint32;
1063 ///
1064 /// All bit fields as a 64-bit value
1065 ///
1066 UINT64 Uint64;
1067 } MSR_SILVERMONT_LBR_SELECT_REGISTER;
1068
1069
1070 /**
1071 Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) that
1072 points to the MSR containing the most recent branch record. See
1073 MSR_LASTBRANCH_0_FROM_IP.
1074
1075 @param ECX MSR_SILVERMONT_LASTBRANCH_TOS (0x000001C9)
1076 @param EAX Lower 32-bits of MSR value.
1077 @param EDX Upper 32-bits of MSR value.
1078
1079 <b>Example usage</b>
1080 @code
1081 UINT64 Msr;
1082
1083 Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS);
1084 AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS, Msr);
1085 @endcode
1086 @note MSR_SILVERMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
1087 **/
1088 #define MSR_SILVERMONT_LASTBRANCH_TOS 0x000001C9
1089
1090
1091 /**
1092 Core. Last Exception Record From Linear IP (R) Contains a pointer to the
1093 last branch instruction that the processor executed prior to the last
1094 exception that was generated or the last interrupt that was handled.
1095
1096 @param ECX MSR_SILVERMONT_LER_FROM_LIP (0x000001DD)
1097 @param EAX Lower 32-bits of MSR value.
1098 @param EDX Upper 32-bits of MSR value.
1099
1100 <b>Example usage</b>
1101 @code
1102 UINT64 Msr;
1103
1104 Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_FROM_LIP);
1105 @endcode
1106 @note MSR_SILVERMONT_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
1107 **/
1108 #define MSR_SILVERMONT_LER_FROM_LIP 0x000001DD
1109
1110
1111 /**
1112 Core. Last Exception Record To Linear IP (R) This area contains a pointer
1113 to the target of the last branch instruction that the processor executed
1114 prior to the last exception that was generated or the last interrupt that
1115 was handled.
1116
1117 @param ECX MSR_SILVERMONT_LER_TO_LIP (0x000001DE)
1118 @param EAX Lower 32-bits of MSR value.
1119 @param EDX Upper 32-bits of MSR value.
1120
1121 <b>Example usage</b>
1122 @code
1123 UINT64 Msr;
1124
1125 Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_TO_LIP);
1126 @endcode
1127 @note MSR_SILVERMONT_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
1128 **/
1129 #define MSR_SILVERMONT_LER_TO_LIP 0x000001DE
1130
1131
1132 /**
1133 Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
1134 (PEBS).".
1135
1136 @param ECX MSR_SILVERMONT_PEBS_ENABLE (0x000003F1)
1137 @param EAX Lower 32-bits of MSR value.
1138 Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.
1139 @param EDX Upper 32-bits of MSR value.
1140 Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.
1141
1142 <b>Example usage</b>
1143 @code
1144 MSR_SILVERMONT_PEBS_ENABLE_REGISTER Msr;
1145
1146 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PEBS_ENABLE);
1147 AsmWriteMsr64 (MSR_SILVERMONT_PEBS_ENABLE, Msr.Uint64);
1148 @endcode
1149 @note MSR_SILVERMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1150 **/
1151 #define MSR_SILVERMONT_PEBS_ENABLE 0x000003F1
1152
1153 /**
1154 MSR information returned for MSR index #MSR_SILVERMONT_PEBS_ENABLE
1155 **/
1156 typedef union {
1157 ///
1158 /// Individual bit fields
1159 ///
1160 struct {
1161 ///
1162 /// [Bit 0] Enable PEBS for precise event on IA32_PMC0. (R/W).
1163 ///
1164 UINT32 PEBS:1;
1165 UINT32 Reserved1:31;
1166 UINT32 Reserved2:32;
1167 } Bits;
1168 ///
1169 /// All bit fields as a 32-bit value
1170 ///
1171 UINT32 Uint32;
1172 ///
1173 /// All bit fields as a 64-bit value
1174 ///
1175 UINT64 Uint64;
1176 } MSR_SILVERMONT_PEBS_ENABLE_REGISTER;
1177
1178
1179 /**
1180 Package. Note: C-state values are processor specific C-state code names,
1181 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
1182 Residency Counter. (R/O) Value since last reset that this package is in
1183 processor-specific C6 states. Counts at the TSC Frequency.
1184
1185 @param ECX MSR_SILVERMONT_PKG_C6_RESIDENCY (0x000003FA)
1186 @param EAX Lower 32-bits of MSR value.
1187 @param EDX Upper 32-bits of MSR value.
1188
1189 <b>Example usage</b>
1190 @code
1191 UINT64 Msr;
1192
1193 Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY);
1194 AsmWriteMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY, Msr);
1195 @endcode
1196 @note MSR_SILVERMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
1197 **/
1198 #define MSR_SILVERMONT_PKG_C6_RESIDENCY 0x000003FA
1199
1200
1201 /**
1202 Core. Note: C-state values are processor specific C-state code names,
1203 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6
1204 Residency Counter. (R/O) Value since last reset that this core is in
1205 processor-specific C6 states. Counts at the TSC Frequency.
1206
1207 @param ECX MSR_SILVERMONT_CORE_C6_RESIDENCY (0x000003FD)
1208 @param EAX Lower 32-bits of MSR value.
1209 @param EDX Upper 32-bits of MSR value.
1210
1211 <b>Example usage</b>
1212 @code
1213 UINT64 Msr;
1214
1215 Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY);
1216 AsmWriteMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY, Msr);
1217 @endcode
1218 @note MSR_SILVERMONT_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
1219 **/
1220 #define MSR_SILVERMONT_CORE_C6_RESIDENCY 0x000003FD
1221
1222
1223 /**
1224 Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.
1225
1226 @param ECX MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
1227 @param EAX Lower 32-bits of MSR value.
1228 @param EDX Upper 32-bits of MSR value.
1229
1230 <b>Example usage</b>
1231 @code
1232 UINT64 Msr;
1233
1234 Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM);
1235 @endcode
1236 @note MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
1237 **/
1238 #define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM 0x0000048C
1239
1240
1241 /**
1242 Core. Capability Reporting Register of VM-Function Controls (R/O) See Table
1243 2-2.
1244
1245 @param ECX MSR_SILVERMONT_IA32_VMX_FMFUNC (0x00000491)
1246 @param EAX Lower 32-bits of MSR value.
1247 @param EDX Upper 32-bits of MSR value.
1248
1249 <b>Example usage</b>
1250 @code
1251 UINT64 Msr;
1252
1253 Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_FMFUNC);
1254 @endcode
1255 @note MSR_SILVERMONT_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.
1256 **/
1257 #define MSR_SILVERMONT_IA32_VMX_FMFUNC 0x00000491
1258
1259
1260 /**
1261 Core. Note: C-state values are processor specific C-state code names,
1262 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C1
1263 Residency Counter. (R/O) Value since last reset that this core is in
1264 processor-specific C1 states. Counts at the TSC frequency.
1265
1266 @param ECX MSR_SILVERMONT_CORE_C1_RESIDENCY (0x00000660)
1267 @param EAX Lower 32-bits of MSR value.
1268 @param EDX Upper 32-bits of MSR value.
1269
1270 <b>Example usage</b>
1271 @code
1272 UINT64 Msr;
1273
1274 Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY);
1275 AsmWriteMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY, Msr);
1276 @endcode
1277 @note MSR_SILVERMONT_CORE_C1_RESIDENCY is defined as MSR_CORE_C1_RESIDENCY in SDM.
1278 **/
1279 #define MSR_SILVERMONT_CORE_C1_RESIDENCY 0x00000660
1280
1281
1282 /**
1283 Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,
1284 "RAPL Interfaces.".
1285
1286 @param ECX MSR_SILVERMONT_RAPL_POWER_UNIT (0x00000606)
1287 @param EAX Lower 32-bits of MSR value.
1288 Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.
1289 @param EDX Upper 32-bits of MSR value.
1290 Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.
1291
1292 <b>Example usage</b>
1293 @code
1294 MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER Msr;
1295
1296 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_RAPL_POWER_UNIT);
1297 @endcode
1298 @note MSR_SILVERMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
1299 **/
1300 #define MSR_SILVERMONT_RAPL_POWER_UNIT 0x00000606
1301
1302 /**
1303 MSR information returned for MSR index #MSR_SILVERMONT_RAPL_POWER_UNIT
1304 **/
1305 typedef union {
1306 ///
1307 /// Individual bit fields
1308 ///
1309 struct {
1310 ///
1311 /// [Bits 3:0] Power Units. Power related information (in milliWatts) is
1312 /// based on the multiplier, 2^PU; where PU is an unsigned integer
1313 /// represented by bits 3:0. Default value is 0101b, indicating power unit
1314 /// is in 32 milliWatts increment.
1315 ///
1316 UINT32 PowerUnits:4;
1317 UINT32 Reserved1:4;
1318 ///
1319 /// [Bits 12:8] Energy Status Units. Energy related information (in
1320 /// microJoules) is based on the multiplier, 2^ESU; where ESU is an
1321 /// unsigned integer represented by bits 12:8. Default value is 00101b,
1322 /// indicating energy unit is in 32 microJoules increment.
1323 ///
1324 UINT32 EnergyStatusUnits:5;
1325 UINT32 Reserved2:3;
1326 ///
1327 /// [Bits 19:16] Time Unit. The value is 0000b, indicating time unit is in
1328 /// one second.
1329 ///
1330 UINT32 TimeUnits:4;
1331 UINT32 Reserved3:12;
1332 UINT32 Reserved4:32;
1333 } Bits;
1334 ///
1335 /// All bit fields as a 32-bit value
1336 ///
1337 UINT32 Uint32;
1338 ///
1339 /// All bit fields as a 64-bit value
1340 ///
1341 UINT64 Uint64;
1342 } MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER;
1343
1344
1345 /**
1346 Package. PKG RAPL Power Limit Control (R/W).
1347
1348 @param ECX MSR_SILVERMONT_PKG_POWER_LIMIT (0x00000610)
1349 @param EAX Lower 32-bits of MSR value.
1350 Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.
1351 @param EDX Upper 32-bits of MSR value.
1352 Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.
1353
1354 <b>Example usage</b>
1355 @code
1356 MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER Msr;
1357
1358 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT);
1359 AsmWriteMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT, Msr.Uint64);
1360 @endcode
1361 @note MSR_SILVERMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
1362 **/
1363 #define MSR_SILVERMONT_PKG_POWER_LIMIT 0x00000610
1364
1365 /**
1366 MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_LIMIT
1367 **/
1368 typedef union {
1369 ///
1370 /// Individual bit fields
1371 ///
1372 struct {
1373 ///
1374 /// [Bits 14:0] Package Power Limit #1 (R/W) See Section 14.9.3, "Package
1375 /// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 2-8.
1376 ///
1377 UINT32 Limit:15;
1378 ///
1379 /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.3, "Package
1380 /// RAPL Domain.".
1381 ///
1382 UINT32 Enable:1;
1383 ///
1384 /// [Bit 16] Package Clamping Limitation #1. (R/W) See Section 14.9.3,
1385 /// "Package RAPL Domain.".
1386 ///
1387 UINT32 ClampingLimit:1;
1388 ///
1389 /// [Bits 23:17] Time Window for Power Limit #1. (R/W) in unit of second.
1390 /// If 0 is specified in bits [23:17], defaults to 1 second window.
1391 ///
1392 UINT32 Time:7;
1393 UINT32 Reserved1:8;
1394 UINT32 Reserved2:32;
1395 } Bits;
1396 ///
1397 /// All bit fields as a 32-bit value
1398 ///
1399 UINT32 Uint32;
1400 ///
1401 /// All bit fields as a 64-bit value
1402 ///
1403 UINT64 Uint64;
1404 } MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER;
1405
1406
1407 /**
1408 Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain."
1409 and MSR_RAPL_POWER_UNIT in Table 2-8.
1410
1411 @param ECX MSR_SILVERMONT_PKG_ENERGY_STATUS (0x00000611)
1412 @param EAX Lower 32-bits of MSR value.
1413 @param EDX Upper 32-bits of MSR value.
1414
1415 <b>Example usage</b>
1416 @code
1417 UINT64 Msr;
1418
1419 Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_ENERGY_STATUS);
1420 @endcode
1421 @note MSR_SILVERMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
1422 **/
1423 #define MSR_SILVERMONT_PKG_ENERGY_STATUS 0x00000611
1424
1425
1426 /**
1427 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains."
1428 and MSR_RAPL_POWER_UNIT in Table 2-8.
1429
1430 @param ECX MSR_SILVERMONT_PP0_ENERGY_STATUS (0x00000639)
1431 @param EAX Lower 32-bits of MSR value.
1432 @param EDX Upper 32-bits of MSR value.
1433
1434 <b>Example usage</b>
1435 @code
1436 UINT64 Msr;
1437
1438 Msr = AsmReadMsr64 (MSR_SILVERMONT_PP0_ENERGY_STATUS);
1439 @endcode
1440 @note MSR_SILVERMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
1441 **/
1442 #define MSR_SILVERMONT_PP0_ENERGY_STATUS 0x00000639
1443
1444
1445 /**
1446 Package. Core C6 demotion policy config MSR. Controls per-core C6 demotion
1447 policy. Writing a value of 0 disables core level HW demotion policy.
1448
1449 @param ECX MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG (0x00000668)
1450 @param EAX Lower 32-bits of MSR value.
1451 @param EDX Upper 32-bits of MSR value.
1452
1453 <b>Example usage</b>
1454 @code
1455 UINT64 Msr;
1456
1457 Msr = AsmReadMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG);
1458 AsmWriteMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG, Msr);
1459 @endcode
1460 @note MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG is defined as MSR_CC6_DEMOTION_POLICY_CONFIG in SDM.
1461 **/
1462 #define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG 0x00000668
1463
1464
1465 /**
1466 Package. Module C6 demotion policy config MSR. Controls module (i.e. two
1467 cores sharing the second-level cache) C6 demotion policy. Writing a value of
1468 0 disables module level HW demotion policy.
1469
1470 @param ECX MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG (0x00000669)
1471 @param EAX Lower 32-bits of MSR value.
1472 @param EDX Upper 32-bits of MSR value.
1473
1474 <b>Example usage</b>
1475 @code
1476 UINT64 Msr;
1477
1478 Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG);
1479 AsmWriteMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG, Msr);
1480 @endcode
1481 @note MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG is defined as MSR_MC6_DEMOTION_POLICY_CONFIG in SDM.
1482 **/
1483 #define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG 0x00000669
1484
1485
1486 /**
1487 Module. Module C6 Residency Counter (R/0) Note: C-state values are processor
1488 specific C-state code names, unrelated to MWAIT extension C-state parameters
1489 or ACPI CStates. Time that this module is in module-specific C6 states since
1490 last reset. Counts at 1 Mhz frequency.
1491
1492 @param ECX MSR_SILVERMONT_MC6_RESIDENCY_COUNTER (0x00000664)
1493 @param EAX Lower 32-bits of MSR value.
1494 @param EDX Upper 32-bits of MSR value.
1495
1496 <b>Example usage</b>
1497 @code
1498 UINT64 Msr;
1499
1500 Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_RESIDENCY_COUNTER);
1501 @endcode
1502 @note MSR_SILVERMONT_MC6_RESIDENCY_COUNTER is defined as MSR_MC6_RESIDENCY_COUNTER in SDM.
1503 **/
1504 #define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER 0x00000664
1505
1506
1507 /**
1508 Package. PKG RAPL Parameter (R/0).
1509
1510 @param ECX MSR_SILVERMONT_PKG_POWER_INFO (0x0000066E)
1511 @param EAX Lower 32-bits of MSR value.
1512 Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.
1513 @param EDX Upper 32-bits of MSR value.
1514 Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.
1515
1516 <b>Example usage</b>
1517 @code
1518 MSR_SILVERMONT_PKG_POWER_INFO_REGISTER Msr;
1519
1520 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_INFO);
1521 @endcode
1522 @note MSR_SILVERMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
1523 **/
1524 #define MSR_SILVERMONT_PKG_POWER_INFO 0x0000066E
1525
1526 /**
1527 MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_INFO
1528 **/
1529 typedef union {
1530 ///
1531 /// Individual bit fields
1532 ///
1533 struct {
1534 ///
1535 /// [Bits 14:0] Thermal Spec Power. (R/0) The unsigned integer value is
1536 /// the equivalent of thermal specification power of the package domain.
1537 /// The unit of this field is specified by the "Power Units" field of
1538 /// MSR_RAPL_POWER_UNIT.
1539 ///
1540 UINT32 ThermalSpecPower:15;
1541 UINT32 Reserved1:17;
1542 UINT32 Reserved2:32;
1543 } Bits;
1544 ///
1545 /// All bit fields as a 32-bit value
1546 ///
1547 UINT32 Uint32;
1548 ///
1549 /// All bit fields as a 64-bit value
1550 ///
1551 UINT64 Uint64;
1552 } MSR_SILVERMONT_PKG_POWER_INFO_REGISTER;
1553
1554
1555 /**
1556 Package. PP0 RAPL Power Limit Control (R/W).
1557
1558 @param ECX MSR_SILVERMONT_PP0_POWER_LIMIT (0x00000638)
1559 @param EAX Lower 32-bits of MSR value.
1560 Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.
1561 @param EDX Upper 32-bits of MSR value.
1562 Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.
1563
1564 <b>Example usage</b>
1565 @code
1566 MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER Msr;
1567
1568 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT);
1569 AsmWriteMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT, Msr.Uint64);
1570 @endcode
1571 @note MSR_SILVERMONT_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
1572 **/
1573 #define MSR_SILVERMONT_PP0_POWER_LIMIT 0x00000638
1574
1575 /**
1576 MSR information returned for MSR index #MSR_SILVERMONT_PP0_POWER_LIMIT
1577 **/
1578 typedef union {
1579 ///
1580 /// Individual bit fields
1581 ///
1582 struct {
1583 ///
1584 /// [Bits 14:0] PP0 Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1
1585 /// RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-8.
1586 ///
1587 UINT32 Limit:15;
1588 ///
1589 /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1
1590 /// RAPL Domains.".
1591 ///
1592 UINT32 Enable:1;
1593 UINT32 Reserved1:1;
1594 ///
1595 /// [Bits 23:17] Time Window for Power Limit #1. (R/W) Specifies the time
1596 /// duration over which the average power must remain below
1597 /// PP0_POWER_LIMIT #1(14:0). Supported Encodings: 0x0: 1 second time
1598 /// duration. 0x1: 5 second time duration (Default). 0x2: 10 second time
1599 /// duration. 0x3: 15 second time duration. 0x4: 20 second time duration.
1600 /// 0x5: 25 second time duration. 0x6: 30 second time duration. 0x7: 35
1601 /// second time duration. 0x8: 40 second time duration. 0x9: 45 second
1602 /// time duration. 0xA: 50 second time duration. 0xB-0x7F - reserved.
1603 ///
1604 UINT32 Time:7;
1605 UINT32 Reserved2:8;
1606 UINT32 Reserved3:32;
1607 } Bits;
1608 ///
1609 /// All bit fields as a 32-bit value
1610 ///
1611 UINT32 Uint32;
1612 ///
1613 /// All bit fields as a 64-bit value
1614 ///
1615 UINT64 Uint64;
1616 } MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER;
1617
1618 #endif
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