UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h

   1 /** @file
   2   MSR Definitions for Intel processors based on the Silvermont microarchitecture.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
  10   This program and the accompanying materials
  11   are licensed and made available under the terms and conditions of the BSD License
  12   which accompanies this distribution.  The full text of the license may be found at
  13   http://opensource.org/licenses/bsd-license.php
  14
  15   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17
  18   @par Specification Reference:
  19   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
  20   September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.4.
  21
  22 **/
  23
  24 #ifndef __SILVERMONT_MSR_H__
  25 #define __SILVERMONT_MSR_H__
  26
  27 #include <Register/ArchitecturalMsr.h>
  28
  29 /**
  30   Module. Model Specific Platform ID (R).
  31
  32   @param  ECX  MSR_SILVERMONT_PLATFORM_ID (0x00000017)
  33   @param  EAX  Lower 32-bits of MSR value.
  34                Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.
  35   @param  EDX  Upper 32-bits of MSR value.
  36                Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.
  37
  38   <b>Example usage</b>
  39   @code
  40   MSR_SILVERMONT_PLATFORM_ID_REGISTER  Msr;
  41
  42   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_ID);
  43   @endcode
  44   @note MSR_SILVERMONT_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
  45 **/
  46 #define MSR_SILVERMONT_PLATFORM_ID               0x00000017
  47
  48 /**
  49   MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_ID
  50 **/
  51 typedef union {
  52   ///
  53   /// Individual bit fields
  54   ///
  55   struct {
  56     UINT32  Reserved1:8;
  57     ///
  58     /// [Bits 12:8] Maximum Qualified Ratio (R)  The maximum allowed bus ratio.
  59     ///
  60     UINT32  MaximumQualifiedRatio:5;
  61     UINT32  Reserved2:19;
  62     UINT32  Reserved3:18;
  63     ///
  64     /// [Bits 52:50] See Table 35-2.
  65     ///
  66     UINT32  PlatformId:3;
  67     UINT32  Reserved4:11;
  68   } Bits;
  69   ///
  70   /// All bit fields as a 64-bit value
  71   ///
  72   UINT64  Uint64;
  73 } MSR_SILVERMONT_PLATFORM_ID_REGISTER;
  74
  75
  76 /**
  77   Module. Processor Hard Power-On Configuration (R/W) Writes ignored.
  78
  79   @param  ECX  MSR_SILVERMONT_EBL_CR_POWERON (0x0000002A)
  80   @param  EAX  Lower 32-bits of MSR value.
  81                Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.
  82   @param  EDX  Upper 32-bits of MSR value.
  83                Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.
  84
  85   <b>Example usage</b>
  86   @code
  87   MSR_SILVERMONT_EBL_CR_POWERON_REGISTER  Msr;
  88
  89   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_EBL_CR_POWERON);
  90   AsmWriteMsr64 (MSR_SILVERMONT_EBL_CR_POWERON, Msr.Uint64);
  91   @endcode
  92   @note MSR_SILVERMONT_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
  93 **/
  94 #define MSR_SILVERMONT_EBL_CR_POWERON            0x0000002A
  95
  96 /**
  97   MSR information returned for MSR index #MSR_SILVERMONT_EBL_CR_POWERON
  98 **/
  99 typedef union {
 100   ///
 101   /// Individual bit fields
 102   ///
 103   struct {
 104     UINT32  Reserved1:32;
 105     UINT32  Reserved2:32;
 106   } Bits;
 107   ///
 108   /// All bit fields as a 32-bit value
 109   ///
 110   UINT32  Uint32;
 111   ///
 112   /// All bit fields as a 64-bit value
 113   ///
 114   UINT64  Uint64;
 115 } MSR_SILVERMONT_EBL_CR_POWERON_REGISTER;
 116
 117
 118 /**
 119   Core. SMI Counter (R/O).
 120
 121   @param  ECX  MSR_SILVERMONT_SMI_COUNT (0x00000034)
 122   @param  EAX  Lower 32-bits of MSR value.
 123                Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.
 124   @param  EDX  Upper 32-bits of MSR value.
 125                Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.
 126
 127   <b>Example usage</b>
 128   @code
 129   MSR_SILVERMONT_SMI_COUNT_REGISTER  Msr;
 130
 131   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_SMI_COUNT);
 132   @endcode
 133   @note MSR_SILVERMONT_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
 134 **/
 135 #define MSR_SILVERMONT_SMI_COUNT                 0x00000034
 136
 137 /**
 138   MSR information returned for MSR index #MSR_SILVERMONT_SMI_COUNT
 139 **/
 140 typedef union {
 141   ///
 142   /// Individual bit fields
 143   ///
 144   struct {
 145     ///
 146     /// [Bits 31:0] SMI Count (R/O)  Running count of SMI events since last
 147     /// RESET.
 148     ///
 149     UINT32  SMICount:32;
 150     UINT32  Reserved:32;
 151   } Bits;
 152   ///
 153   /// All bit fields as a 32-bit value
 154   ///
 155   UINT32  Uint32;
 156   ///
 157   /// All bit fields as a 64-bit value
 158   ///
 159   UINT64  Uint64;
 160 } MSR_SILVERMONT_SMI_COUNT_REGISTER;
 161
 162
 163 /**
 164   Core. Control Features in Intel 64 Processor (R/W). See Table 35-2.
 165
 166   @param  ECX  MSR_IA32_SILVERMONT_FEATURE_CONTROL (0x0000003A)
 167   @param  EAX  Lower 32-bits of MSR value.
 168                Described by the type
 169                MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER.
 170   @param  EDX  Upper 32-bits of MSR value.
 171                Described by the type
 172                MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER.
 173
 174   <b>Example usage</b>
 175   @code
 176   MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER  Msr;
 177
 178   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL);
 179   AsmWriteMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL, Msr.Uint64);
 180   @endcode
 181   @note MSR_SILVERMONT_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
 182 **/
 183 #define MSR_SILVERMONT_IA32_FEATURE_CONTROL      0x0000003A
 184
 185 /**
 186   MSR information returned for MSR index #MSR_SILVERMONT_IA32_FEATURE_CONTROL
 187 **/
 188 typedef union {
 189   ///
 190   /// Individual bit fields
 191   ///
 192   struct {
 193     ///
 194     /// [Bit 0] Lock (R/WL).
 195     ///
 196     UINT32  Lock:1;
 197     UINT32  Reserved1:1;
 198     ///
 199     /// [Bit 2] Enable VMX outside SMX operation (R/WL).
 200     ///
 201     UINT32  EnableVmxOutsideSmx:1;
 202     UINT32  Reserved2:29;
 203     UINT32  Reserved3:32;
 204   } Bits;
 205   ///
 206   /// All bit fields as a 32-bit value
 207   ///
 208   UINT32  Uint32;
 209   ///
 210   /// All bit fields as a 64-bit value
 211   ///
 212   UINT64  Uint64;
 213 } MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER;
 214
 215
 216 /**
 217   Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch
 218   record registers on the last branch record stack. The From_IP part of the
 219   stack contains pointers to the source instruction. See also: -  Last Branch
 220   Record Stack TOS at 1C9H -  Section 17.5 and record format in Section
 221   17.4.8.1.
 222
 223   @param  ECX  MSR_SILVERMONT_LASTBRANCH_n_FROM_IP
 224   @param  EAX  Lower 32-bits of MSR value.
 225   @param  EDX  Upper 32-bits of MSR value.
 226
 227   <b>Example usage</b>
 228   @code
 229   UINT64  Msr;
 230
 231   Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);
 232   AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);
 233   @endcode
 234   @note MSR_SILVERMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
 235         MSR_SILVERMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
 236         MSR_SILVERMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
 237         MSR_SILVERMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
 238         MSR_SILVERMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
 239         MSR_SILVERMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
 240         MSR_SILVERMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
 241         MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
 242   @{
 243 **/
 244 #define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP      0x00000040
 245 #define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP      0x00000041
 246 #define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP      0x00000042
 247 #define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP      0x00000043
 248 #define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP      0x00000044
 249 #define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP      0x00000045
 250 #define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP      0x00000046
 251 #define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP      0x00000047
 252 /// @}
 253
 254
 255 /**
 256   Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch
 257   record registers on the last branch record stack. The To_IP part of the
 258   stack contains pointers to the destination instruction.
 259
 260   @param  ECX  MSR_SILVERMONT_LASTBRANCH_n_TO_IP
 261   @param  EAX  Lower 32-bits of MSR value.
 262   @param  EDX  Upper 32-bits of MSR value.
 263
 264   <b>Example usage</b>
 265   @code
 266   UINT64  Msr;
 267
 268   Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);
 269   AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);
 270   @endcode
 271   @note MSR_SILVERMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
 272         MSR_SILVERMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
 273         MSR_SILVERMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
 274         MSR_SILVERMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
 275         MSR_SILVERMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
 276         MSR_SILVERMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
 277         MSR_SILVERMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
 278         MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
 279   @{
 280 **/
 281 #define MSR_SILVERMONT_LASTBRANCH_0_TO_IP        0x00000060
 282 #define MSR_SILVERMONT_LASTBRANCH_1_TO_IP        0x00000061
 283 #define MSR_SILVERMONT_LASTBRANCH_2_TO_IP        0x00000062
 284 #define MSR_SILVERMONT_LASTBRANCH_3_TO_IP        0x00000063
 285 #define MSR_SILVERMONT_LASTBRANCH_4_TO_IP        0x00000064
 286 #define MSR_SILVERMONT_LASTBRANCH_5_TO_IP        0x00000065
 287 #define MSR_SILVERMONT_LASTBRANCH_6_TO_IP        0x00000066
 288 #define MSR_SILVERMONT_LASTBRANCH_7_TO_IP        0x00000067
 289 /// @}
 290
 291
 292 /**
 293   Module. Scalable Bus Speed(RO) This field indicates the intended scalable
 294   bus clock speed for processors based on Silvermont microarchitecture:.
 295
 296   @param  ECX  MSR_SILVERMONT_FSB_FREQ (0x000000CD)
 297   @param  EAX  Lower 32-bits of MSR value.
 298                Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.
 299   @param  EDX  Upper 32-bits of MSR value.
 300                Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.
 301
 302   <b>Example usage</b>
 303   @code
 304   MSR_SILVERMONT_FSB_FREQ_REGISTER  Msr;
 305
 306   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FSB_FREQ);
 307   @endcode
 308   @note MSR_SILVERMONT_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
 309 **/
 310 #define MSR_SILVERMONT_FSB_FREQ                  0x000000CD
 311
 312 /**
 313   MSR information returned for MSR index #MSR_SILVERMONT_FSB_FREQ
 314 **/
 315 typedef union {
 316   ///
 317   /// Individual bit fields
 318   ///
 319   struct {
 320     ///
 321     /// [Bits 3:0] Scalable Bus Speed
 322     ///
 323     /// Silvermont Processor Family
 324     /// ---------------------------
 325     ///   100B: 080.0 MHz
 326     ///   000B: 083.3 MHz
 327     ///   001B: 100.0 MHz
 328     ///   010B: 133.3 MHz
 329     ///   011B: 116.7 MHz
 330     ///
 331     /// Airmont Processor Family
 332     /// ---------------------------
 333     ///   0000B: 083.3 MHz
 334     ///   0001B: 100.0 MHz
 335     ///   0010B: 133.3 MHz
 336     ///   0011B: 116.7 MHz
 337     ///   0100B: 080.0 MHz
 338     ///   0101B: 093.3 MHz
 339     ///   0110B: 090.0 MHz
 340     ///   0111B: 088.9 MHz
 341     ///   1000B: 087.5 MHz
 342     ///
 343     UINT32  ScalableBusSpeed:4;
 344     UINT32  Reserved1:28;
 345     UINT32  Reserved2:32;
 346   } Bits;
 347   ///
 348   /// All bit fields as a 32-bit value
 349   ///
 350   UINT32  Uint32;
 351   ///
 352   /// All bit fields as a 64-bit value
 353   ///
 354   UINT64  Uint64;
 355 } MSR_SILVERMONT_FSB_FREQ_REGISTER;
 356
 357
 358 /**
 359   Module. C-State Configuration Control (R/W)  Note: C-state values are
 360   processor specific C-state code names, unrelated to MWAIT extension C-state
 361   parameters or ACPI CStates. See http://biosbits.org.
 362
 363   @param  ECX  MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)
 364   @param  EAX  Lower 32-bits of MSR value.
 365                Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
 366   @param  EDX  Upper 32-bits of MSR value.
 367                Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
 368
 369   <b>Example usage</b>
 370   @code
 371   MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
 372
 373   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL);
 374   AsmWriteMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
 375   @endcode
 376   @note MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
 377 **/
 378 #define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL    0x000000E2
 379
 380 /**
 381   MSR information returned for MSR index #MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL
 382 **/
 383 typedef union {
 384   ///
 385   /// Individual bit fields
 386   ///
 387   struct {
 388     ///
 389     /// [Bits 2:0] Package C-State Limit (R/W)  Specifies the lowest
 390     /// processor-specific C-state code name (consuming the least power). for
 391     /// the package. The default is set as factory-configured package C-state
 392     /// limit. The following C-state code name encodings are supported: 000b:
 393     /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)
 394     /// 100b: C4 110b: C6 111b: C7 (Silvermont only).
 395     ///
 396     UINT32  Limit:3;
 397     UINT32  Reserved1:7;
 398     ///
 399     /// [Bit 10] I/O MWAIT Redirection Enable (R/W)  When set, will map
 400     /// IO_read instructions sent to IO register specified by
 401     /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
 402     ///
 403     UINT32  IO_MWAIT:1;
 404     UINT32  Reserved2:4;
 405     ///
 406     /// [Bit 15] CFG Lock (R/WO)  When set, lock bits 15:0 of this register
 407     /// until next reset.
 408     ///
 409     UINT32  CFGLock:1;
 410     UINT32  Reserved3:16;
 411     UINT32  Reserved4:32;
 412   } Bits;
 413   ///
 414   /// All bit fields as a 32-bit value
 415   ///
 416   UINT32  Uint32;
 417   ///
 418   /// All bit fields as a 64-bit value
 419   ///
 420   UINT64  Uint64;
 421 } MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER;
 422
 423
 424 /**
 425   Module. Power Management IO Redirection in C-state (R/W) See
 426   http://biosbits.org.
 427
 428   @param  ECX  MSR_SILVERMONT_PMG_IO_CAPTURE_BASE (0x000000E4)
 429   @param  EAX  Lower 32-bits of MSR value.
 430                Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.
 431   @param  EDX  Upper 32-bits of MSR value.
 432                Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.
 433
 434   <b>Example usage</b>
 435   @code
 436   MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER  Msr;
 437
 438   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE);
 439   AsmWriteMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE, Msr.Uint64);
 440   @endcode
 441   @note MSR_SILVERMONT_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
 442 **/
 443 #define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE       0x000000E4
 444
 445 /**
 446   MSR information returned for MSR index #MSR_SILVERMONT_PMG_IO_CAPTURE_BASE
 447 **/
 448 typedef union {
 449   ///
 450   /// Individual bit fields
 451   ///
 452   struct {
 453     ///
 454     /// [Bits 15:0] LVL_2 Base Address (R/W)  Specifies the base address
 455     /// visible to software for IO redirection. If IO MWAIT Redirection is
 456     /// enabled, reads to this address will be consumed by the power
 457     /// management logic and decoded to MWAIT instructions. When IO port
 458     /// address redirection is enabled, this is the IO port address reported
 459     /// to the OS/software.
 460     ///
 461     UINT32  Lvl2Base:16;
 462     ///
 463     /// [Bits 18:16] C-state Range (R/W)  Specifies the encoding value of the
 464     /// maximum C-State code name to be included when IO read to MWAIT
 465     /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4
 466     /// is the max C-State to include 110b - C6 is the max C-State to include
 467     /// 111b - C7 is the max C-State to include.
 468     ///
 469     UINT32  CStateRange:3;
 470     UINT32  Reserved1:13;
 471     UINT32  Reserved2:32;
 472   } Bits;
 473   ///
 474   /// All bit fields as a 32-bit value
 475   ///
 476   UINT32  Uint32;
 477   ///
 478   /// All bit fields as a 64-bit value
 479   ///
 480   UINT64  Uint64;
 481 } MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER;
 482
 483
 484 /**
 485   Module.
 486
 487   @param  ECX  MSR_SILVERMONT_BBL_CR_CTL3 (0x0000011E)
 488   @param  EAX  Lower 32-bits of MSR value.
 489                Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.
 490   @param  EDX  Upper 32-bits of MSR value.
 491                Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.
 492
 493   <b>Example usage</b>
 494   @code
 495   MSR_SILVERMONT_BBL_CR_CTL3_REGISTER  Msr;
 496
 497   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_BBL_CR_CTL3);
 498   AsmWriteMsr64 (MSR_SILVERMONT_BBL_CR_CTL3, Msr.Uint64);
 499   @endcode
 500   @note MSR_SILVERMONT_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
 501 **/
 502 #define MSR_SILVERMONT_BBL_CR_CTL3               0x0000011E
 503
 504 /**
 505   MSR information returned for MSR index #MSR_SILVERMONT_BBL_CR_CTL3
 506 **/
 507 typedef union {
 508   ///
 509   /// Individual bit fields
 510   ///
 511   struct {
 512     ///
 513     /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
 514     /// Indicates if the L2 is hardware-disabled.
 515     ///
 516     UINT32  L2HardwareEnabled:1;
 517     UINT32  Reserved1:7;
 518     ///
 519     /// [Bit 8] L2 Enabled. (R/W)  1 = L2 cache has been initialized 0 =
 520     /// Disabled (default) Until this bit is set the processor will not
 521     /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
 522     ///
 523     UINT32  L2Enabled:1;
 524     UINT32  Reserved2:14;
 525     ///
 526     /// [Bit 23] L2 Not Present (RO)  1. = L2 Present 2. = L2 Not Present.
 527     ///
 528     UINT32  L2NotPresent:1;
 529     UINT32  Reserved3:8;
 530     UINT32  Reserved4:32;
 531   } Bits;
 532   ///
 533   /// All bit fields as a 32-bit value
 534   ///
 535   UINT32  Uint32;
 536   ///
 537   /// All bit fields as a 64-bit value
 538   ///
 539   UINT64  Uint64;
 540 } MSR_SILVERMONT_BBL_CR_CTL3_REGISTER;
 541
 542
 543 /**
 544   Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
 545   handler to handle unsuccessful read of this MSR.
 546
 547   @param  ECX  MSR_SILVERMONT_FEATURE_CONFIG (0x0000013C)
 548   @param  EAX  Lower 32-bits of MSR value.
 549                Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.
 550   @param  EDX  Upper 32-bits of MSR value.
 551                Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.
 552
 553   <b>Example usage</b>
 554   @code
 555   MSR_SILVERMONT_FEATURE_CONFIG_REGISTER  Msr;
 556
 557   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FEATURE_CONFIG);
 558   AsmWriteMsr64 (MSR_SILVERMONT_FEATURE_CONFIG, Msr.Uint64);
 559   @endcode
 560   @note MSR_SILVERMONT_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
 561 **/
 562 #define MSR_SILVERMONT_FEATURE_CONFIG            0x0000013C
 563
 564 /**
 565   MSR information returned for MSR index #MSR_SILVERMONT_FEATURE_CONFIG
 566 **/
 567 typedef union {
 568   ///
 569   /// Individual bit fields
 570   ///
 571   struct {
 572     ///
 573     /// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this
 574     /// MSR, the configuration of AES instruction set availability is as
 575     /// follows: 11b: AES instructions are not available until next RESET.
 576     /// otherwise, AES instructions are available. Note, AES instruction set
 577     /// is not available if read is unsuccessful. If the configuration is not
 578     /// 01b, AES instruction can be mis-configured if a privileged agent
 579     /// unintentionally writes 11b.
 580     ///
 581     UINT32  AESConfiguration:2;
 582     UINT32  Reserved1:30;
 583     UINT32  Reserved2:32;
 584   } Bits;
 585   ///
 586   /// All bit fields as a 32-bit value
 587   ///
 588   UINT32  Uint32;
 589   ///
 590   /// All bit fields as a 64-bit value
 591   ///
 592   UINT64  Uint64;
 593 } MSR_SILVERMONT_FEATURE_CONFIG_REGISTER;
 594
 595
 596 /**
 597   Enable Misc. Processor Features (R/W)  Allows a variety of processor
 598   functions to be enabled and disabled.
 599
 600   @param  ECX  MSR_SILVERMONT_IA32_MISC_ENABLE (0x000001A0)
 601   @param  EAX  Lower 32-bits of MSR value.
 602                Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.
 603   @param  EDX  Upper 32-bits of MSR value.
 604                Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.
 605
 606   <b>Example usage</b>
 607   @code
 608   MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER  Msr;
 609
 610   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE);
 611   AsmWriteMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE, Msr.Uint64);
 612   @endcode
 613   @note MSR_SILVERMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
 614 **/
 615 #define MSR_SILVERMONT_IA32_MISC_ENABLE          0x000001A0
 616
 617 /**
 618   MSR information returned for MSR index #MSR_SILVERMONT_IA32_MISC_ENABLE
 619 **/
 620 typedef union {
 621   ///
 622   /// Individual bit fields
 623   ///
 624   struct {
 625     ///
 626     /// [Bit 0] Core. Fast-Strings Enable See Table 35-2.
 627     ///
 628     UINT32  FastStrings:1;
 629     UINT32  Reserved1:2;
 630     ///
 631     /// [Bit 3] Module. Automatic Thermal Control Circuit Enable (R/W) See
 632     /// Table 35-2. Default value is 0.
 633     ///
 634     UINT32  AutomaticThermalControlCircuit:1;
 635     UINT32  Reserved2:3;
 636     ///
 637     /// [Bit 7] Core. Performance Monitoring Available (R) See Table 35-2.
 638     ///
 639     UINT32  PerformanceMonitoring:1;
 640     UINT32  Reserved3:3;
 641     ///
 642     /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 35-2.
 643     ///
 644     UINT32  BTS:1;
 645     ///
 646     /// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See
 647     /// Table 35-2.
 648     ///
 649     UINT32  PEBS:1;
 650     UINT32  Reserved4:3;
 651     ///
 652     /// [Bit 16] Module. Enhanced Intel SpeedStep Technology Enable (R/W) See
 653     /// Table 35-2.
 654     ///
 655     UINT32  EIST:1;
 656     UINT32  Reserved5:1;
 657     ///
 658     /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 35-2.
 659     ///
 660     UINT32  MONITOR:1;
 661     UINT32  Reserved6:3;
 662     ///
 663     /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 35-2.
 664     ///
 665     UINT32  LimitCpuidMaxval:1;
 666     ///
 667     /// [Bit 23] Module. xTPR Message Disable (R/W) See Table 35-2.
 668     ///
 669     UINT32  xTPR_Message_Disable:1;
 670     UINT32  Reserved7:8;
 671     UINT32  Reserved8:2;
 672     ///
 673     /// [Bit 34] Core. XD Bit Disable (R/W) See Table 35-2.
 674     ///
 675     UINT32  XD:1;
 676     UINT32  Reserved9:3;
 677     ///
 678     /// [Bit 38] Module. Turbo Mode Disable (R/W) When set to 1 on processors
 679     /// that support Intel Turbo Boost Technology, the turbo mode feature is
 680     /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
 681     /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
 682     /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
 683     /// the power-on default value is used by BIOS to detect hardware support
 684     /// of turbo mode. If power-on default value is 1, turbo mode is available
 685     /// in the processor. If power-on default value is 0, turbo mode is not
 686     /// available.
 687     ///
 688     UINT32  TurboModeDisable:1;
 689     UINT32  Reserved10:25;
 690   } Bits;
 691   ///
 692   /// All bit fields as a 64-bit value
 693   ///
 694   UINT64  Uint64;
 695 } MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER;
 696
 697
 698 /**
 699   Package.
 700
 701   @param  ECX  MSR_SILVERMONT_TEMPERATURE_TARGET (0x000001A2)
 702   @param  EAX  Lower 32-bits of MSR value.
 703                Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.
 704   @param  EDX  Upper 32-bits of MSR value.
 705                Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.
 706
 707   <b>Example usage</b>
 708   @code
 709   MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER  Msr;
 710
 711   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET);
 712   AsmWriteMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET, Msr.Uint64);
 713   @endcode
 714   @note MSR_SILVERMONT_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
 715 **/
 716 #define MSR_SILVERMONT_TEMPERATURE_TARGET        0x000001A2
 717
 718 /**
 719   MSR information returned for MSR index #MSR_SILVERMONT_TEMPERATURE_TARGET
 720 **/
 721 typedef union {
 722   ///
 723   /// Individual bit fields
 724   ///
 725   struct {
 726     UINT32  Reserved1:16;
 727     ///
 728     /// [Bits 23:16] Temperature Target (R)  The default thermal throttling or
 729     /// PROCHOT# activation temperature in degree C, The effective temperature
 730     /// for thermal throttling or PROCHOT# activation is "Temperature Target"
 731     /// + "Target Offset".
 732     ///
 733     UINT32  TemperatureTarget:8;
 734     ///
 735     /// [Bits 29:24] Target Offset (R/W)  Specifies an offset in degrees C to
 736     /// adjust the throttling and PROCHOT# activation temperature from the
 737     /// default target specified in TEMPERATURE_TARGET (bits 23:16).
 738     ///
 739     UINT32  TargetOffset:6;
 740     UINT32  Reserved2:2;
 741     UINT32  Reserved3:32;
 742   } Bits;
 743   ///
 744   /// All bit fields as a 32-bit value
 745   ///
 746   UINT32  Uint32;
 747   ///
 748   /// All bit fields as a 64-bit value
 749   ///
 750   UINT64  Uint64;
 751 } MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER;
 752
 753
 754 /**
 755   Miscellaneous Feature Control (R/W).
 756
 757   @param  ECX  MSR_SILVERMONT_MISC_FEATURE_CONTROL (0x000001A4)
 758   @param  EAX  Lower 32-bits of MSR value.
 759                Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER.
 760   @param  EDX  Upper 32-bits of MSR value.
 761                Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER.
 762
 763   <b>Example usage</b>
 764   @code
 765   MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER  Msr;
 766
 767   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL);
 768   AsmWriteMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL, Msr.Uint64);
 769   @endcode
 770   @note MSR_SILVERMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
 771 **/
 772 #define MSR_SILVERMONT_MISC_FEATURE_CONTROL      0x000001A4
 773
 774 /**
 775   MSR information returned for MSR index #MSR_SILVERMONT_MISC_FEATURE_CONTROL
 776 **/
 777 typedef union {
 778   ///
 779   /// Individual bit fields
 780   ///
 781   struct {
 782     ///
 783     /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W)  If 1, disables the
 784     /// L2 hardware prefetcher, which fetches additional lines of code or data
 785     /// into the L2 cache.
 786     ///
 787     UINT32  L2HardwarePrefetcherDisable:1;
 788     UINT32  Reserved1:1;
 789     ///
 790     /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W)  If 1, disables
 791     /// the L1 data cache prefetcher, which fetches the next cache line into
 792     /// L1 data cache.
 793     ///
 794     UINT32  DCUHardwarePrefetcherDisable:1;
 795     UINT32  Reserved2:29;
 796     UINT32  Reserved3:32;
 797   } Bits;
 798   ///
 799   /// All bit fields as a 32-bit value
 800   ///
 801   UINT32  Uint32;
 802   ///
 803   /// All bit fields as a 64-bit value
 804   ///
 805   UINT64  Uint64;
 806 } MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER;
 807
 808
 809 /**
 810   Module. Offcore Response Event Select Register (R/W).
 811
 812   @param  ECX  MSR_SILVERMONT_OFFCORE_RSP_0 (0x000001A6)
 813   @param  EAX  Lower 32-bits of MSR value.
 814   @param  EDX  Upper 32-bits of MSR value.
 815
 816   <b>Example usage</b>
 817   @code
 818   UINT64  Msr;
 819
 820   Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0);
 821   AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0, Msr);
 822   @endcode
 823   @note MSR_SILVERMONT_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
 824 **/
 825 #define MSR_SILVERMONT_OFFCORE_RSP_0             0x000001A6
 826
 827
 828 /**
 829   Module. Offcore Response Event Select Register (R/W).
 830
 831   @param  ECX  MSR_SILVERMONT_OFFCORE_RSP_1 (0x000001A7)
 832   @param  EAX  Lower 32-bits of MSR value.
 833   @param  EDX  Upper 32-bits of MSR value.
 834
 835   <b>Example usage</b>
 836   @code
 837   UINT64  Msr;
 838
 839   Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1);
 840   AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1, Msr);
 841   @endcode
 842   @note MSR_SILVERMONT_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
 843 **/
 844 #define MSR_SILVERMONT_OFFCORE_RSP_1             0x000001A7
 845
 846
 847 /**
 848   Package. Maximum Ratio Limit of Turbo Mode (RW).
 849
 850   @param  ECX  MSR_SILVERMONT_TURBO_RATIO_LIMIT (0x000001AD)
 851   @param  EAX  Lower 32-bits of MSR value.
 852                Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.
 853   @param  EDX  Upper 32-bits of MSR value.
 854                Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.
 855
 856   <b>Example usage</b>
 857   @code
 858   MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER  Msr;
 859
 860   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT);
 861   AsmWriteMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT, Msr.Uint64);
 862   @endcode
 863   @note MSR_SILVERMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 864 **/
 865 #define MSR_SILVERMONT_TURBO_RATIO_LIMIT         0x000001AD
 866
 867 /**
 868   MSR information returned for MSR index #MSR_SILVERMONT_TURBO_RATIO_LIMIT
 869 **/
 870 typedef union {
 871   ///
 872   /// Individual bit fields
 873   ///
 874   struct {
 875     ///
 876     /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
 877     /// limit of 1 core active.
 878     ///
 879     UINT32  Maximum1C:8;
 880     ///
 881     /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
 882     /// limit of 2 core active.
 883     ///
 884     UINT32  Maximum2C:8;
 885     ///
 886     /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
 887     /// limit of 3 core active.
 888     ///
 889     UINT32  Maximum3C:8;
 890     ///
 891     /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
 892     /// limit of 4 core active.
 893     ///
 894     UINT32  Maximum4C:8;
 895     ///
 896     /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
 897     /// limit of 5 core active.
 898     ///
 899     UINT32  Maximum5C:8;
 900     ///
 901     /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
 902     /// limit of 6 core active.
 903     ///
 904     UINT32  Maximum6C:8;
 905     ///
 906     /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
 907     /// limit of 7 core active.
 908     ///
 909     UINT32  Maximum7C:8;
 910     ///
 911     /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
 912     /// limit of 8 core active.
 913     ///
 914     UINT32  Maximum8C:8;
 915   } Bits;
 916   ///
 917   /// All bit fields as a 64-bit value
 918   ///
 919   UINT64  Uint64;
 920 } MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER;
 921
 922
 923 /**
 924   Core. Last Branch Record Filtering Select Register (R/W)  See Section
 925   17.7.2, "Filtering of Last Branch Records.".
 926
 927   @param  ECX  MSR_SILVERMONT_LBR_SELECT (0x000001C8)
 928   @param  EAX  Lower 32-bits of MSR value.
 929                Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER.
 930   @param  EDX  Upper 32-bits of MSR value.
 931                Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER.
 932
 933   <b>Example usage</b>
 934   @code
 935   MSR_SILVERMONT_LBR_SELECT_REGISTER  Msr;
 936
 937   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_LBR_SELECT);
 938   AsmWriteMsr64 (MSR_SILVERMONT_LBR_SELECT, Msr.Uint64);
 939   @endcode
 940   @note MSR_SILVERMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
 941 **/
 942 #define MSR_SILVERMONT_LBR_SELECT                0x000001C8
 943
 944 /**
 945   MSR information returned for MSR index #MSR_SILVERMONT_LBR_SELECT
 946 **/
 947 typedef union {
 948   ///
 949   /// Individual bit fields
 950   ///
 951   struct {
 952     ///
 953     /// [Bit 0] CPL_EQ_0.
 954     ///
 955     UINT32  CPL_EQ_0:1;
 956     ///
 957     /// [Bit 1] CPL_NEQ_0.
 958     ///
 959     UINT32  CPL_NEQ_0:1;
 960     ///
 961     /// [Bit 2] JCC.
 962     ///
 963     UINT32  JCC:1;
 964     ///
 965     /// [Bit 3] NEAR_REL_CALL.
 966     ///
 967     UINT32  NEAR_REL_CALL:1;
 968     ///
 969     /// [Bit 4] NEAR_IND_CALL.
 970     ///
 971     UINT32  NEAR_IND_CALL:1;
 972     ///
 973     /// [Bit 5] NEAR_RET.
 974     ///
 975     UINT32  NEAR_RET:1;
 976     ///
 977     /// [Bit 6] NEAR_IND_JMP.
 978     ///
 979     UINT32  NEAR_IND_JMP:1;
 980     ///
 981     /// [Bit 7] NEAR_REL_JMP.
 982     ///
 983     UINT32  NEAR_REL_JMP:1;
 984     ///
 985     /// [Bit 8] FAR_BRANCH.
 986     ///
 987     UINT32  FAR_BRANCH:1;
 988     UINT32  Reserved1:23;
 989     UINT32  Reserved2:32;
 990   } Bits;
 991   ///
 992   /// All bit fields as a 32-bit value
 993   ///
 994   UINT32  Uint32;
 995   ///
 996   /// All bit fields as a 64-bit value
 997   ///
 998   UINT64  Uint64;
 999 } MSR_SILVERMONT_LBR_SELECT_REGISTER;
1000
1001
1002 /**
1003   Core. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-2) that
1004   points to the MSR containing the most recent branch record. See
1005   MSR_LASTBRANCH_0_FROM_IP.
1006
1007   @param  ECX  MSR_SILVERMONT_LASTBRANCH_TOS (0x000001C9)
1008   @param  EAX  Lower 32-bits of MSR value.
1009   @param  EDX  Upper 32-bits of MSR value.
1010
1011   <b>Example usage</b>
1012   @code
1013   UINT64  Msr;
1014
1015   Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS);
1016   AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS, Msr);
1017   @endcode
1018   @note MSR_SILVERMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
1019 **/
1020 #define MSR_SILVERMONT_LASTBRANCH_TOS            0x000001C9
1021
1022
1023 /**
1024   Core. Last Exception Record From Linear IP (R)  Contains a pointer to the
1025   last branch instruction that the processor executed prior to the last
1026   exception that was generated or the last interrupt that was handled.
1027
1028   @param  ECX  MSR_SILVERMONT_LER_FROM_LIP (0x000001DD)
1029   @param  EAX  Lower 32-bits of MSR value.
1030   @param  EDX  Upper 32-bits of MSR value.
1031
1032   <b>Example usage</b>
1033   @code
1034   UINT64  Msr;
1035
1036   Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_FROM_LIP);
1037   @endcode
1038   @note MSR_SILVERMONT_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
1039 **/
1040 #define MSR_SILVERMONT_LER_FROM_LIP              0x000001DD
1041
1042
1043 /**
1044   Core. Last Exception Record To Linear IP (R)  This area contains a pointer
1045   to the target of the last branch instruction that the processor executed
1046   prior to the last exception that was generated or the last interrupt that
1047   was handled.
1048
1049   @param  ECX  MSR_SILVERMONT_LER_TO_LIP (0x000001DE)
1050   @param  EAX  Lower 32-bits of MSR value.
1051   @param  EDX  Upper 32-bits of MSR value.
1052
1053   <b>Example usage</b>
1054   @code
1055   UINT64  Msr;
1056
1057   Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_TO_LIP);
1058   @endcode
1059   @note MSR_SILVERMONT_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
1060 **/
1061 #define MSR_SILVERMONT_LER_TO_LIP                0x000001DE
1062
1063
1064 /**
1065   Core. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling
1066   (PEBS).".
1067
1068   @param  ECX  MSR_SILVERMONT_PEBS_ENABLE (0x000003F1)
1069   @param  EAX  Lower 32-bits of MSR value.
1070                Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.
1071   @param  EDX  Upper 32-bits of MSR value.
1072                Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.
1073
1074   <b>Example usage</b>
1075   @code
1076   MSR_SILVERMONT_PEBS_ENABLE_REGISTER  Msr;
1077
1078   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PEBS_ENABLE);
1079   AsmWriteMsr64 (MSR_SILVERMONT_PEBS_ENABLE, Msr.Uint64);
1080   @endcode
1081   @note MSR_SILVERMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1082 **/
1083 #define MSR_SILVERMONT_PEBS_ENABLE               0x000003F1
1084
1085 /**
1086   MSR information returned for MSR index #MSR_SILVERMONT_PEBS_ENABLE
1087 **/
1088 typedef union {
1089   ///
1090   /// Individual bit fields
1091   ///
1092   struct {
1093     ///
1094     /// [Bit 0] Enable PEBS for precise event on IA32_PMC0. (R/W).
1095     ///
1096     UINT32  PEBS:1;
1097     UINT32  Reserved1:31;
1098     UINT32  Reserved2:32;
1099   } Bits;
1100   ///
1101   /// All bit fields as a 32-bit value
1102   ///
1103   UINT32  Uint32;
1104   ///
1105   /// All bit fields as a 64-bit value
1106   ///
1107   UINT64  Uint64;
1108 } MSR_SILVERMONT_PEBS_ENABLE_REGISTER;
1109
1110
1111 /**
1112   Package. Note: C-state values are processor specific C-state code names,
1113   unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
1114   Residency Counter. (R/O) Value since last reset that this package is in
1115   processor-specific C6 states. Counts at the TSC Frequency.
1116
1117   @param  ECX  MSR_SILVERMONT_PKG_C6_RESIDENCY (0x000003FA)
1118   @param  EAX  Lower 32-bits of MSR value.
1119   @param  EDX  Upper 32-bits of MSR value.
1120
1121   <b>Example usage</b>
1122   @code
1123   UINT64  Msr;
1124
1125   Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY);
1126   AsmWriteMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY, Msr);
1127   @endcode
1128   @note MSR_SILVERMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
1129 **/
1130 #define MSR_SILVERMONT_PKG_C6_RESIDENCY          0x000003FA
1131
1132
1133 /**
1134   Core. Note: C-state values are processor specific C-state code names,
1135   unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6
1136   Residency Counter. (R/O) Value since last reset that this core is in
1137   processor-specific C6 states. Counts at the TSC Frequency.
1138
1139   @param  ECX  MSR_SILVERMONT_CORE_C6_RESIDENCY (0x000003FD)
1140   @param  EAX  Lower 32-bits of MSR value.
1141   @param  EDX  Upper 32-bits of MSR value.
1142
1143   <b>Example usage</b>
1144   @code
1145   UINT64  Msr;
1146
1147   Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY);
1148   AsmWriteMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY, Msr);
1149   @endcode
1150   @note MSR_SILVERMONT_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
1151 **/
1152 #define MSR_SILVERMONT_CORE_C6_RESIDENCY         0x000003FD
1153
1154
1155 /**
1156   Core. Capability Reporting Register of EPT and VPID (R/O)  See Table 35-2.
1157
1158   @param  ECX  MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
1159   @param  EAX  Lower 32-bits of MSR value.
1160   @param  EDX  Upper 32-bits of MSR value.
1161
1162   <b>Example usage</b>
1163   @code
1164   UINT64  Msr;
1165
1166   Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM);
1167   @endcode
1168   @note MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
1169 **/
1170 #define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM    0x0000048C
1171
1172
1173 /**
1174   Core. Capability Reporting Register of VM-function Controls (R/O) See Table
1175   35-2.
1176
1177   @param  ECX  MSR_SILVERMONT_IA32_VMX_FMFUNC (0x00000491)
1178   @param  EAX  Lower 32-bits of MSR value.
1179   @param  EDX  Upper 32-bits of MSR value.
1180
1181   <b>Example usage</b>
1182   @code
1183   UINT64  Msr;
1184
1185   Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_FMFUNC);
1186   @endcode
1187   @note MSR_SILVERMONT_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.
1188 **/
1189 #define MSR_SILVERMONT_IA32_VMX_FMFUNC           0x00000491
1190
1191
1192 /**
1193   Core. Note: C-state values are processor specific C-state code names,
1194   unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C1
1195   Residency Counter. (R/O) Value since last reset that this core is in
1196   processor-specific C1 states. Counts at the TSC frequency.
1197
1198   @param  ECX  MSR_SILVERMONT_CORE_C1_RESIDENCY (0x00000660)
1199   @param  EAX  Lower 32-bits of MSR value.
1200   @param  EDX  Upper 32-bits of MSR value.
1201
1202   <b>Example usage</b>
1203   @code
1204   UINT64  Msr;
1205
1206   Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY);
1207   AsmWriteMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY, Msr);
1208   @endcode
1209   @note MSR_SILVERMONT_CORE_C1_RESIDENCY is defined as MSR_CORE_C1_RESIDENCY in SDM.
1210 **/
1211 #define MSR_SILVERMONT_CORE_C1_RESIDENCY         0x00000660
1212
1213
1214 /**
1215   Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,
1216   "RAPL Interfaces.".
1217
1218   @param  ECX  MSR_SILVERMONT_RAPL_POWER_UNIT (0x00000606)
1219   @param  EAX  Lower 32-bits of MSR value.
1220                Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.
1221   @param  EDX  Upper 32-bits of MSR value.
1222                Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.
1223
1224   <b>Example usage</b>
1225   @code
1226   MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER  Msr;
1227
1228   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_RAPL_POWER_UNIT);
1229   @endcode
1230   @note MSR_SILVERMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
1231 **/
1232 #define MSR_SILVERMONT_RAPL_POWER_UNIT           0x00000606
1233
1234 /**
1235   MSR information returned for MSR index #MSR_SILVERMONT_RAPL_POWER_UNIT
1236 **/
1237 typedef union {
1238   ///
1239   /// Individual bit fields
1240   ///
1241   struct {
1242     ///
1243     /// [Bits 3:0] Power Units. Power related information (in milliWatts) is
1244     /// based on the multiplier, 2^PU; where PU is an unsigned integer
1245     /// represented by bits 3:0. Default value is 0101b, indicating power unit
1246     /// is in 32 milliWatts increment.
1247     ///
1248     UINT32  PowerUnits:4;
1249     UINT32  Reserved1:4;
1250     ///
1251     /// [Bits 12:8] Energy Status Units. Energy related information (in
1252     /// microJoules) is based on the multiplier, 2^ESU; where ESU is an
1253     /// unsigned integer represented by bits 12:8. Default value is 00101b,
1254     /// indicating energy unit is in 32 microJoules increment.
1255     ///
1256     UINT32  EnergyStatusUnits:5;
1257     UINT32  Reserved2:3;
1258     ///
1259     /// [Bits 19:16] Time Unit. The value is 0000b, indicating time unit is in
1260     /// one second.
1261     ///
1262     UINT32  TimeUnits:4;
1263     UINT32  Reserved3:12;
1264     UINT32  Reserved4:32;
1265   } Bits;
1266   ///
1267   /// All bit fields as a 32-bit value
1268   ///
1269   UINT32  Uint32;
1270   ///
1271   /// All bit fields as a 64-bit value
1272   ///
1273   UINT64  Uint64;
1274 } MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER;
1275
1276
1277 /**
1278   Package. PKG RAPL Power Limit Control (R/W).
1279
1280   @param  ECX  MSR_SILVERMONT_PKG_POWER_LIMIT (0x00000610)
1281   @param  EAX  Lower 32-bits of MSR value.
1282                Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.
1283   @param  EDX  Upper 32-bits of MSR value.
1284                Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.
1285
1286   <b>Example usage</b>
1287   @code
1288   MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER  Msr;
1289
1290   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT);
1291   AsmWriteMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT, Msr.Uint64);
1292   @endcode
1293   @note MSR_SILVERMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
1294 **/
1295 #define MSR_SILVERMONT_PKG_POWER_LIMIT           0x00000610
1296
1297 /**
1298   MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_LIMIT
1299 **/
1300 typedef union {
1301   ///
1302   /// Individual bit fields
1303   ///
1304   struct {
1305     ///
1306     /// [Bits 14:0] Package Power Limit #1. (R/W) See Section 14.9.3, "Package
1307     /// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 35-8.
1308     ///
1309     UINT32  Limit:15;
1310     ///
1311     /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.3, "Package
1312     /// RAPL Domain.".
1313     ///
1314     UINT32  Enable:1;
1315     ///
1316     /// [Bit 16] Package Clamping Limitation #1. (R/W) See Section 14.9.3,
1317     /// "Package RAPL Domain.".
1318     ///
1319     UINT32  ClampingLimit:1;
1320     ///
1321     /// [Bits 23:17] Time Window for Power Limit #1. (R/W) in unit of second.
1322     /// If 0 is specified in bits [23:17], defaults to 1 second window.
1323     ///
1324     UINT32  Time:7;
1325     UINT32  Reserved1:8;
1326     UINT32  Reserved2:32;
1327   } Bits;
1328   ///
1329   /// All bit fields as a 32-bit value
1330   ///
1331   UINT32  Uint32;
1332   ///
1333   /// All bit fields as a 64-bit value
1334   ///
1335   UINT64  Uint64;
1336 } MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER;
1337
1338
1339 /**
1340   Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain."
1341   and MSR_RAPL_POWER_UNIT in Table 35-8.
1342
1343   @param  ECX  MSR_SILVERMONT_PKG_ENERGY_STATUS (0x00000611)
1344   @param  EAX  Lower 32-bits of MSR value.
1345   @param  EDX  Upper 32-bits of MSR value.
1346
1347   <b>Example usage</b>
1348   @code
1349   UINT64  Msr;
1350
1351   Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_ENERGY_STATUS);
1352   @endcode
1353   @note MSR_SILVERMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
1354 **/
1355 #define MSR_SILVERMONT_PKG_ENERGY_STATUS         0x00000611
1356
1357
1358 /**
1359   Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
1360   Domains." and MSR_RAPL_POWER_UNIT in Table 35-8.
1361
1362   @param  ECX  MSR_SILVERMONT_PP0_ENERGY_STATUS (0x00000639)
1363   @param  EAX  Lower 32-bits of MSR value.
1364   @param  EDX  Upper 32-bits of MSR value.
1365
1366   <b>Example usage</b>
1367   @code
1368   UINT64  Msr;
1369
1370   Msr = AsmReadMsr64 (MSR_SILVERMONT_PP0_ENERGY_STATUS);
1371   @endcode
1372   @note MSR_SILVERMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
1373 **/
1374 #define MSR_SILVERMONT_PP0_ENERGY_STATUS         0x00000639
1375
1376
1377 /**
1378   Package. Core C6 demotion policy config MSR. Controls per-core C6 demotion
1379   policy. Writing a value of 0 disables core level HW demotion policy.
1380
1381   @param  ECX  MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG (0x00000668)
1382   @param  EAX  Lower 32-bits of MSR value.
1383   @param  EDX  Upper 32-bits of MSR value.
1384
1385   <b>Example usage</b>
1386   @code
1387   UINT64  Msr;
1388
1389   Msr = AsmReadMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG);
1390   AsmWriteMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG, Msr);
1391   @endcode
1392   @note MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG is defined as MSR_CC6_DEMOTION_POLICY_CONFIG in SDM.
1393 **/
1394 #define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG 0x00000668
1395
1396
1397 /**
1398   Package. Module C6 demotion policy config MSR. Controls module (i.e. two
1399   cores sharing the second-level cache) C6 demotion policy. Writing a value of
1400   0 disables module level HW demotion policy.
1401
1402   @param  ECX  MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG (0x00000669)
1403   @param  EAX  Lower 32-bits of MSR value.
1404   @param  EDX  Upper 32-bits of MSR value.
1405
1406   <b>Example usage</b>
1407   @code
1408   UINT64  Msr;
1409
1410   Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG);
1411   AsmWriteMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG, Msr);
1412   @endcode
1413   @note MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG is defined as MSR_MC6_DEMOTION_POLICY_CONFIG in SDM.
1414 **/
1415 #define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG 0x00000669
1416
1417
1418 /**
1419   Module. Module C6 Residency Counter (R/0) Note: C-state values are processor
1420   specific C-state code names, unrelated to MWAIT extension C-state parameters
1421   or ACPI CStates. Time that this module is in module-specific C6 states since
1422   last reset. Counts at 1 Mhz frequency.
1423
1424   @param  ECX  MSR_SILVERMONT_MC6_RESIDENCY_COUNTER (0x00000664)
1425   @param  EAX  Lower 32-bits of MSR value.
1426   @param  EDX  Upper 32-bits of MSR value.
1427
1428   <b>Example usage</b>
1429   @code
1430   UINT64  Msr;
1431
1432   Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_RESIDENCY_COUNTER);
1433   @endcode
1434   @note MSR_SILVERMONT_MC6_RESIDENCY_COUNTER is defined as MSR_MC6_RESIDENCY_COUNTER in SDM.
1435 **/
1436 #define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER     0x00000664
1437
1438
1439 /**
1440   Package. PKG RAPL Parameter (R/0).
1441
1442   @param  ECX  MSR_SILVERMONT_PKG_POWER_INFO (0x0000066E)
1443   @param  EAX  Lower 32-bits of MSR value.
1444                Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.
1445   @param  EDX  Upper 32-bits of MSR value.
1446                Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.
1447
1448   <b>Example usage</b>
1449   @code
1450   MSR_SILVERMONT_PKG_POWER_INFO_REGISTER  Msr;
1451
1452   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_INFO);
1453   @endcode
1454   @note MSR_SILVERMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
1455 **/
1456 #define MSR_SILVERMONT_PKG_POWER_INFO            0x0000066E
1457
1458 /**
1459   MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_INFO
1460 **/
1461 typedef union {
1462   ///
1463   /// Individual bit fields
1464   ///
1465   struct {
1466     ///
1467     /// [Bits 14:0] Thermal Spec Power. (R/0) The unsigned integer value is
1468     /// the equivalent of thermal specification power of the package domain.
1469     /// The unit of this field is specified by the "Power Units" field of
1470     /// MSR_RAPL_POWER_UNIT.
1471     ///
1472     UINT32  ThermalSpecPower:15;
1473     UINT32  Reserved1:17;
1474     UINT32  Reserved2:32;
1475   } Bits;
1476   ///
1477   /// All bit fields as a 32-bit value
1478   ///
1479   UINT32  Uint32;
1480   ///
1481   /// All bit fields as a 64-bit value
1482   ///
1483   UINT64  Uint64;
1484 } MSR_SILVERMONT_PKG_POWER_INFO_REGISTER;
1485
1486
1487 /**
1488   Package. PP0 RAPL Power Limit Control (R/W).
1489
1490   @param  ECX  MSR_SILVERMONT_PP0_POWER_LIMIT (0x00000638)
1491   @param  EAX  Lower 32-bits of MSR value.
1492                Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.
1493   @param  EDX  Upper 32-bits of MSR value.
1494                Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.
1495
1496   <b>Example usage</b>
1497   @code
1498   MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER  Msr;
1499
1500   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT);
1501   AsmWriteMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT, Msr.Uint64);
1502   @endcode
1503   @note MSR_SILVERMONT_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
1504 **/
1505 #define MSR_SILVERMONT_PP0_POWER_LIMIT           0x00000638
1506
1507 /**
1508   MSR information returned for MSR index #MSR_SILVERMONT_PP0_POWER_LIMIT
1509 **/
1510 typedef union {
1511   ///
1512   /// Individual bit fields
1513   ///
1514   struct {
1515     ///
1516     /// [Bits 14:0] PP0 Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1
1517     /// RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-8.
1518     ///
1519     UINT32  Limit:15;
1520     ///
1521     /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1
1522     /// RAPL Domains.".
1523     ///
1524     UINT32  Enable:1;
1525     UINT32  Reserved1:1;
1526     ///
1527     /// [Bits 23:17] Time Window for Power Limit #1. (R/W) Specifies the time
1528     /// duration over which the average power must remain below
1529     /// PP0_POWER_LIMIT #1(14:0). Supported Encodings: 0x0: 1 second time
1530     /// duration. 0x1: 5 second time duration (Default). 0x2: 10 second time
1531     /// duration. 0x3: 15 second time duration. 0x4: 20 second time duration.
1532     /// 0x5: 25 second time duration. 0x6: 30 second time duration. 0x7: 35
1533     /// second time duration. 0x8: 40 second time duration. 0x9: 45 second
1534     /// time duration. 0xA: 50 second time duration. 0xB-0x7F - reserved.
1535     ///
1536     UINT32  Time:7;
1537     UINT32  Reserved2:8;
1538     UINT32  Reserved3:32;
1539   } Bits;
1540   ///
1541   /// All bit fields as a 32-bit value
1542   ///
1543   UINT32  Uint32;
1544   ///
1545   /// All bit fields as a 64-bit value
1546   ///
1547   UINT64  Uint64;
1548 } MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER;
1549
1550 #endif