2 MSR Defintions for Intel processors based on the Skylake/Kabylake/Coffeelake/Cannonlake microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
20 May 2018, Volume 4: Model-Specific-Registers (MSR)
24 #ifndef __SKYLAKE_MSR_H__
25 #define __SKYLAKE_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Is Intel processors based on the Skylake microarchitecture?
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
38 #define IS_SKYLAKE_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
41 DisplayModel == 0x4E || \
42 DisplayModel == 0x5E || \
43 DisplayModel == 0x55 || \
44 DisplayModel == 0x8E || \
45 DisplayModel == 0x9E || \
46 DisplayModel == 0x66 \
51 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
52 RW if MSR_PLATFORM_INFO.[28] = 1.
54 @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT (0x000001AD)
55 @param EAX Lower 32-bits of MSR value.
56 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.
57 @param EDX Upper 32-bits of MSR value.
58 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.
62 MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER Msr;
64 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT);
66 @note MSR_SKYLAKE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
68 #define MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD
71 MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT
75 /// Individual bit fields
79 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
80 /// limit of 1 core active.
84 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
85 /// limit of 2 core active.
89 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
90 /// limit of 3 core active.
94 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
95 /// limit of 4 core active.
101 /// All bit fields as a 32-bit value
105 /// All bit fields as a 64-bit value
108 } MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER
;
112 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4)
113 that points to the MSR containing the most recent branch record.
115 @param ECX MSR_SKYLAKE_LASTBRANCH_TOS (0x000001C9)
116 @param EAX Lower 32-bits of MSR value.
117 @param EDX Upper 32-bits of MSR value.
123 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS);
124 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS, Msr);
126 @note MSR_SKYLAKE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
128 #define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9
132 Core. Power Control Register See http://biosbits.org.
134 @param ECX MSR_SKYLAKE_POWER_CTL (0x000001FC)
135 @param EAX Lower 32-bits of MSR value.
136 Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.
137 @param EDX Upper 32-bits of MSR value.
138 Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.
142 MSR_SKYLAKE_POWER_CTL_REGISTER Msr;
144 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_POWER_CTL);
145 AsmWriteMsr64 (MSR_SKYLAKE_POWER_CTL, Msr.Uint64);
148 #define MSR_SKYLAKE_POWER_CTL 0x000001FC
151 MSR information returned for MSR index #MSR_SKYLAKE_POWER_CTL
155 /// Individual bit fields
160 /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the CPU
161 /// to switch to the Minimum Enhanced Intel SpeedStep Technology operating
162 /// point when all execution cores enter MWAIT (C1).
167 /// [Bit 19] Disable Race to Halt Optimization (R/W) Setting this bit
168 /// disables the Race to Halt optimization and avoids this optimization
169 /// limitation to execute below the most efficient frequency ratio.
170 /// Default value is 0 for processors that support Race to Halt
171 /// optimization. Default value is 1 for processors that do not support
172 /// Race to Halt optimization.
176 /// [Bit 20] Disable Energy Efficiency Optimization (R/W) Setting this bit
177 /// disables the P-States energy efficiency optimization. Default value is
178 /// 0. Disable/enable the energy efficiency optimization in P-State legacy
179 /// mode (when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the
180 /// turbo range or into PERF_MIN_CTL value if it is not zero set. In HWP
181 /// mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect between the OS
182 /// desired or OS maximize to the OS minimize performance setting.
184 UINT32 DisableEnergyEfficiencyOptimization
:1;
189 /// All bit fields as a 32-bit value
193 /// All bit fields as a 64-bit value
196 } MSR_SKYLAKE_POWER_CTL_REGISTER
;
200 Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update
201 CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in
202 the package. Lower 64 bits of an 128-bit external entropy value for key
203 derivation of an enclave.
205 @param ECX MSR_SKYLAKE_SGXOWNEREPOCH0 (0x00000300)
206 @param EAX Lower 32-bits of MSR value.
207 @param EDX Upper 32-bits of MSR value.
214 AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH0, Msr);
216 @note MSR_SKYLAKE_SGXOWNEREPOCH0 is defined as MSR_SGXOWNER0 in SDM.
218 #define MSR_SKYLAKE_SGXOWNEREPOCH0 0x00000300
221 // Define MSR_SKYLAKE_SGXOWNER0 for compatibility due to name change in the SDM.
223 #define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0
225 Package. Upper 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update
226 CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in
227 the package. Upper 64 bits of an 128-bit external entropy value for key
228 derivation of an enclave.
230 @param ECX MSR_SKYLAKE_SGXOWNEREPOCH1 (0x00000301)
231 @param EAX Lower 32-bits of MSR value.
232 @param EDX Upper 32-bits of MSR value.
239 AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH1, Msr);
241 @note MSR_SKYLAKE_SGXOWNEREPOCH1 is defined as MSR_SGXOWNER1 in SDM.
243 #define MSR_SKYLAKE_SGXOWNEREPOCH1 0x00000301
246 // Define MSR_SKYLAKE_SGXOWNER1 for compatibility due to name change in the SDM.
248 #define MSR_SKYLAKE_SGXOWNER1 MSR_SKYLAKE_SGXOWNEREPOCH1
252 See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring
255 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS (0x0000038E)
256 @param EAX Lower 32-bits of MSR value.
257 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.
258 @param EDX Upper 32-bits of MSR value.
259 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.
263 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
265 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS);
266 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);
268 @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
270 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS 0x0000038E
273 MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS
277 /// Individual bit fields
281 /// [Bit 0] Thread. Ovf_PMC0.
285 /// [Bit 1] Thread. Ovf_PMC1.
289 /// [Bit 2] Thread. Ovf_PMC2.
293 /// [Bit 3] Thread. Ovf_PMC3.
297 /// [Bit 4] Thread. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
301 /// [Bit 5] Thread. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
305 /// [Bit 6] Thread. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
309 /// [Bit 7] Thread. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
314 /// [Bit 32] Thread. Ovf_FixedCtr0.
316 UINT32 Ovf_FixedCtr0
:1;
318 /// [Bit 33] Thread. Ovf_FixedCtr1.
320 UINT32 Ovf_FixedCtr1
:1;
322 /// [Bit 34] Thread. Ovf_FixedCtr2.
324 UINT32 Ovf_FixedCtr2
:1;
327 /// [Bit 55] Thread. Trace_ToPA_PMI.
329 UINT32 Trace_ToPA_PMI
:1;
332 /// [Bit 58] Thread. LBR_Frz.
336 /// [Bit 59] Thread. CTR_Frz.
340 /// [Bit 60] Thread. ASCI.
344 /// [Bit 61] Thread. Ovf_Uncore.
348 /// [Bit 62] Thread. Ovf_BufDSSAVE.
350 UINT32 Ovf_BufDSSAVE
:1;
352 /// [Bit 63] Thread. CondChgd.
357 /// All bit fields as a 64-bit value
360 } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER
;
364 See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring
367 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
368 @param EAX Lower 32-bits of MSR value.
369 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
370 @param EDX Upper 32-bits of MSR value.
371 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
375 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;
377 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET);
378 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
380 @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
382 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
385 MSR information returned for MSR index
386 #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET
390 /// Individual bit fields
394 /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.
398 /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.
402 /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.
406 /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.
410 /// [Bit 4] Thread. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
414 /// [Bit 5] Thread. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
418 /// [Bit 6] Thread. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
422 /// [Bit 7] Thread. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
427 /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.
429 UINT32 Ovf_FixedCtr0
:1;
431 /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.
433 UINT32 Ovf_FixedCtr1
:1;
435 /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.
437 UINT32 Ovf_FixedCtr2
:1;
440 /// [Bit 55] Thread. Set 1 to clear Trace_ToPA_PMI.
442 UINT32 Trace_ToPA_PMI
:1;
445 /// [Bit 58] Thread. Set 1 to clear LBR_Frz.
449 /// [Bit 59] Thread. Set 1 to clear CTR_Frz.
453 /// [Bit 60] Thread. Set 1 to clear ASCI.
457 /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.
461 /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.
463 UINT32 Ovf_BufDSSAVE
:1;
465 /// [Bit 63] Thread. Set 1 to clear CondChgd.
470 /// All bit fields as a 64-bit value
473 } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
;
477 See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring
480 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
481 @param EAX Lower 32-bits of MSR value.
482 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
483 @param EDX Upper 32-bits of MSR value.
484 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
488 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;
490 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET);
491 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
493 @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
495 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
498 MSR information returned for MSR index
499 #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET
503 /// Individual bit fields
507 /// [Bit 0] Thread. Set 1 to cause Ovf_PMC0 = 1.
511 /// [Bit 1] Thread. Set 1 to cause Ovf_PMC1 = 1.
515 /// [Bit 2] Thread. Set 1 to cause Ovf_PMC2 = 1.
519 /// [Bit 3] Thread. Set 1 to cause Ovf_PMC3 = 1.
523 /// [Bit 4] Thread. Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4).
527 /// [Bit 5] Thread. Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5).
531 /// [Bit 6] Thread. Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6).
535 /// [Bit 7] Thread. Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7).
540 /// [Bit 32] Thread. Set 1 to cause Ovf_FixedCtr0 = 1.
542 UINT32 Ovf_FixedCtr0
:1;
544 /// [Bit 33] Thread. Set 1 to cause Ovf_FixedCtr1 = 1.
546 UINT32 Ovf_FixedCtr1
:1;
548 /// [Bit 34] Thread. Set 1 to cause Ovf_FixedCtr2 = 1.
550 UINT32 Ovf_FixedCtr2
:1;
553 /// [Bit 55] Thread. Set 1 to cause Trace_ToPA_PMI = 1.
555 UINT32 Trace_ToPA_PMI
:1;
558 /// [Bit 58] Thread. Set 1 to cause LBR_Frz = 1.
562 /// [Bit 59] Thread. Set 1 to cause CTR_Frz = 1.
566 /// [Bit 60] Thread. Set 1 to cause ASCI = 1.
570 /// [Bit 61] Thread. Set 1 to cause Ovf_Uncore.
574 /// [Bit 62] Thread. Set 1 to cause Ovf_BufDSSAVE.
576 UINT32 Ovf_BufDSSAVE
:1;
580 /// All bit fields as a 64-bit value
583 } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
;
587 Thread. FrontEnd Precise Event Condition Select (R/W).
589 @param ECX MSR_SKYLAKE_PEBS_FRONTEND (0x000003F7)
590 @param EAX Lower 32-bits of MSR value.
591 Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.
592 @param EDX Upper 32-bits of MSR value.
593 Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.
597 MSR_SKYLAKE_PEBS_FRONTEND_REGISTER Msr;
599 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PEBS_FRONTEND);
600 AsmWriteMsr64 (MSR_SKYLAKE_PEBS_FRONTEND, Msr.Uint64);
602 @note MSR_SKYLAKE_PEBS_FRONTEND is defined as MSR_PEBS_FRONTEND in SDM.
604 #define MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7
607 MSR information returned for MSR index #MSR_SKYLAKE_PEBS_FRONTEND
611 /// Individual bit fields
615 /// [Bits 2:0] Event Code Select.
617 UINT32 EventCodeSelect
:3;
620 /// [Bit 4] Event Code Select High.
622 UINT32 EventCodeSelectHigh
:1;
625 /// [Bits 19:8] IDQ_Bubble_Length Specifier.
627 UINT32 IDQ_Bubble_Length
:12;
629 /// [Bits 22:20] IDQ_Bubble_Width Specifier.
631 UINT32 IDQ_Bubble_Width
:3;
636 /// All bit fields as a 32-bit value
640 /// All bit fields as a 64-bit value
643 } MSR_SKYLAKE_PEBS_FRONTEND_REGISTER
;
647 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
650 @param ECX MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)
651 @param EAX Lower 32-bits of MSR value.
652 @param EDX Upper 32-bits of MSR value.
658 Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);
660 @note MSR_SKYLAKE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
662 #define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639
666 Platform*. Platform Energy Counter. (R/O). This MSR is valid only if both
667 platform vendor hardware implementation and BIOS enablement support it. This
668 MSR will read 0 if not valid.
670 @param ECX MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER (0x0000064D)
671 @param EAX Lower 32-bits of MSR value.
672 Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.
673 @param EDX Upper 32-bits of MSR value.
674 Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.
678 MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER Msr;
680 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER);
682 @note MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER is defined as MSR_PLATFORM_ENERGY_COUNTER in SDM.
684 #define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D
687 MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER
691 /// Individual bit fields
695 /// [Bits 31:0] Total energy consumed by all devices in the platform that
696 /// receive power from integrated power delivery mechanism, Included
697 /// platform devices are processor cores, SOC, memory, add-on or
698 /// peripheral devices that get powered directly from the platform power
699 /// delivery means. The energy units are specified in the
700 /// MSR_RAPL_POWER_UNIT.Enery_Status_Unit.
702 UINT32 TotalEnergy
:32;
706 /// All bit fields as a 32-bit value
710 /// All bit fields as a 64-bit value
713 } MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER
;
717 Thread. Productive Performance Count. (R/O). Hardware's view of workload
718 scalability. See Section 14.4.5.1.
720 @param ECX MSR_SKYLAKE_PPERF (0x0000064E)
721 @param EAX Lower 32-bits of MSR value.
722 @param EDX Upper 32-bits of MSR value.
728 Msr = AsmReadMsr64 (MSR_SKYLAKE_PPERF);
730 @note MSR_SKYLAKE_PPERF is defined as MSR_PPERF in SDM.
732 #define MSR_SKYLAKE_PPERF 0x0000064E
736 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
737 refers to processor core frequency).
739 @param ECX MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS (0x0000064F)
740 @param EAX Lower 32-bits of MSR value.
741 Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.
742 @param EDX Upper 32-bits of MSR value.
743 Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.
747 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
749 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS);
750 AsmWriteMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
752 @note MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
754 #define MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS 0x0000064F
757 MSR information returned for MSR index #MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS
761 /// Individual bit fields
765 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the
766 /// operating system request due to assertion of external PROCHOT.
768 UINT32 PROCHOT_Status
:1;
770 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
771 /// operating system request due to a thermal event.
773 UINT32 ThermalStatus
:1;
776 /// [Bit 4] Residency State Regulation Status (R0) When set, frequency is
777 /// reduced below the operating system request due to residency state
778 /// regulation limit.
780 UINT32 ResidencyStateRegulationStatus
:1;
782 /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency
783 /// is reduced below the operating system request due to Running Average
784 /// Thermal Limit (RATL).
786 UINT32 RunningAverageThermalLimitStatus
:1;
788 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
789 /// below the operating system request due to a thermal alert from a
790 /// processor Voltage Regulator (VR).
792 UINT32 VRThermAlertStatus
:1;
794 /// [Bit 7] VR Therm Design Current Status (R0) When set, frequency is
795 /// reduced below the operating system request due to VR thermal design
798 UINT32 VRThermDesignCurrentStatus
:1;
800 /// [Bit 8] Other Status (R0) When set, frequency is reduced below the
801 /// operating system request due to electrical or other constraints.
803 UINT32 OtherStatus
:1;
806 /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When
807 /// set, frequency is reduced below the operating system request due to
808 /// package/platform-level power limiting PL1.
812 /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When
813 /// set, frequency is reduced below the operating system request due to
814 /// package/platform-level power limiting PL2/PL3.
818 /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced
819 /// below the operating system request due to multi-core turbo limits.
821 UINT32 MaxTurboLimitStatus
:1;
823 /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency
824 /// is reduced below the operating system request due to Turbo transition
825 /// attenuation. This prevents performance degradation due to frequent
826 /// operating ratio changes.
828 UINT32 TurboTransitionAttenuationStatus
:1;
831 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
832 /// has asserted since the log bit was last cleared. This log bit will
833 /// remain set until cleared by software writing 0.
835 UINT32 PROCHOT_Log
:1;
837 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
838 /// has asserted since the log bit was last cleared. This log bit will
839 /// remain set until cleared by software writing 0.
844 /// [Bit 20] Residency State Regulation Log When set, indicates that the
845 /// Residency State Regulation Status bit has asserted since the log bit
846 /// was last cleared. This log bit will remain set until cleared by
847 /// software writing 0.
849 UINT32 ResidencyStateRegulationLog
:1;
851 /// [Bit 21] Running Average Thermal Limit Log When set, indicates that
852 /// the RATL Status bit has asserted since the log bit was last cleared.
853 /// This log bit will remain set until cleared by software writing 0.
855 UINT32 RunningAverageThermalLimitLog
:1;
857 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
858 /// Alert Status bit has asserted since the log bit was last cleared. This
859 /// log bit will remain set until cleared by software writing 0.
861 UINT32 VRThermAlertLog
:1;
863 /// [Bit 23] VR Thermal Design Current Log When set, indicates that the
864 /// VR TDC Status bit has asserted since the log bit was last cleared.
865 /// This log bit will remain set until cleared by software writing 0.
867 UINT32 VRThermalDesignCurrentLog
:1;
869 /// [Bit 24] Other Log When set, indicates that the Other Status bit has
870 /// asserted since the log bit was last cleared. This log bit will remain
871 /// set until cleared by software writing 0.
876 /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,
877 /// indicates that the Package or Platform Level PL1 Power Limiting Status
878 /// bit has asserted since the log bit was last cleared. This log bit will
879 /// remain set until cleared by software writing 0.
883 /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,
884 /// indicates that the Package or Platform Level PL2/PL3 Power Limiting
885 /// Status bit has asserted since the log bit was last cleared. This log
886 /// bit will remain set until cleared by software writing 0.
890 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
891 /// Limit Status bit has asserted since the log bit was last cleared. This
892 /// log bit will remain set until cleared by software writing 0.
894 UINT32 MaxTurboLimitLog
:1;
896 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
897 /// Turbo Transition Attenuation Status bit has asserted since the log bit
898 /// was last cleared. This log bit will remain set until cleared by
899 /// software writing 0.
901 UINT32 TurboTransitionAttenuationLog
:1;
906 /// All bit fields as a 32-bit value
910 /// All bit fields as a 64-bit value
913 } MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER
;
917 Package. HDC Configuration (R/W)..
919 @param ECX MSR_SKYLAKE_PKG_HDC_CONFIG (0x00000652)
920 @param EAX Lower 32-bits of MSR value.
921 Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.
922 @param EDX Upper 32-bits of MSR value.
923 Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.
927 MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER Msr;
929 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG);
930 AsmWriteMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG, Msr.Uint64);
932 @note MSR_SKYLAKE_PKG_HDC_CONFIG is defined as MSR_PKG_HDC_CONFIG in SDM.
934 #define MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652
937 MSR information returned for MSR index #MSR_SKYLAKE_PKG_HDC_CONFIG
941 /// Individual bit fields
945 /// [Bits 2:0] PKG_Cx_Monitor. Configures Package Cx state threshold for
946 /// MSR_PKG_HDC_DEEP_RESIDENCY.
948 UINT32 PKG_Cx_Monitor
:3;
953 /// All bit fields as a 32-bit value
957 /// All bit fields as a 64-bit value
960 } MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER
;
964 Core. Core HDC Idle Residency. (R/O). Core_Cx_Duty_Cycle_Cnt.
966 @param ECX MSR_SKYLAKE_CORE_HDC_RESIDENCY (0x00000653)
967 @param EAX Lower 32-bits of MSR value.
968 @param EDX Upper 32-bits of MSR value.
974 Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_HDC_RESIDENCY);
976 @note MSR_SKYLAKE_CORE_HDC_RESIDENCY is defined as MSR_CORE_HDC_RESIDENCY in SDM.
978 #define MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653
982 Package. Accumulate the cycles the package was in C2 state and at least one
983 logical processor was in forced idle. (R/O). Pkg_C2_Duty_Cycle_Cnt.
985 @param ECX MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY (0x00000655)
986 @param EAX Lower 32-bits of MSR value.
987 @param EDX Upper 32-bits of MSR value.
993 Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY);
995 @note MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY is defined as MSR_PKG_HDC_SHALLOW_RESIDENCY in SDM.
997 #define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655
1001 Package. Package Cx HDC Idle Residency. (R/O). Pkg_Cx_Duty_Cycle_Cnt.
1003 @param ECX MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY (0x00000656)
1004 @param EAX Lower 32-bits of MSR value.
1005 @param EDX Upper 32-bits of MSR value.
1007 <b>Example usage</b>
1011 Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY);
1013 @note MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY is defined as MSR_PKG_HDC_DEEP_RESIDENCY in SDM.
1015 #define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656
1019 Package. Core-count Weighted C0 Residency. (R/O). Increment at the same rate
1020 as the TSC. The increment each cycle is weighted by the number of processor
1021 cores in the package that reside in C0. If N cores are simultaneously in C0,
1022 then each cycle the counter increments by N.
1024 @param ECX MSR_SKYLAKE_WEIGHTED_CORE_C0 (0x00000658)
1025 @param EAX Lower 32-bits of MSR value.
1026 @param EDX Upper 32-bits of MSR value.
1028 <b>Example usage</b>
1032 Msr = AsmReadMsr64 (MSR_SKYLAKE_WEIGHTED_CORE_C0);
1034 @note MSR_SKYLAKE_WEIGHTED_CORE_C0 is defined as MSR_WEIGHTED_CORE_C0 in SDM.
1036 #define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658
1040 Package. Any Core C0 Residency. (R/O). Increment at the same rate as the
1041 TSC. The increment each cycle is one if any processor core in the package is
1044 @param ECX MSR_SKYLAKE_ANY_CORE_C0 (0x00000659)
1045 @param EAX Lower 32-bits of MSR value.
1046 @param EDX Upper 32-bits of MSR value.
1048 <b>Example usage</b>
1052 Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_CORE_C0);
1054 @note MSR_SKYLAKE_ANY_CORE_C0 is defined as MSR_ANY_CORE_C0 in SDM.
1056 #define MSR_SKYLAKE_ANY_CORE_C0 0x00000659
1060 Package. Any Graphics Engine C0 Residency. (R/O). Increment at the same rate
1061 as the TSC. The increment each cycle is one if any processor graphic
1062 device's compute engines are in C0.
1064 @param ECX MSR_SKYLAKE_ANY_GFXE_C0 (0x0000065A)
1065 @param EAX Lower 32-bits of MSR value.
1066 @param EDX Upper 32-bits of MSR value.
1068 <b>Example usage</b>
1072 Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_GFXE_C0);
1074 @note MSR_SKYLAKE_ANY_GFXE_C0 is defined as MSR_ANY_GFXE_C0 in SDM.
1076 #define MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A
1080 Package. Core and Graphics Engine Overlapped C0 Residency. (R/O). Increment
1081 at the same rate as the TSC. The increment each cycle is one if at least one
1082 compute engine of the processor graphics is in C0 and at least one processor
1083 core in the package is also in C0.
1085 @param ECX MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 (0x0000065B)
1086 @param EAX Lower 32-bits of MSR value.
1087 @param EDX Upper 32-bits of MSR value.
1089 <b>Example usage</b>
1093 Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0);
1095 @note MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 is defined as MSR_CORE_GFXE_OVERLAP_C0 in SDM.
1097 #define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B
1101 Platform*. Platform Power Limit Control (R/W-L) Allows platform BIOS to
1102 limit power consumption of the platform devices to the specified values. The
1103 Long Duration power consumption is specified via Platform_Power_Limit_1 and
1104 Platform_Power_Limit_1_Time. The Short Duration power consumption limit is
1105 specified via the Platform_Power_Limit_2 with duration chosen by the
1106 processor. The processor implements an exponential-weighted algorithm in the
1107 placement of the time windows.
1109 @param ECX MSR_SKYLAKE_PLATFORM_POWER_LIMIT (0x0000065C)
1110 @param EAX Lower 32-bits of MSR value.
1111 Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.
1112 @param EDX Upper 32-bits of MSR value.
1113 Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.
1115 <b>Example usage</b>
1117 MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER Msr;
1119 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT);
1120 AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT, Msr.Uint64);
1122 @note MSR_SKYLAKE_PLATFORM_POWER_LIMIT is defined as MSR_PLATFORM_POWER_LIMIT in SDM.
1124 #define MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C
1127 MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_POWER_LIMIT
1131 /// Individual bit fields
1135 /// [Bits 14:0] Platform Power Limit #1. Average Power limit value which
1136 /// the platform must not exceed over a time window as specified by
1137 /// Power_Limit_1_TIME field. The default value is the Thermal Design
1138 /// Power (TDP) and varies with product skus. The unit is specified in
1139 /// MSR_RAPLPOWER_UNIT.
1141 UINT32 PlatformPowerLimit1
:15;
1143 /// [Bit 15] Enable Platform Power Limit #1. When set, enables the
1144 /// processor to apply control policy such that the platform power does
1145 /// not exceed Platform Power limit #1 over the time window specified by
1146 /// Power Limit #1 Time Window.
1148 UINT32 EnablePlatformPowerLimit1
:1;
1150 /// [Bit 16] Platform Clamping Limitation #1. When set, allows the
1151 /// processor to go below the OS requested P states in order to maintain
1152 /// the power below specified Platform Power Limit #1 value. This bit is
1153 /// writeable only when CPUID (EAX=6):EAX[4] is set.
1155 UINT32 PlatformClampingLimitation1
:1;
1157 /// [Bits 23:17] Time Window for Platform Power Limit #1. Specifies the
1158 /// duration of the time window over which Platform Power Limit 1 value
1159 /// should be maintained for sustained long duration. This field is made
1160 /// up of two numbers from the following equation: Time Window = (float)
1161 /// ((1+(X/4))*(2^Y)), where: X. = POWER_LIMIT_1_TIME[23:22] Y. =
1162 /// POWER_LIMIT_1_TIME[21:17]. The maximum allowed value in this field is
1163 /// defined in MSR_PKG_POWER_INFO[PKG_MAX_WIN]. The default value is 0DH,
1164 /// The unit is specified in MSR_RAPLPOWER_UNIT[Time Unit].
1169 /// [Bits 46:32] Platform Power Limit #2. Average Power limit value which
1170 /// the platform must not exceed over the Short Duration time window
1171 /// chosen by the processor. The recommended default value is 1.25 times
1172 /// the Long Duration Power Limit (i.e. Platform Power Limit # 1).
1174 UINT32 PlatformPowerLimit2
:15;
1176 /// [Bit 47] Enable Platform Power Limit #2. When set, enables the
1177 /// processor to apply control policy such that the platform power does
1178 /// not exceed Platform Power limit #2 over the Short Duration time window.
1180 UINT32 EnablePlatformPowerLimit2
:1;
1182 /// [Bit 48] Platform Clamping Limitation #2. When set, allows the
1183 /// processor to go below the OS requested P states in order to maintain
1184 /// the power below specified Platform Power Limit #2 value.
1186 UINT32 PlatformClampingLimitation2
:1;
1187 UINT32 Reserved2
:14;
1189 /// [Bit 63] Lock. Setting this bit will lock all other bits of this MSR
1190 /// until system RESET.
1195 /// All bit fields as a 64-bit value
1198 } MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
;
1202 Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last
1203 branch record registers on the last branch record stack. This part of the
1204 stack contains pointers to the source instruction. See also: - Last Branch
1205 Record Stack TOS at 1C9H - Section 17.10.
1207 @param ECX MSR_SKYLAKE_LASTBRANCH_n_FROM_IP
1208 @param EAX Lower 32-bits of MSR value.
1209 @param EDX Upper 32-bits of MSR value.
1211 <b>Example usage</b>
1215 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP);
1216 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP, Msr);
1218 @note MSR_SKYLAKE_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM.
1219 MSR_SKYLAKE_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM.
1220 MSR_SKYLAKE_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM.
1221 MSR_SKYLAKE_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM.
1222 MSR_SKYLAKE_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM.
1223 MSR_SKYLAKE_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM.
1224 MSR_SKYLAKE_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM.
1225 MSR_SKYLAKE_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM.
1226 MSR_SKYLAKE_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM.
1227 MSR_SKYLAKE_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM.
1228 MSR_SKYLAKE_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM.
1229 MSR_SKYLAKE_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM.
1230 MSR_SKYLAKE_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM.
1231 MSR_SKYLAKE_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM.
1232 MSR_SKYLAKE_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM.
1233 MSR_SKYLAKE_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.
1236 #define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690
1237 #define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP 0x00000691
1238 #define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP 0x00000692
1239 #define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP 0x00000693
1240 #define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP 0x00000694
1241 #define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP 0x00000695
1242 #define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP 0x00000696
1243 #define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP 0x00000697
1244 #define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP 0x00000698
1245 #define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP 0x00000699
1246 #define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP 0x0000069A
1247 #define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP 0x0000069B
1248 #define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP 0x0000069C
1249 #define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP 0x0000069D
1250 #define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP 0x0000069E
1251 #define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F
1256 Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)
1257 (frequency refers to processor graphics frequency).
1259 @param ECX MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)
1260 @param EAX Lower 32-bits of MSR value.
1261 Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
1262 @param EDX Upper 32-bits of MSR value.
1263 Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
1265 <b>Example usage</b>
1267 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr;
1269 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS);
1270 AsmWriteMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);
1272 @note MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.
1274 #define MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0
1277 MSR information returned for MSR index
1278 #MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS
1282 /// Individual bit fields
1286 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to
1287 /// assertion of external PROCHOT.
1289 UINT32 PROCHOT_Status
:1;
1291 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a
1294 UINT32 ThermalStatus
:1;
1297 /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency
1298 /// is reduced due to running average thermal limit.
1300 UINT32 RunningAverageThermalLimitStatus
:1;
1302 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due
1303 /// to a thermal alert from a processor Voltage Regulator.
1305 UINT32 VRThermAlertStatus
:1;
1307 /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is
1308 /// reduced due to VR TDC limit.
1310 UINT32 VRThermalDesignCurrentStatus
:1;
1312 /// [Bit 8] Other Status (R0) When set, frequency is reduced due to
1313 /// electrical or other constraints.
1315 UINT32 OtherStatus
:1;
1318 /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When
1319 /// set, frequency is reduced due to package/platform-level power limiting
1324 /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When
1325 /// set, frequency is reduced due to package/platform-level power limiting
1330 /// [Bit 12] Inefficient Operation Status (R0) When set, processor
1331 /// graphics frequency is operating below target frequency.
1333 UINT32 InefficientOperationStatus
:1;
1336 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
1337 /// has asserted since the log bit was last cleared. This log bit will
1338 /// remain set until cleared by software writing 0.
1340 UINT32 PROCHOT_Log
:1;
1342 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
1343 /// has asserted since the log bit was last cleared. This log bit will
1344 /// remain set until cleared by software writing 0.
1346 UINT32 ThermalLog
:1;
1349 /// [Bit 21] Running Average Thermal Limit Log When set, indicates that
1350 /// the RATL Status bit has asserted since the log bit was last cleared.
1351 /// This log bit will remain set until cleared by software writing 0.
1353 UINT32 RunningAverageThermalLimitLog
:1;
1355 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
1356 /// Alert Status bit has asserted since the log bit was last cleared. This
1357 /// log bit will remain set until cleared by software writing 0.
1359 UINT32 VRThermAlertLog
:1;
1361 /// [Bit 23] VR Thermal Design Current Log When set, indicates that the
1362 /// VR Therm Alert Status bit has asserted since the log bit was last
1363 /// cleared. This log bit will remain set until cleared by software
1366 UINT32 VRThermalDesignCurrentLog
:1;
1368 /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has
1369 /// asserted since the log bit was last cleared. This log bit will remain
1370 /// set until cleared by software writing 0.
1375 /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,
1376 /// indicates that the Package/Platform Level PL1 Power Limiting Status
1377 /// bit has asserted since the log bit was last cleared. This log bit will
1378 /// remain set until cleared by software writing 0.
1382 /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,
1383 /// indicates that the Package/Platform Level PL2 Power Limiting Status
1384 /// bit has asserted since the log bit was last cleared. This log bit will
1385 /// remain set until cleared by software writing 0.
1389 /// [Bit 28] Inefficient Operation Log When set, indicates that the
1390 /// Inefficient Operation Status bit has asserted since the log bit was
1391 /// last cleared. This log bit will remain set until cleared by software
1394 UINT32 InefficientOperationLog
:1;
1396 UINT32 Reserved7
:32;
1399 /// All bit fields as a 32-bit value
1403 /// All bit fields as a 64-bit value
1406 } MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER
;
1410 Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)
1411 (frequency refers to ring interconnect in the uncore).
1413 @param ECX MSR_SKYLAKE_RING_PERF_LIMIT_REASONS (0x000006B1)
1414 @param EAX Lower 32-bits of MSR value.
1415 Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.
1416 @param EDX Upper 32-bits of MSR value.
1417 Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.
1419 <b>Example usage</b>
1421 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER Msr;
1423 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS);
1424 AsmWriteMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS, Msr.Uint64);
1426 @note MSR_SKYLAKE_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.
1428 #define MSR_SKYLAKE_RING_PERF_LIMIT_REASONS 0x000006B1
1431 MSR information returned for MSR index #MSR_SKYLAKE_RING_PERF_LIMIT_REASONS
1435 /// Individual bit fields
1439 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to
1440 /// assertion of external PROCHOT.
1442 UINT32 PROCHOT_Status
:1;
1444 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a
1447 UINT32 ThermalStatus
:1;
1450 /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency
1451 /// is reduced due to running average thermal limit.
1453 UINT32 RunningAverageThermalLimitStatus
:1;
1455 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due
1456 /// to a thermal alert from a processor Voltage Regulator.
1458 UINT32 VRThermAlertStatus
:1;
1460 /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is
1461 /// reduced due to VR TDC limit.
1463 UINT32 VRThermalDesignCurrentStatus
:1;
1465 /// [Bit 8] Other Status (R0) When set, frequency is reduced due to
1466 /// electrical or other constraints.
1468 UINT32 OtherStatus
:1;
1471 /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When
1472 /// set, frequency is reduced due to package/Platform-level power limiting
1477 /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When
1478 /// set, frequency is reduced due to package/Platform-level power limiting
1484 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
1485 /// has asserted since the log bit was last cleared. This log bit will
1486 /// remain set until cleared by software writing 0.
1488 UINT32 PROCHOT_Log
:1;
1490 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
1491 /// has asserted since the log bit was last cleared. This log bit will
1492 /// remain set until cleared by software writing 0.
1494 UINT32 ThermalLog
:1;
1497 /// [Bit 21] Running Average Thermal Limit Log When set, indicates that
1498 /// the RATL Status bit has asserted since the log bit was last cleared.
1499 /// This log bit will remain set until cleared by software writing 0.
1501 UINT32 RunningAverageThermalLimitLog
:1;
1503 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
1504 /// Alert Status bit has asserted since the log bit was last cleared. This
1505 /// log bit will remain set until cleared by software writing 0.
1507 UINT32 VRThermAlertLog
:1;
1509 /// [Bit 23] VR Thermal Design Current Log When set, indicates that the
1510 /// VR Therm Alert Status bit has asserted since the log bit was last
1511 /// cleared. This log bit will remain set until cleared by software
1514 UINT32 VRThermalDesignCurrentLog
:1;
1516 /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has
1517 /// asserted since the log bit was last cleared. This log bit will remain
1518 /// set until cleared by software writing 0.
1523 /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,
1524 /// indicates that the Package/Platform Level PL1 Power Limiting Status
1525 /// bit has asserted since the log bit was last cleared. This log bit will
1526 /// remain set until cleared by software writing 0.
1530 /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,
1531 /// indicates that the Package/Platform Level PL2 Power Limiting Status
1532 /// bit has asserted since the log bit was last cleared. This log bit will
1533 /// remain set until cleared by software writing 0.
1537 UINT32 Reserved7
:32;
1540 /// All bit fields as a 32-bit value
1544 /// All bit fields as a 64-bit value
1547 } MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
;
1551 Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch
1552 record registers on the last branch record stack. This part of the stack
1553 contains pointers to the destination instruction. See also: - Last Branch
1554 Record Stack TOS at 1C9H - Section 17.10.
1556 @param ECX MSR_SKYLAKE_LASTBRANCH_n_TO_IP
1557 @param EAX Lower 32-bits of MSR value.
1558 @param EDX Upper 32-bits of MSR value.
1560 <b>Example usage</b>
1564 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP);
1565 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP, Msr);
1567 @note MSR_SKYLAKE_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM.
1568 MSR_SKYLAKE_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM.
1569 MSR_SKYLAKE_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM.
1570 MSR_SKYLAKE_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM.
1571 MSR_SKYLAKE_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM.
1572 MSR_SKYLAKE_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM.
1573 MSR_SKYLAKE_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM.
1574 MSR_SKYLAKE_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM.
1575 MSR_SKYLAKE_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM.
1576 MSR_SKYLAKE_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM.
1577 MSR_SKYLAKE_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM.
1578 MSR_SKYLAKE_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM.
1579 MSR_SKYLAKE_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM.
1580 MSR_SKYLAKE_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM.
1581 MSR_SKYLAKE_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM.
1582 MSR_SKYLAKE_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.
1585 #define MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0
1586 #define MSR_SKYLAKE_LASTBRANCH_17_TO_IP 0x000006D1
1587 #define MSR_SKYLAKE_LASTBRANCH_18_TO_IP 0x000006D2
1588 #define MSR_SKYLAKE_LASTBRANCH_19_TO_IP 0x000006D3
1589 #define MSR_SKYLAKE_LASTBRANCH_20_TO_IP 0x000006D4
1590 #define MSR_SKYLAKE_LASTBRANCH_21_TO_IP 0x000006D5
1591 #define MSR_SKYLAKE_LASTBRANCH_22_TO_IP 0x000006D6
1592 #define MSR_SKYLAKE_LASTBRANCH_23_TO_IP 0x000006D7
1593 #define MSR_SKYLAKE_LASTBRANCH_24_TO_IP 0x000006D8
1594 #define MSR_SKYLAKE_LASTBRANCH_25_TO_IP 0x000006D9
1595 #define MSR_SKYLAKE_LASTBRANCH_26_TO_IP 0x000006DA
1596 #define MSR_SKYLAKE_LASTBRANCH_27_TO_IP 0x000006DB
1597 #define MSR_SKYLAKE_LASTBRANCH_28_TO_IP 0x000006DC
1598 #define MSR_SKYLAKE_LASTBRANCH_29_TO_IP 0x000006DD
1599 #define MSR_SKYLAKE_LASTBRANCH_30_TO_IP 0x000006DE
1600 #define MSR_SKYLAKE_LASTBRANCH_31_TO_IP 0x000006DF
1605 Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet
1606 of last branch record registers on the last branch record stack. This part
1607 of the stack contains flag, TSX-related and elapsed cycle information. See
1608 also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR
1611 @param ECX MSR_SKYLAKE_LBR_INFO_n
1612 @param EAX Lower 32-bits of MSR value.
1613 @param EDX Upper 32-bits of MSR value.
1615 <b>Example usage</b>
1619 Msr = AsmReadMsr64 (MSR_SKYLAKE_LBR_INFO_0);
1620 AsmWriteMsr64 (MSR_SKYLAKE_LBR_INFO_0, Msr);
1622 @note MSR_SKYLAKE_LBR_INFO_0 is defined as MSR_LBR_INFO_0 in SDM.
1623 MSR_SKYLAKE_LBR_INFO_1 is defined as MSR_LBR_INFO_1 in SDM.
1624 MSR_SKYLAKE_LBR_INFO_2 is defined as MSR_LBR_INFO_2 in SDM.
1625 MSR_SKYLAKE_LBR_INFO_3 is defined as MSR_LBR_INFO_3 in SDM.
1626 MSR_SKYLAKE_LBR_INFO_4 is defined as MSR_LBR_INFO_4 in SDM.
1627 MSR_SKYLAKE_LBR_INFO_5 is defined as MSR_LBR_INFO_5 in SDM.
1628 MSR_SKYLAKE_LBR_INFO_6 is defined as MSR_LBR_INFO_6 in SDM.
1629 MSR_SKYLAKE_LBR_INFO_7 is defined as MSR_LBR_INFO_7 in SDM.
1630 MSR_SKYLAKE_LBR_INFO_8 is defined as MSR_LBR_INFO_8 in SDM.
1631 MSR_SKYLAKE_LBR_INFO_9 is defined as MSR_LBR_INFO_9 in SDM.
1632 MSR_SKYLAKE_LBR_INFO_10 is defined as MSR_LBR_INFO_10 in SDM.
1633 MSR_SKYLAKE_LBR_INFO_11 is defined as MSR_LBR_INFO_11 in SDM.
1634 MSR_SKYLAKE_LBR_INFO_12 is defined as MSR_LBR_INFO_12 in SDM.
1635 MSR_SKYLAKE_LBR_INFO_13 is defined as MSR_LBR_INFO_13 in SDM.
1636 MSR_SKYLAKE_LBR_INFO_14 is defined as MSR_LBR_INFO_14 in SDM.
1637 MSR_SKYLAKE_LBR_INFO_15 is defined as MSR_LBR_INFO_15 in SDM.
1638 MSR_SKYLAKE_LBR_INFO_16 is defined as MSR_LBR_INFO_16 in SDM.
1639 MSR_SKYLAKE_LBR_INFO_17 is defined as MSR_LBR_INFO_17 in SDM.
1640 MSR_SKYLAKE_LBR_INFO_18 is defined as MSR_LBR_INFO_18 in SDM.
1641 MSR_SKYLAKE_LBR_INFO_19 is defined as MSR_LBR_INFO_19 in SDM.
1642 MSR_SKYLAKE_LBR_INFO_20 is defined as MSR_LBR_INFO_20 in SDM.
1643 MSR_SKYLAKE_LBR_INFO_21 is defined as MSR_LBR_INFO_21 in SDM.
1644 MSR_SKYLAKE_LBR_INFO_22 is defined as MSR_LBR_INFO_22 in SDM.
1645 MSR_SKYLAKE_LBR_INFO_23 is defined as MSR_LBR_INFO_23 in SDM.
1646 MSR_SKYLAKE_LBR_INFO_24 is defined as MSR_LBR_INFO_24 in SDM.
1647 MSR_SKYLAKE_LBR_INFO_25 is defined as MSR_LBR_INFO_25 in SDM.
1648 MSR_SKYLAKE_LBR_INFO_26 is defined as MSR_LBR_INFO_26 in SDM.
1649 MSR_SKYLAKE_LBR_INFO_27 is defined as MSR_LBR_INFO_27 in SDM.
1650 MSR_SKYLAKE_LBR_INFO_28 is defined as MSR_LBR_INFO_28 in SDM.
1651 MSR_SKYLAKE_LBR_INFO_29 is defined as MSR_LBR_INFO_29 in SDM.
1652 MSR_SKYLAKE_LBR_INFO_30 is defined as MSR_LBR_INFO_30 in SDM.
1653 MSR_SKYLAKE_LBR_INFO_31 is defined as MSR_LBR_INFO_31 in SDM.
1656 #define MSR_SKYLAKE_LBR_INFO_0 0x00000DC0
1657 #define MSR_SKYLAKE_LBR_INFO_1 0x00000DC1
1658 #define MSR_SKYLAKE_LBR_INFO_2 0x00000DC2
1659 #define MSR_SKYLAKE_LBR_INFO_3 0x00000DC3
1660 #define MSR_SKYLAKE_LBR_INFO_4 0x00000DC4
1661 #define MSR_SKYLAKE_LBR_INFO_5 0x00000DC5
1662 #define MSR_SKYLAKE_LBR_INFO_6 0x00000DC6
1663 #define MSR_SKYLAKE_LBR_INFO_7 0x00000DC7
1664 #define MSR_SKYLAKE_LBR_INFO_8 0x00000DC8
1665 #define MSR_SKYLAKE_LBR_INFO_9 0x00000DC9
1666 #define MSR_SKYLAKE_LBR_INFO_10 0x00000DCA
1667 #define MSR_SKYLAKE_LBR_INFO_11 0x00000DCB
1668 #define MSR_SKYLAKE_LBR_INFO_12 0x00000DCC
1669 #define MSR_SKYLAKE_LBR_INFO_13 0x00000DCD
1670 #define MSR_SKYLAKE_LBR_INFO_14 0x00000DCE
1671 #define MSR_SKYLAKE_LBR_INFO_15 0x00000DCF
1672 #define MSR_SKYLAKE_LBR_INFO_16 0x00000DD0
1673 #define MSR_SKYLAKE_LBR_INFO_17 0x00000DD1
1674 #define MSR_SKYLAKE_LBR_INFO_18 0x00000DD2
1675 #define MSR_SKYLAKE_LBR_INFO_19 0x00000DD3
1676 #define MSR_SKYLAKE_LBR_INFO_20 0x00000DD4
1677 #define MSR_SKYLAKE_LBR_INFO_21 0x00000DD5
1678 #define MSR_SKYLAKE_LBR_INFO_22 0x00000DD6
1679 #define MSR_SKYLAKE_LBR_INFO_23 0x00000DD7
1680 #define MSR_SKYLAKE_LBR_INFO_24 0x00000DD8
1681 #define MSR_SKYLAKE_LBR_INFO_25 0x00000DD9
1682 #define MSR_SKYLAKE_LBR_INFO_26 0x00000DDA
1683 #define MSR_SKYLAKE_LBR_INFO_27 0x00000DDB
1684 #define MSR_SKYLAKE_LBR_INFO_28 0x00000DDC
1685 #define MSR_SKYLAKE_LBR_INFO_29 0x00000DDD
1686 #define MSR_SKYLAKE_LBR_INFO_30 0x00000DDE
1687 #define MSR_SKYLAKE_LBR_INFO_31 0x00000DDF
1692 Package. Uncore fixed counter control (R/W).
1694 @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTRL (0x00000394)
1695 @param EAX Lower 32-bits of MSR value.
1696 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.
1697 @param EDX Upper 32-bits of MSR value.
1698 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.
1700 <b>Example usage</b>
1702 MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER Msr;
1704 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL);
1705 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL, Msr.Uint64);
1707 @note MSR_SKYLAKE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.
1709 #define MSR_SKYLAKE_UNC_PERF_FIXED_CTRL 0x00000394
1712 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTRL
1716 /// Individual bit fields
1719 UINT32 Reserved1
:20;
1721 /// [Bit 20] Enable overflow propagation.
1723 UINT32 EnableOverflow
:1;
1726 /// [Bit 22] Enable counting.
1728 UINT32 EnableCounting
:1;
1730 UINT32 Reserved4
:32;
1733 /// All bit fields as a 32-bit value
1737 /// All bit fields as a 64-bit value
1740 } MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER
;
1744 Package. Uncore fixed counter.
1746 @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTR (0x00000395)
1747 @param EAX Lower 32-bits of MSR value.
1748 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.
1749 @param EDX Upper 32-bits of MSR value.
1750 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.
1752 <b>Example usage</b>
1754 MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER Msr;
1756 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR);
1757 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR, Msr.Uint64);
1759 @note MSR_SKYLAKE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.
1761 #define MSR_SKYLAKE_UNC_PERF_FIXED_CTR 0x00000395
1764 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTR
1768 /// Individual bit fields
1772 /// [Bits 31:0] Current count.
1774 UINT32 CurrentCount
:32;
1776 /// [Bits 43:32] Current count.
1778 UINT32 CurrentCountHi
:12;
1782 /// All bit fields as a 64-bit value
1785 } MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER
;
1789 Package. Uncore C-Box configuration information (R/O).
1791 @param ECX MSR_SKYLAKE_UNC_CBO_CONFIG (0x00000396)
1792 @param EAX Lower 32-bits of MSR value.
1793 Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.
1794 @param EDX Upper 32-bits of MSR value.
1795 Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.
1797 <b>Example usage</b>
1799 MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER Msr;
1801 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_CONFIG);
1803 @note MSR_SKYLAKE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.
1805 #define MSR_SKYLAKE_UNC_CBO_CONFIG 0x00000396
1808 MSR information returned for MSR index #MSR_SKYLAKE_UNC_CBO_CONFIG
1812 /// Individual bit fields
1816 /// [Bits 3:0] Specifies the number of C-Box units with programmable
1817 /// counters (including processor cores and processor graphics),.
1820 UINT32 Reserved1
:28;
1821 UINT32 Reserved2
:32;
1824 /// All bit fields as a 32-bit value
1828 /// All bit fields as a 64-bit value
1831 } MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER
;
1835 Package. Uncore Arb unit, performance counter 0.
1837 @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR0 (0x000003B0)
1838 @param EAX Lower 32-bits of MSR value.
1839 @param EDX Upper 32-bits of MSR value.
1841 <b>Example usage</b>
1845 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0);
1846 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0, Msr);
1848 @note MSR_SKYLAKE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.
1850 #define MSR_SKYLAKE_UNC_ARB_PERFCTR0 0x000003B0
1854 Package. Uncore Arb unit, performance counter 1.
1856 @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR1 (0x000003B1)
1857 @param EAX Lower 32-bits of MSR value.
1858 @param EDX Upper 32-bits of MSR value.
1860 <b>Example usage</b>
1864 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1);
1865 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1, Msr);
1867 @note MSR_SKYLAKE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.
1869 #define MSR_SKYLAKE_UNC_ARB_PERFCTR1 0x000003B1
1873 Package. Uncore Arb unit, counter 0 event select MSR.
1875 @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 (0x000003B2)
1876 @param EAX Lower 32-bits of MSR value.
1877 @param EDX Upper 32-bits of MSR value.
1879 <b>Example usage</b>
1883 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0);
1884 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0, Msr);
1886 @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.
1888 #define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 0x000003B2
1892 Package. Uncore Arb unit, counter 1 event select MSR.
1894 @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 (0x000003B3)
1895 @param EAX Lower 32-bits of MSR value.
1896 @param EDX Upper 32-bits of MSR value.
1898 <b>Example usage</b>
1902 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1);
1903 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1, Msr);
1905 @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 is defined as MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 in SDM.
1907 #define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 0x000003B3
1911 Package. Uncore C-Box 0, counter 0 event select MSR.
1913 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 (0x00000700)
1914 @param EAX Lower 32-bits of MSR value.
1915 @param EDX Upper 32-bits of MSR value.
1917 <b>Example usage</b>
1921 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0);
1922 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0, Msr);
1924 @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.
1926 #define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 0x00000700
1930 Package. Uncore C-Box 0, counter 1 event select MSR.
1932 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 (0x00000701)
1933 @param EAX Lower 32-bits of MSR value.
1934 @param EDX Upper 32-bits of MSR value.
1936 <b>Example usage</b>
1940 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1);
1941 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1, Msr);
1943 @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.
1945 #define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 0x00000701
1949 Package. Uncore C-Box 0, performance counter 0.
1951 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 (0x00000706)
1952 @param EAX Lower 32-bits of MSR value.
1953 @param EDX Upper 32-bits of MSR value.
1955 <b>Example usage</b>
1959 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0);
1960 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0, Msr);
1962 @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.
1964 #define MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 0x00000706
1968 Package. Uncore C-Box 0, performance counter 1.
1970 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 (0x00000707)
1971 @param EAX Lower 32-bits of MSR value.
1972 @param EDX Upper 32-bits of MSR value.
1974 <b>Example usage</b>
1978 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1);
1979 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1, Msr);
1981 @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.
1983 #define MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 0x00000707
1987 Package. Uncore C-Box 1, counter 0 event select MSR.
1989 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 (0x00000710)
1990 @param EAX Lower 32-bits of MSR value.
1991 @param EDX Upper 32-bits of MSR value.
1993 <b>Example usage</b>
1997 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0);
1998 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0, Msr);
2000 @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.
2002 #define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 0x00000710
2006 Package. Uncore C-Box 1, counter 1 event select MSR.
2008 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 (0x00000711)
2009 @param EAX Lower 32-bits of MSR value.
2010 @param EDX Upper 32-bits of MSR value.
2012 <b>Example usage</b>
2016 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1);
2017 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1, Msr);
2019 @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.
2021 #define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 0x00000711
2025 Package. Uncore C-Box 1, performance counter 0.
2027 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 (0x00000716)
2028 @param EAX Lower 32-bits of MSR value.
2029 @param EDX Upper 32-bits of MSR value.
2031 <b>Example usage</b>
2035 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0);
2036 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0, Msr);
2038 @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.
2040 #define MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 0x00000716
2044 Package. Uncore C-Box 1, performance counter 1.
2046 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 (0x00000717)
2047 @param EAX Lower 32-bits of MSR value.
2048 @param EDX Upper 32-bits of MSR value.
2050 <b>Example usage</b>
2054 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1);
2055 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1, Msr);
2057 @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.
2059 #define MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 0x00000717
2063 Package. Uncore C-Box 2, counter 0 event select MSR.
2065 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 (0x00000720)
2066 @param EAX Lower 32-bits of MSR value.
2067 @param EDX Upper 32-bits of MSR value.
2069 <b>Example usage</b>
2073 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0);
2074 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0, Msr);
2076 @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.
2078 #define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 0x00000720
2082 Package. Uncore C-Box 2, counter 1 event select MSR.
2084 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 (0x00000721)
2085 @param EAX Lower 32-bits of MSR value.
2086 @param EDX Upper 32-bits of MSR value.
2088 <b>Example usage</b>
2092 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1);
2093 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1, Msr);
2095 @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.
2097 #define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 0x00000721
2101 Package. Uncore C-Box 2, performance counter 0.
2103 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 (0x00000726)
2104 @param EAX Lower 32-bits of MSR value.
2105 @param EDX Upper 32-bits of MSR value.
2107 <b>Example usage</b>
2111 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0);
2112 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0, Msr);
2114 @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.
2116 #define MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 0x00000726
2120 Package. Uncore C-Box 2, performance counter 1.
2122 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 (0x00000727)
2123 @param EAX Lower 32-bits of MSR value.
2124 @param EDX Upper 32-bits of MSR value.
2126 <b>Example usage</b>
2130 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1);
2131 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1, Msr);
2133 @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.
2135 #define MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 0x00000727
2139 Package. Uncore C-Box 3, counter 0 event select MSR.
2141 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 (0x00000730)
2142 @param EAX Lower 32-bits of MSR value.
2143 @param EDX Upper 32-bits of MSR value.
2145 <b>Example usage</b>
2149 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0);
2150 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0, Msr);
2152 @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.
2154 #define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 0x00000730
2158 Package. Uncore C-Box 3, counter 1 event select MSR.
2160 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 (0x00000731)
2161 @param EAX Lower 32-bits of MSR value.
2162 @param EDX Upper 32-bits of MSR value.
2164 <b>Example usage</b>
2168 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1);
2169 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1, Msr);
2171 @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.
2173 #define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 0x00000731
2177 Package. Uncore C-Box 3, performance counter 0.
2179 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 (0x00000736)
2180 @param EAX Lower 32-bits of MSR value.
2181 @param EDX Upper 32-bits of MSR value.
2183 <b>Example usage</b>
2187 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0);
2188 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0, Msr);
2190 @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.
2192 #define MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 0x00000736
2196 Package. Uncore C-Box 3, performance counter 1.
2198 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 (0x00000737)
2199 @param EAX Lower 32-bits of MSR value.
2200 @param EDX Upper 32-bits of MSR value.
2202 <b>Example usage</b>
2206 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1);
2207 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1, Msr);
2209 @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.
2211 #define MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 0x00000737
2215 Package. Uncore PMU global control.
2217 @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL (0x00000E01)
2218 @param EAX Lower 32-bits of MSR value.
2219 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.
2220 @param EDX Upper 32-bits of MSR value.
2221 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.
2223 <b>Example usage</b>
2225 MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;
2227 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL);
2228 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);
2230 @note MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.
2232 #define MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL 0x00000E01
2235 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL
2239 /// Individual bit fields
2243 /// [Bit 0] Slice 0 select.
2245 UINT32 PMI_Sel_Slice0
:1;
2247 /// [Bit 1] Slice 1 select.
2249 UINT32 PMI_Sel_Slice1
:1;
2251 /// [Bit 2] Slice 2 select.
2253 UINT32 PMI_Sel_Slice2
:1;
2255 /// [Bit 3] Slice 3 select.
2257 UINT32 PMI_Sel_Slice3
:1;
2259 /// [Bit 4] Slice 4select.
2261 UINT32 PMI_Sel_Slice4
:1;
2262 UINT32 Reserved1
:14;
2263 UINT32 Reserved2
:10;
2265 /// [Bit 29] Enable all uncore counters.
2269 /// [Bit 30] Enable wake on PMI.
2273 /// [Bit 31] Enable Freezing counter when overflow.
2276 UINT32 Reserved3
:32;
2279 /// All bit fields as a 32-bit value
2283 /// All bit fields as a 64-bit value
2286 } MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER
;
2290 Package. Uncore PMU main status.
2292 @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS (0x00000E02)
2293 @param EAX Lower 32-bits of MSR value.
2294 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.
2295 @param EDX Upper 32-bits of MSR value.
2296 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.
2298 <b>Example usage</b>
2300 MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;
2302 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS);
2303 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);
2305 @note MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.
2307 #define MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS 0x00000E02
2310 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS
2314 /// Individual bit fields
2318 /// [Bit 0] Fixed counter overflowed.
2322 /// [Bit 1] An ARB counter overflowed.
2327 /// [Bit 3] A CBox counter overflowed (on any slice).
2330 UINT32 Reserved2
:28;
2331 UINT32 Reserved3
:32;
2334 /// All bit fields as a 32-bit value
2338 /// All bit fields as a 64-bit value
2341 } MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER
;
2345 Package. NPK Address Used by AET Messages (R/W).
2347 @param ECX MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE (0x00000080)
2348 @param EAX Lower 32-bits of MSR value.
2349 Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.
2350 @param EDX Upper 32-bits of MSR value.
2351 Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.
2353 <b>Example usage</b>
2355 MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER Msr;
2357 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE);
2358 AsmWriteMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE, Msr.Uint64);
2361 #define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080
2364 MSR information returned for MSR index
2365 #MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE
2369 /// Individual bit fields
2373 /// [Bit 0] Lock Bit If set, this MSR cannot be re-written anymore. Lock
2374 /// bit has to be set in order for the AET packets to be directed to NPK
2380 /// [Bits 31:18] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.
2382 UINT32 ACPIBAR_BASE_ADDRESS
:14;
2384 /// [Bits 63:32] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.
2389 /// All bit fields as a 64-bit value
2392 } MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER
;
2396 Core. Processor Reserved Memory Range Register - Physical Base Control
2399 @param ECX MSR_SKYLAKE_PRMRR_PHYS_BASE (0x000001F4)
2400 @param EAX Lower 32-bits of MSR value.
2401 Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER.
2402 @param EDX Upper 32-bits of MSR value.
2403 Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER.
2405 <b>Example usage</b>
2407 MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER Msr;
2409 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE);
2410 AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE, Msr.Uint64);
2413 #define MSR_SKYLAKE_PRMRR_PHYS_BASE 0x000001F4
2416 MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_BASE
2420 /// Individual bit fields
2424 /// [Bits 2:0] MemType PRMRR BASE MemType.
2426 UINT32 MemTypePRMRRBASEMemType
:3;
2429 /// [Bits 31:12] Base PRMRR Base Address.
2431 UINT32 BasePRMRRBaseAddress
:20;
2433 /// [Bits 45:32] Base PRMRR Base Address.
2436 UINT32 Reserved2
:18;
2439 /// All bit fields as a 64-bit value
2442 } MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER
;
2446 Core. Processor Reserved Memory Range Register - Physical Mask Control
2449 @param ECX MSR_SKYLAKE_PRMRR_PHYS_MASK (0x000001F5)
2450 @param EAX Lower 32-bits of MSR value.
2451 Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER.
2452 @param EDX Upper 32-bits of MSR value.
2453 Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER.
2455 <b>Example usage</b>
2457 MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER Msr;
2459 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK);
2460 AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK, Msr.Uint64);
2463 #define MSR_SKYLAKE_PRMRR_PHYS_MASK 0x000001F5
2466 MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_MASK
2470 /// Individual bit fields
2473 UINT32 Reserved1
:10;
2475 /// [Bit 10] Lock Lock bit for the PRMRR.
2479 /// [Bit 11] VLD Enable bit for the PRMRR.
2483 /// [Bits 31:12] Mask PRMRR MASK bits.
2487 /// [Bits 45:32] Mask PRMRR MASK bits.
2490 UINT32 Reserved2
:18;
2493 /// All bit fields as a 64-bit value
2496 } MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER
;
2500 Core. Valid PRMRR Configurations (R/W).
2502 @param ECX MSR_SKYLAKE_PRMRR_VALID_CONFIG (0x000001FB)
2503 @param EAX Lower 32-bits of MSR value.
2504 Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER.
2505 @param EDX Upper 32-bits of MSR value.
2506 Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER.
2508 <b>Example usage</b>
2510 MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER Msr;
2512 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG);
2513 AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG, Msr.Uint64);
2516 #define MSR_SKYLAKE_PRMRR_VALID_CONFIG 0x000001FB
2519 MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_VALID_CONFIG
2523 /// Individual bit fields
2527 /// [Bit 0] 1M supported MEE size.
2532 /// [Bit 5] 32M supported MEE size.
2536 /// [Bit 6] 64M supported MEE size.
2540 /// [Bit 7] 128M supported MEE size.
2543 UINT32 Reserved2
:24;
2544 UINT32 Reserved3
:32;
2547 /// All bit fields as a 32-bit value
2551 /// All bit fields as a 64-bit value
2554 } MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER
;
2558 Package. (R/W) The PRMRR range is used to protect Xucode memory from
2559 unauthorized reads and writes. Any IO access to this range is aborted. This
2560 register controls the location of the PRMRR range by indicating its starting
2561 address. It functions in tandem with the PRMRR mask register.
2563 @param ECX MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE (0x000002F4)
2564 @param EAX Lower 32-bits of MSR value.
2565 Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER.
2566 @param EDX Upper 32-bits of MSR value.
2567 Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER.
2569 <b>Example usage</b>
2571 MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER Msr;
2573 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE);
2574 AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE, Msr.Uint64);
2577 #define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE 0x000002F4
2580 MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE
2584 /// Individual bit fields
2587 UINT32 Reserved1
:12;
2589 /// [Bits 31:12] Range Base This field corresponds to bits 38:12 of the
2590 /// base address memory range which is allocated to PRMRR memory.
2594 /// [Bits 38:32] Range Base This field corresponds to bits 38:12 of the
2595 /// base address memory range which is allocated to PRMRR memory.
2598 UINT32 Reserved2
:25;
2601 /// All bit fields as a 64-bit value
2604 } MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER
;
2608 Package. (R/W) This register controls the size of the PRMRR range by
2609 indicating which address bits must match the PRMRR base register value.
2611 @param ECX MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK (0x000002F5)
2612 @param EAX Lower 32-bits of MSR value.
2613 Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER.
2614 @param EDX Upper 32-bits of MSR value.
2615 Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER.
2617 <b>Example usage</b>
2619 MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER Msr;
2621 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK);
2622 AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK, Msr.Uint64);
2625 #define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK 0x000002F5
2628 MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK
2632 /// Individual bit fields
2635 UINT32 Reserved1
:10;
2637 /// [Bit 10] Lock Setting this bit locks all writeable settings in this
2638 /// register, including itself.
2642 /// [Bit 11] Range_En Indicates whether the PRMRR range is enabled and
2646 UINT32 Reserved2
:20;
2647 UINT32 Reserved3
:32;
2650 /// All bit fields as a 32-bit value
2654 /// All bit fields as a 64-bit value
2657 } MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER
;
2660 Package. Ring Ratio Limit (R/W) This register provides Min/Max Ratio Limits
2661 for the LLC and Ring.
2663 @param ECX MSR_SKYLAKE_RING_RATIO_LIMIT (0x00000620)
2664 @param EAX Lower 32-bits of MSR value.
2665 Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER.
2666 @param EDX Upper 32-bits of MSR value.
2667 Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER.
2669 <b>Example usage</b>
2671 MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER Msr;
2673 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT);
2674 AsmWriteMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT, Msr.Uint64);
2677 #define MSR_SKYLAKE_RING_RATIO_LIMIT 0x00000620
2680 MSR information returned for MSR index #MSR_SKYLAKE_RING_RATIO_LIMIT
2684 /// Individual bit fields
2688 /// [Bits 6:0] MAX_Ratio This field is used to limit the max ratio of the
2694 /// [Bits 14:8] MIN_Ratio Writing to this field controls the minimum
2695 /// possible ratio of the LLC/Ring.
2698 UINT32 Reserved2
:17;
2699 UINT32 Reserved3
:32;
2702 /// All bit fields as a 32-bit value
2706 /// All bit fields as a 64-bit value
2709 } MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER
;
2713 Branch Monitoring Global Control (R/W).
2715 @param ECX MSR_SKYLAKE_BR_DETECT_CTRL (0x00000350)
2716 @param EAX Lower 32-bits of MSR value.
2717 Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER.
2718 @param EDX Upper 32-bits of MSR value.
2719 Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER.
2721 <b>Example usage</b>
2723 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER Msr;
2725 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL);
2726 AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL, Msr.Uint64);
2729 #define MSR_SKYLAKE_BR_DETECT_CTRL 0x00000350
2732 MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_CTRL
2736 /// Individual bit fields
2740 /// [Bit 0] EnMonitoring Global enable for branch monitoring.
2742 UINT32 EnMonitoring
:1;
2744 /// [Bit 1] EnExcept Enable branch monitoring event signaling on threshold
2745 /// trip. The branch monitoring event handler is signaled via the existing
2746 /// PMI signaling mechanism as programmed from the corresponding local
2751 /// [Bit 2] EnLBRFrz Enable LBR freeze on threshold trip. This will cause
2752 /// the LBR frozen bit 58 to be set in IA32_PERF_GLOBAL_STATUS when a
2753 /// triggering condition occurs and this bit is enabled.
2757 /// [Bit 3] DisableInGuest When set to '1', branch monitoring, event
2758 /// triggering and LBR freeze actions are disabled when operating at VMX
2759 /// non-root operation.
2761 UINT32 DisableInGuest
:1;
2764 /// [Bits 17:8] WindowSize Window size defined by WindowCntSel. Values 0 -
2765 /// 1023 are supported. Once the Window counter reaches the WindowSize
2766 /// count both the Window Counter and all Branch Monitoring Counters are
2769 UINT32 WindowSize
:10;
2772 /// [Bits 25:24] WindowCntSel Window event count select: '00 =
2773 /// Instructions retired. '01 = Branch instructions retired '10 = Return
2774 /// instructions retired. '11 = Indirect branch instructions retired.
2776 UINT32 WindowCntSel
:2;
2778 /// [Bit 26] CntAndMode When set to '1', the overall branch monitoring
2779 /// event triggering condition is true only if all enabled counters'
2780 /// threshold conditions are true. When '0', the threshold tripping
2781 /// condition is true if any enabled counters' threshold is true.
2783 UINT32 CntAndMode
:1;
2785 UINT32 Reserved4
:32;
2788 /// All bit fields as a 32-bit value
2792 /// All bit fields as a 64-bit value
2795 } MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER
;
2798 Branch Monitoring Global Status (R/W).
2800 @param ECX MSR_SKYLAKE_BR_DETECT_STATUS (0x00000351)
2801 @param EAX Lower 32-bits of MSR value.
2802 Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER.
2803 @param EDX Upper 32-bits of MSR value.
2804 Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER.
2806 <b>Example usage</b>
2808 MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER Msr;
2810 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS);
2811 AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS, Msr.Uint64);
2814 #define MSR_SKYLAKE_BR_DETECT_STATUS 0x00000351
2817 MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_STATUS
2821 /// Individual bit fields
2825 /// [Bit 0] Branch Monitoring Event Signaled When set to '1', Branch
2826 /// Monitoring event signaling is blocked until this bit is cleared by
2829 UINT32 BranchMonitoringEventSignaled
:1;
2831 /// [Bit 1] LBRsValid This status bit is set to '1' if the LBR state is
2832 /// considered valid for sampling by branch monitoring software.
2837 /// [Bit 8] CntrHit0 Branch monitoring counter #0 threshold hit. This
2838 /// status bit is sticky and once set requires clearing by software.
2839 /// Counter operation continues independent of the state of the bit.
2843 /// [Bit 9] CntrHit1 Branch monitoring counter #1 threshold hit. This
2844 /// status bit is sticky and once set requires clearing by software.
2845 /// Counter operation continues independent of the state of the bit.
2850 /// [Bits 25:16] CountWindow The current value of the window counter. The
2851 /// count value is frozen on a valid branch monitoring triggering
2852 /// condition. This is a 10-bit unsigned value.
2854 UINT32 CountWindow
:10;
2857 /// [Bits 39:32] Count0 The current value of counter 0 updated after each
2858 /// occurrence of the event being counted. The count value is frozen on a
2859 /// valid branch monitoring triggering condition (in which case CntrHit0
2860 /// will also be set). This is an 8-bit signed value (2's complement).
2861 /// Heuristic events which only increment will saturate and freeze at
2862 /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum
2863 /// value 0x7F (+127) and minimum value 0x80 (-128).
2867 /// [Bits 47:40] Count1 The current value of counter 1 updated after each
2868 /// occurrence of the event being counted. The count value is frozen on a
2869 /// valid branch monitoring triggering condition (in which case CntrHit1
2870 /// will also be set). This is an 8-bit signed value (2's complement).
2871 /// Heuristic events which only increment will saturate and freeze at
2872 /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum
2873 /// value 0x7F (+127) and minimum value 0x80 (-128).
2876 UINT32 Reserved4
:16;
2879 /// All bit fields as a 32-bit value
2883 /// All bit fields as a 64-bit value
2886 } MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER
;
2890 Package. Package C3 Residency Counter (R/O). Note: C-state values are
2891 processor specific C-state code names, unrelated to MWAIT extension C-state
2892 parameters or ACPI C-states.
2894 @param ECX MSR_SKYLAKE_PKG_C3_RESIDENCY (0x000003F8)
2895 @param EAX Lower 32-bits of MSR value.
2896 @param EDX Upper 32-bits of MSR value.
2898 <b>Example usage</b>
2902 Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_C3_RESIDENCY);
2905 #define MSR_SKYLAKE_PKG_C3_RESIDENCY 0x000003F8
2909 Core. Core C1 Residency Counter (R/O). Value since last reset for the Core
2910 C1 residency. Counter rate is the Max Non-Turbo frequency (same as TSC).
2911 This counter counts in case both of the core's threads are in an idle state
2912 and at least one of the core's thread residency is in a C1 state or in one
2913 of its sub states. The counter is updated only after a core C state exit.
2914 Note: Always reads 0 if core C1 is unsupported. A value of zero indicates
2915 that this processor does not support core C1 or never entered core C1 level
2918 @param ECX MSR_SKYLAKE_CORE_C1_RESIDENCY (0x00000660)
2919 @param EAX Lower 32-bits of MSR value.
2920 @param EDX Upper 32-bits of MSR value.
2922 <b>Example usage</b>
2926 Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C1_RESIDENCY);
2929 #define MSR_SKYLAKE_CORE_C1_RESIDENCY 0x00000660
2933 Core. Core C3 Residency Counter (R/O). Will always return 0.
2935 @param ECX MSR_SKYLAKE_CORE_C3_RESIDENCY (0x00000662)
2936 @param EAX Lower 32-bits of MSR value.
2937 @param EDX Upper 32-bits of MSR value.
2939 <b>Example usage</b>
2943 Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C3_RESIDENCY);
2946 #define MSR_SKYLAKE_CORE_C3_RESIDENCY 0x00000662
2950 Package. Protected Processor Inventory Number Enable Control (R/W).
2952 @param ECX MSR_SKYLAKE_PPIN_CTL (0x0000004E)
2953 @param EAX Lower 32-bits of MSR value.
2954 Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER.
2955 @param EDX Upper 32-bits of MSR value.
2956 Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER.
2958 <b>Example usage</b>
2960 MSR_SKYLAKE_PPIN_CTL_REGISTER Msr;
2962 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PPIN_CTL);
2963 AsmWriteMsr64 (MSR_SKYLAKE_PPIN_CTL, Msr.Uint64);
2966 #define MSR_SKYLAKE_PPIN_CTL 0x0000004E
2969 MSR information returned for MSR index #MSR_SKYLAKE_PPIN_CTL
2973 /// Individual bit fields
2977 /// [Bit 0] LockOut (R/WO) See Table 2-25.
2981 /// [Bit 1] Enable_PPIN (R/W) See Table 2-25.
2983 UINT32 Enable_PPIN
:1;
2984 UINT32 Reserved1
:30;
2985 UINT32 Reserved2
:32;
2988 /// All bit fields as a 32-bit value
2992 /// All bit fields as a 64-bit value
2995 } MSR_SKYLAKE_PPIN_CTL_REGISTER
;
2999 Package. Protected Processor Inventory Number (R/O). Protected Processor
3000 Inventory Number (R/O) See Table 2-25.
3002 @param ECX MSR_SKYLAKE_PPIN (0x0000004F)
3003 @param EAX Lower 32-bits of MSR value.
3004 @param EDX Upper 32-bits of MSR value.
3006 <b>Example usage</b>
3010 Msr = AsmReadMsr64 (MSR_SKYLAKE_PPIN);
3013 #define MSR_SKYLAKE_PPIN 0x0000004F
3017 Package. Platform Information Contains power management and other model
3018 specific features enumeration. See http://biosbits.org.
3020 @param ECX MSR_SKYLAKE_PLATFORM_INFO (0x000000CE)
3021 @param EAX Lower 32-bits of MSR value.
3022 Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER.
3023 @param EDX Upper 32-bits of MSR value.
3024 Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER.
3026 <b>Example usage</b>
3028 MSR_SKYLAKE_PLATFORM_INFO_REGISTER Msr;
3030 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_INFO);
3031 AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_INFO, Msr.Uint64);
3034 #define MSR_SKYLAKE_PLATFORM_INFO 0x000000CE
3037 MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_INFO
3041 /// Individual bit fields
3046 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.
3048 UINT32 MaximumNon_TurboRatio
:8;
3051 /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.
3056 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See
3059 UINT32 ProgrammableRatioLimit
:1;
3061 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See
3064 UINT32 ProgrammableTDPLimit
:1;
3066 /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.
3068 UINT32 ProgrammableTJOFFSET
:1;
3072 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.
3074 UINT32 MaximumEfficiencyRatio
:8;
3075 UINT32 Reserved6
:16;
3078 /// All bit fields as a 64-bit value
3081 } MSR_SKYLAKE_PLATFORM_INFO_REGISTER
;
3085 Core. C-State Configuration Control (R/W) Note: C-state values are processor
3086 specific C-state code names, unrelated to MWAIT extension C-state parameters
3087 or ACPI C-states. `See http://biosbits.org. <http://biosbits.org/>`__.
3089 @param ECX MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL (0x000000E2)
3090 @param EAX Lower 32-bits of MSR value.
3091 Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER.
3092 @param EDX Upper 32-bits of MSR value.
3093 Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER.
3095 <b>Example usage</b>
3097 MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
3099 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL);
3100 AsmWriteMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
3103 #define MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL 0x000000E2
3106 MSR information returned for MSR index #MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL
3110 /// Individual bit fields
3114 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
3115 /// processor-specific C-state code name (consuming the least power) for
3116 /// the package. The default is set as factory-configured package Cstate
3117 /// limit. The following C-state code name encodings are supported: 000b:
3118 /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)
3119 /// 011b: C6 (retention) 111b: No Package C state limits. All C states
3120 /// supported by the processor are available.
3122 UINT32 C_StateLimit
:3;
3125 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
3127 UINT32 MWAITRedirectionEnable
:1;
3130 /// [Bit 15] CFG Lock (R/WO).
3134 /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor
3135 /// will convert HALT or MWAT(C1) to MWAIT(C6).
3137 UINT32 AutomaticC_StateConversionEnable
:1;
3140 /// [Bit 25] C3 State Auto Demotion Enable (R/W).
3142 UINT32 C3StateAutoDemotionEnable
:1;
3144 /// [Bit 26] C1 State Auto Demotion Enable (R/W).
3146 UINT32 C1StateAutoDemotionEnable
:1;
3148 /// [Bit 27] Enable C3 Undemotion (R/W).
3150 UINT32 EnableC3Undemotion
:1;
3152 /// [Bit 28] Enable C1 Undemotion (R/W).
3154 UINT32 EnableC1Undemotion
:1;
3156 /// [Bit 29] Package C State Demotion Enable (R/W).
3158 UINT32 CStateDemotionEnable
:1;
3160 /// [Bit 30] Package C State UnDemotion Enable (R/W).
3162 UINT32 CStateUnDemotionEnable
:1;
3164 UINT32 Reserved5
:32;
3167 /// All bit fields as a 32-bit value
3171 /// All bit fields as a 64-bit value
3174 } MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER
;
3178 Thread. Global Machine Check Capability (R/O).
3180 @param ECX MSR_SKYLAKE_IA32_MCG_CAP (0x00000179)
3181 @param EAX Lower 32-bits of MSR value.
3182 Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER.
3183 @param EDX Upper 32-bits of MSR value.
3184 Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER.
3186 <b>Example usage</b>
3188 MSR_SKYLAKE_IA32_MCG_CAP_REGISTER Msr;
3190 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_MCG_CAP);
3193 #define MSR_SKYLAKE_IA32_MCG_CAP 0x00000179
3196 MSR information returned for MSR index #MSR_SKYLAKE_IA32_MCG_CAP
3200 /// Individual bit fields
3204 /// [Bits 7:0] Count.
3208 /// [Bit 8] MCG_CTL_P.
3212 /// [Bit 9] MCG_EXT_P.
3216 /// [Bit 10] MCP_CMCI_P.
3218 UINT32 MCP_CMCI_P
:1;
3220 /// [Bit 11] MCG_TES_P.
3225 /// [Bits 23:16] MCG_EXT_CNT.
3227 UINT32 MCG_EXT_CNT
:8;
3229 /// [Bit 24] MCG_SER_P.
3233 /// [Bit 25] MCG_EM_P.
3237 /// [Bit 26] MCG_ELOG_P.
3239 UINT32 MCG_ELOG_P
:1;
3241 UINT32 Reserved3
:32;
3244 /// All bit fields as a 32-bit value
3248 /// All bit fields as a 64-bit value
3251 } MSR_SKYLAKE_IA32_MCG_CAP_REGISTER
;
3255 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
3256 Enhancement. Accessible only while in SMM.
3258 @param ECX MSR_SKYLAKE_SMM_MCA_CAP (0x0000017D)
3259 @param EAX Lower 32-bits of MSR value.
3260 Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER.
3261 @param EDX Upper 32-bits of MSR value.
3262 Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER.
3264 <b>Example usage</b>
3266 MSR_SKYLAKE_SMM_MCA_CAP_REGISTER Msr;
3268 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_SMM_MCA_CAP);
3269 AsmWriteMsr64 (MSR_SKYLAKE_SMM_MCA_CAP, Msr.Uint64);
3272 #define MSR_SKYLAKE_SMM_MCA_CAP 0x0000017D
3275 MSR information returned for MSR index #MSR_SKYLAKE_SMM_MCA_CAP
3279 /// Individual bit fields
3282 UINT32 Reserved1
:32;
3283 UINT32 Reserved2
:26;
3285 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
3286 /// SMM code access restriction is supported and a host-space interface is
3287 /// available to SMM handler.
3289 UINT32 SMM_Code_Access_Chk
:1;
3291 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
3292 /// SMM long flow indicator is supported and a host-space interface is
3293 /// available to SMM handler.
3295 UINT32 Long_Flow_Indication
:1;
3299 /// All bit fields as a 64-bit value
3302 } MSR_SKYLAKE_SMM_MCA_CAP_REGISTER
;
3306 Package. Temperature Target.
3308 @param ECX MSR_SKYLAKE_TEMPERATURE_TARGET (0x000001A2)
3309 @param EAX Lower 32-bits of MSR value.
3310 Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER.
3311 @param EDX Upper 32-bits of MSR value.
3312 Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER.
3314 <b>Example usage</b>
3316 MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER Msr;
3318 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET);
3319 AsmWriteMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET, Msr.Uint64);
3322 #define MSR_SKYLAKE_TEMPERATURE_TARGET 0x000001A2
3325 MSR information returned for MSR index #MSR_SKYLAKE_TEMPERATURE_TARGET
3329 /// Individual bit fields
3332 UINT32 Reserved1
:16;
3334 /// [Bits 23:16] Temperature Target (RO) See Table 2-25.
3336 UINT32 TemperatureTarget
:8;
3338 /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.
3340 UINT32 TCCActivationOffset
:4;
3342 UINT32 Reserved3
:32;
3345 /// All bit fields as a 32-bit value
3349 /// All bit fields as a 64-bit value
3352 } MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER
;
3355 Package. This register defines the active core ranges for each frequency
3356 point. NUMCORE[0:7] must be populated in ascending order. NUMCORE[i+1] must
3357 be greater than NUMCORE[i]. Entries with NUMCORE[i] == 0 will be ignored.
3358 The last valid entry must have NUMCORE >= the number of cores in the SKU. If
3359 any of the rules above are broken, the configuration is silently rejected.
3361 @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES (0x000001AE)
3362 @param EAX Lower 32-bits of MSR value.
3363 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER.
3364 @param EDX Upper 32-bits of MSR value.
3365 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER.
3367 <b>Example usage</b>
3369 MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER Msr;
3371 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES);
3372 AsmWriteMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES, Msr.Uint64);
3375 #define MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES 0x000001AE
3378 MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES
3382 /// Individual bit fields
3386 /// [Bits 7:0] NUMCORE_0 Defines the active core ranges for each frequency
3391 /// [Bits 15:8] NUMCORE_1 Defines the active core ranges for each
3392 /// frequency point.
3396 /// [Bits 23:16] NUMCORE_2 Defines the active core ranges for each
3397 /// frequency point.
3401 /// [Bits 31:24] NUMCORE_3 Defines the active core ranges for each
3402 /// frequency point.
3406 /// [Bits 39:32] NUMCORE_4 Defines the active core ranges for each
3407 /// frequency point.
3411 /// [Bits 47:40] NUMCORE_5 Defines the active core ranges for each
3412 /// frequency point.
3416 /// [Bits 55:48] NUMCORE_6 Defines the active core ranges for each
3417 /// frequency point.
3421 /// [Bits 63:56] NUMCORE_7 Defines the active core ranges for each
3422 /// frequency point.
3427 /// All bit fields as a 64-bit value
3430 } MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER
;
3434 Package. Unit Multipliers Used in RAPL Interfaces (R/O).
3436 @param ECX MSR_SKYLAKE_RAPL_POWER_UNIT (0x00000606)
3437 @param EAX Lower 32-bits of MSR value.
3438 Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER.
3439 @param EDX Upper 32-bits of MSR value.
3440 Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER.
3442 <b>Example usage</b>
3444 MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER Msr;
3446 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RAPL_POWER_UNIT);
3449 #define MSR_SKYLAKE_RAPL_POWER_UNIT 0x00000606
3452 MSR information returned for MSR index #MSR_SKYLAKE_RAPL_POWER_UNIT
3456 /// Individual bit fields
3460 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
3462 UINT32 PowerUnits
:4;
3465 /// [Bits 12:8] Package. Energy Status Units Energy related information
3466 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
3467 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
3470 UINT32 EnergyStatusUnits
:5;
3473 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
3477 UINT32 Reserved3
:12;
3478 UINT32 Reserved4
:32;
3481 /// All bit fields as a 32-bit value
3485 /// All bit fields as a 64-bit value
3488 } MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER
;
3492 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
3495 @param ECX MSR_SKYLAKE_DRAM_POWER_LIMIT (0x00000618)
3496 @param EAX Lower 32-bits of MSR value.
3497 @param EDX Upper 32-bits of MSR value.
3499 <b>Example usage</b>
3503 Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT);
3504 AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT, Msr);
3507 #define MSR_SKYLAKE_DRAM_POWER_LIMIT 0x00000618
3511 Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.
3513 @param ECX MSR_SKYLAKE_DRAM_ENERGY_STATUS (0x00000619)
3514 @param EAX Lower 32-bits of MSR value.
3515 Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER.
3516 @param EDX Upper 32-bits of MSR value.
3517 Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER.
3519 <b>Example usage</b>
3521 MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER Msr;
3523 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_DRAM_ENERGY_STATUS);
3526 #define MSR_SKYLAKE_DRAM_ENERGY_STATUS 0x00000619
3529 MSR information returned for MSR index #MSR_SKYLAKE_DRAM_ENERGY_STATUS
3533 /// Individual bit fields
3537 /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration
3538 /// to enable DRAM RAPL mode 0 (Direct VR).
3544 /// All bit fields as a 32-bit value
3548 /// All bit fields as a 64-bit value
3551 } MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER
;
3555 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
3558 @param ECX MSR_SKYLAKE_DRAM_PERF_STATUS (0x0000061B)
3559 @param EAX Lower 32-bits of MSR value.
3560 @param EDX Upper 32-bits of MSR value.
3562 <b>Example usage</b>
3566 Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_PERF_STATUS);
3569 #define MSR_SKYLAKE_DRAM_PERF_STATUS 0x0000061B
3573 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
3575 @param ECX MSR_SKYLAKE_DRAM_POWER_INFO (0x0000061C)
3576 @param EAX Lower 32-bits of MSR value.
3577 @param EDX Upper 32-bits of MSR value.
3579 <b>Example usage</b>
3583 Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO);
3584 AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO, Msr);
3587 #define MSR_SKYLAKE_DRAM_POWER_INFO 0x0000061C
3591 Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
3592 fields represent the widest possible range of uncore frequencies. Writing to
3593 these fields allows software to control the minimum and the maximum
3594 frequency that hardware will select.
3596 @param ECX MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT (0x00000620)
3597 @param EAX Lower 32-bits of MSR value.
3598 Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER.
3599 @param EDX Upper 32-bits of MSR value.
3600 Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER.
3602 <b>Example usage</b>
3604 MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
3606 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT);
3607 AsmWriteMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
3610 #define MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT 0x00000620
3613 MSR information returned for MSR index #MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT
3617 /// Individual bit fields
3621 /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
3627 /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
3628 /// possible ratio of the LLC/Ring.
3631 UINT32 Reserved2
:17;
3632 UINT32 Reserved3
:32;
3635 /// All bit fields as a 32-bit value
3639 /// All bit fields as a 64-bit value
3642 } MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER
;
3646 Package. Reserved (R/O) Reads return 0.
3648 @param ECX MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)
3649 @param EAX Lower 32-bits of MSR value.
3650 @param EDX Upper 32-bits of MSR value.
3652 <b>Example usage</b>
3656 Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);
3659 #define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639
3663 THREAD. Monitoring Event Select Register (R/W) If CPUID.(EAX=07H,
3664 ECX=0):EBX.RDT-M[bit 12] = 1.
3666 @param ECX MSR_SKYLAKE_IA32_QM_EVTSEL (0x00000C8D)
3667 @param EAX Lower 32-bits of MSR value.
3668 Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER.
3669 @param EDX Upper 32-bits of MSR value.
3670 Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER.
3672 <b>Example usage</b>
3674 MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER Msr;
3676 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL);
3677 AsmWriteMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL, Msr.Uint64);
3680 #define MSR_SKYLAKE_IA32_QM_EVTSEL 0x00000C8D
3683 MSR information returned for MSR index #MSR_SKYLAKE_IA32_QM_EVTSEL
3687 /// Individual bit fields
3691 /// [Bits 7:0] EventID (RW) Event encoding: 0x00: No monitoring. 0x01: L3
3692 /// occupancy monitoring. 0x02: Total memory bandwidth monitoring. 0x03:
3693 /// Local memory bandwidth monitoring. All other encoding reserved.
3696 UINT32 Reserved1
:24;
3698 /// [Bits 41:32] RMID (RW).
3701 UINT32 Reserved2
:22;
3704 /// All bit fields as a 64-bit value
3707 } MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER
;
3711 THREAD. Resource Association Register (R/W).
3713 @param ECX MSR_SKYLAKE_IA32_PQR_ASSOC (0x00000C8F)
3714 @param EAX Lower 32-bits of MSR value.
3715 Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER.
3716 @param EDX Upper 32-bits of MSR value.
3717 Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER.
3719 <b>Example usage</b>
3721 MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER Msr;
3723 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC);
3724 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC, Msr.Uint64);
3727 #define MSR_SKYLAKE_IA32_PQR_ASSOC 0x00000C8F
3730 MSR information returned for MSR index #MSR_SKYLAKE_IA32_PQR_ASSOC
3734 /// Individual bit fields
3738 /// [Bits 9:0] RMID.
3741 UINT32 Reserved1
:22;
3743 /// [Bits 51:32] COS (R/W).
3746 UINT32 Reserved2
:12;
3749 /// All bit fields as a 64-bit value
3752 } MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER
;
3756 Package. L3 Class Of Service Mask - COS N (R/W) If CPUID.(EAX=10H,
3757 ECX=1):EDX.COS_MAX[15:0] >=0.
3759 @param ECX MSR_SKYLAKE_IA32_L3_QOS_MASK_N
3760 @param EAX Lower 32-bits of MSR value.
3761 Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER.
3762 @param EDX Upper 32-bits of MSR value.
3763 Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER.
3765 <b>Example usage</b>
3767 MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER Msr;
3769 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N);
3770 AsmWriteMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N, Msr.Uint64);
3773 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_0 0x00000C90
3774 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_1 0x00000C91
3775 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_2 0x00000C92
3776 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_3 0x00000C93
3777 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_4 0x00000C94
3778 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_5 0x00000C95
3779 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_6 0x00000C96
3780 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_7 0x00000C97
3781 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_8 0x00000C98
3782 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_9 0x00000C99
3783 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_10 0x00000C9A
3784 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_11 0x00000C9B
3785 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_12 0x00000C9C
3786 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_13 0x00000C9D
3787 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_14 0x00000C9E
3788 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_15 0x00000C9F
3791 MSR information returned for MSR index #MSR_SKYLAKE_IA32_L3_QOS_MASK_N
3795 /// Individual bit fields
3799 /// [Bit 19:0] CBM: Bit vector of available L3 ways for COS N enforcement.
3802 UINT32 Reserved2
:12;
3803 UINT32 Reserved3
:32;
3806 /// All bit fields as a 32-bit value
3810 /// All bit fields as a 64-bit value
3813 } MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER
;