2 MSR Definitions for Intel processors based on the Skylake microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-14.
24 #ifndef __SKYLAKE_MSR_H__
25 #define __SKYLAKE_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
31 RW if MSR_PLATFORM_INFO.[28] = 1.
33 @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT (0x000001AD)
34 @param EAX Lower 32-bits of MSR value.
35 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.
36 @param EDX Upper 32-bits of MSR value.
37 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.
41 MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER Msr;
43 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT);
45 @note MSR_SKYLAKE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
47 #define MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD
50 MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT
54 /// Individual bit fields
58 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
59 /// limit of 1 core active.
63 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
64 /// limit of 2 core active.
68 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
69 /// limit of 3 core active.
73 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
74 /// limit of 4 core active.
80 /// All bit fields as a 32-bit value
84 /// All bit fields as a 64-bit value
87 } MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER
;
91 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4)
92 that points to the MSR containing the most recent branch record.
94 @param ECX MSR_SKYLAKE_LASTBRANCH_TOS (0x000001C9)
95 @param EAX Lower 32-bits of MSR value.
96 @param EDX Upper 32-bits of MSR value.
102 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS);
103 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS, Msr);
105 @note MSR_SKYLAKE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
107 #define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9
111 Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of
112 an 128-bit external entropy value for key derivation of an enclave.
114 @param ECX MSR_SKYLAKE_SGXOWNER0 (0x00000300)
115 @param EAX Lower 32-bits of MSR value.
116 @param EDX Upper 32-bits of MSR value.
122 Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER0);
124 @note MSR_SKYLAKE_SGXOWNER0 is defined as MSR_SGXOWNER0 in SDM.
126 #define MSR_SKYLAKE_SGXOWNER0 0x00000300
130 Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of
131 an 128-bit external entropy value for key derivation of an enclave.
133 @param ECX MSR_SKYLAKE_SGXOWNER1 (0x00000301)
134 @param EAX Lower 32-bits of MSR value.
135 @param EDX Upper 32-bits of MSR value.
141 Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER1);
143 @note MSR_SKYLAKE_SGXOWNER1 is defined as MSR_SGXOWNER1 in SDM.
145 #define MSR_SKYLAKE_SGXOWNER1 0x00000301
149 See Table 35-2. See Section 18.2.2.3, "Full-Width Writes to Performance
152 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS (0x0000038E)
153 @param EAX Lower 32-bits of MSR value.
154 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS_REGISTER.
155 @param EDX Upper 32-bits of MSR value.
156 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS_REGISTER.
160 MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS_REGISTER Msr;
162 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS);
163 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);
165 @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
167 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS 0x0000038E
170 MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS
174 /// Individual bit fields
178 /// [Bit 0] Thread. Ovf_PMC0.
182 /// [Bit 1] Thread. Ovf_PMC1.
186 /// [Bit 2] Thread. Ovf_PMC2.
190 /// [Bit 3] Thread. Ovf_PMC3.
194 /// [Bit 4] Thread. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
198 /// [Bit 5] Thread. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
202 /// [Bit 6] Thread. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
206 /// [Bit 7] Thread. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
211 /// [Bit 32] Thread. Ovf_FixedCtr0.
213 UINT32 Ovf_FixedCtr0
:1;
215 /// [Bit 33] Thread. Ovf_FixedCtr1.
217 UINT32 Ovf_FixedCtr1
:1;
219 /// [Bit 34] Thread. Ovf_FixedCtr2.
221 UINT32 Ovf_FixedCtr2
:1;
224 /// [Bit 55] Thread. Trace_ToPA_PMI.
226 UINT32 Trace_ToPA_PMI
:1;
229 /// [Bit 58] Thread. LBR_Frz.
233 /// [Bit 59] Thread. CTR_Frz.
237 /// [Bit 60] Thread. ASCI.
241 /// [Bit 61] Thread. Ovf_Uncore.
245 /// [Bit 62] Thread. Ovf_BufDSSAVE.
247 UINT32 Ovf_BufDSSAVE
:1;
249 /// [Bit 63] Thread. CondChgd.
254 /// All bit fields as a 64-bit value
257 } MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS_REGISTER
;
261 See Table 35-2. See Section 18.2.2.3, "Full-Width Writes to Performance
264 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
265 @param EAX Lower 32-bits of MSR value.
266 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
267 @param EDX Upper 32-bits of MSR value.
268 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
272 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;
274 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET);
275 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
277 @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
279 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
282 MSR information returned for MSR index
283 #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET
287 /// Individual bit fields
291 /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.
295 /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.
299 /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.
303 /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.
307 /// [Bit 4] Thread. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
311 /// [Bit 5] Thread. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
315 /// [Bit 6] Thread. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
319 /// [Bit 7] Thread. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
324 /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.
326 UINT32 Ovf_FixedCtr0
:1;
328 /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.
330 UINT32 Ovf_FixedCtr1
:1;
332 /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.
334 UINT32 Ovf_FixedCtr2
:1;
337 /// [Bit 55] Thread. Set 1 to clear Trace_ToPA_PMI.
339 UINT32 Trace_ToPA_PMI
:1;
342 /// [Bit 58] Thread. Set 1 to clear LBR_Frz.
346 /// [Bit 59] Thread. Set 1 to clear CTR_Frz.
350 /// [Bit 60] Thread. Set 1 to clear ASCI.
354 /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.
358 /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.
360 UINT32 Ovf_BufDSSAVE
:1;
362 /// [Bit 63] Thread. Set 1 to clear CondChgd.
367 /// All bit fields as a 64-bit value
370 } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
;
374 See Table 35-2. See Section 18.2.2.3, "Full-Width Writes to Performance
377 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
378 @param EAX Lower 32-bits of MSR value.
379 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
380 @param EDX Upper 32-bits of MSR value.
381 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
385 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;
387 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET);
388 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
390 @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
392 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
395 MSR information returned for MSR index
396 #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET
400 /// Individual bit fields
404 /// [Bit 0] Thread. Set 1 to cause Ovf_PMC0 = 1.
408 /// [Bit 1] Thread. Set 1 to cause Ovf_PMC1 = 1.
412 /// [Bit 2] Thread. Set 1 to cause Ovf_PMC2 = 1.
416 /// [Bit 3] Thread. Set 1 to cause Ovf_PMC3 = 1.
420 /// [Bit 4] Thread. Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4).
424 /// [Bit 5] Thread. Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5).
428 /// [Bit 6] Thread. Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6).
432 /// [Bit 7] Thread. Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7).
437 /// [Bit 32] Thread. Set 1 to cause Ovf_FixedCtr0 = 1.
439 UINT32 Ovf_FixedCtr0
:1;
441 /// [Bit 33] Thread. Set 1 to cause Ovf_FixedCtr1 = 1.
443 UINT32 Ovf_FixedCtr1
:1;
445 /// [Bit 34] Thread. Set 1 to cause Ovf_FixedCtr2 = 1.
447 UINT32 Ovf_FixedCtr2
:1;
450 /// [Bit 55] Thread. Set 1 to cause Trace_ToPA_PMI = 1.
452 UINT32 Trace_ToPA_PMI
:1;
455 /// [Bit 58] Thread. Set 1 to cause LBR_Frz = 1.
459 /// [Bit 59] Thread. Set 1 to cause CTR_Frz = 1.
463 /// [Bit 60] Thread. Set 1 to cause ASCI = 1.
467 /// [Bit 61] Thread. Set 1 to cause Ovf_Uncore.
471 /// [Bit 62] Thread. Set 1 to cause Ovf_BufDSSAVE.
473 UINT32 Ovf_BufDSSAVE
:1;
477 /// All bit fields as a 64-bit value
480 } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
;
484 Thread. FrontEnd Precise Event Condition Select (R/W).
486 @param ECX MSR_SKYLAKE_PEBS_FRONTEND (0x000003F7)
487 @param EAX Lower 32-bits of MSR value.
488 Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.
489 @param EDX Upper 32-bits of MSR value.
490 Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.
494 MSR_SKYLAKE_PEBS_FRONTEND_REGISTER Msr;
496 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PEBS_FRONTEND);
497 AsmWriteMsr64 (MSR_SKYLAKE_PEBS_FRONTEND, Msr.Uint64);
499 @note MSR_SKYLAKE_PEBS_FRONTEND is defined as MSR_PEBS_FRONTEND in SDM.
501 #define MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7
504 MSR information returned for MSR index #MSR_SKYLAKE_PEBS_FRONTEND
508 /// Individual bit fields
512 /// [Bits 2:0] Event Code Select.
514 UINT32 EventCodeSelect
:3;
517 /// [Bit 4] Event Code Select High.
519 UINT32 EventCodeSelectHigh
:1;
522 /// [Bits 19:8] IDQ_Bubble_Length Specifier.
524 UINT32 IDQ_Bubble_Length
:12;
526 /// [Bits 22:20] IDQ_Bubble_Width Specifier.
528 UINT32 IDQ_Bubble_Width
:3;
533 /// All bit fields as a 32-bit value
537 /// All bit fields as a 64-bit value
540 } MSR_SKYLAKE_PEBS_FRONTEND_REGISTER
;
544 Platform*. Platform Energy Counter. (R/O). This MSR is valid only if both
545 platform vendor hardware implementation and BIOS enablement support it. This
546 MSR will read 0 if not valid.
548 @param ECX MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER (0x0000064D)
549 @param EAX Lower 32-bits of MSR value.
550 Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.
551 @param EDX Upper 32-bits of MSR value.
552 Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.
556 MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER Msr;
558 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER);
560 @note MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER is defined as MSR_PLATFORM_ENERGY_COUNTER in SDM.
562 #define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D
565 MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER
569 /// Individual bit fields
573 /// [Bits 31:0] Total energy consumed by all devices in the platform that
574 /// receive power from integrated power delivery mechanism, Included
575 /// platform devices are processor cores, SOC, memory, add-on or
576 /// peripheral devices that get powered directly from the platform power
577 /// delivery means. The energy units are specified in the
578 /// MSR_RAPL_POWER_UNIT.Enery_Status_Unit.
580 UINT32 TotalEnergy
:32;
584 /// All bit fields as a 32-bit value
588 /// All bit fields as a 64-bit value
591 } MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER
;
595 Thread. Productive Performance Count. (R/O). Hardware's view of workload
596 scalability. See Section 14.4.5.1.
598 @param ECX MSR_SKYLAKE_PPERF (0x0000064E)
599 @param EAX Lower 32-bits of MSR value.
600 @param EDX Upper 32-bits of MSR value.
606 Msr = AsmReadMsr64 (MSR_SKYLAKE_PPERF);
608 @note MSR_SKYLAKE_PPERF is defined as MSR_PPERF in SDM.
610 #define MSR_SKYLAKE_PPERF 0x0000064E
614 Package. HDC Configuration (R/W)..
616 @param ECX MSR_SKYLAKE_PKG_HDC_CONFIG (0x00000652)
617 @param EAX Lower 32-bits of MSR value.
618 Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.
619 @param EDX Upper 32-bits of MSR value.
620 Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.
624 MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER Msr;
626 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG);
627 AsmWriteMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG, Msr.Uint64);
629 @note MSR_SKYLAKE_PKG_HDC_CONFIG is defined as MSR_PKG_HDC_CONFIG in SDM.
631 #define MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652
634 MSR information returned for MSR index #MSR_SKYLAKE_PKG_HDC_CONFIG
638 /// Individual bit fields
642 /// [Bits 2:0] PKG_Cx_Monitor. Configures Package Cx state threshold for
643 /// MSR_PKG_HDC_DEEP_RESIDENCY.
645 UINT32 PKG_Cx_Monitor
:3;
650 /// All bit fields as a 32-bit value
654 /// All bit fields as a 64-bit value
657 } MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER
;
661 Core. Core HDC Idle Residency. (R/O). Core_Cx_Duty_Cycle_Cnt.
663 @param ECX MSR_SKYLAKE_CORE_HDC_RESIDENCY (0x00000653)
664 @param EAX Lower 32-bits of MSR value.
665 @param EDX Upper 32-bits of MSR value.
671 Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_HDC_RESIDENCY);
673 @note MSR_SKYLAKE_CORE_HDC_RESIDENCY is defined as MSR_CORE_HDC_RESIDENCY in SDM.
675 #define MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653
679 Package. Accumulate the cycles the package was in C2 state and at least one
680 logical processor was in forced idle. (R/O). Pkg_C2_Duty_Cycle_Cnt.
682 @param ECX MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY (0x00000655)
683 @param EAX Lower 32-bits of MSR value.
684 @param EDX Upper 32-bits of MSR value.
690 Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY);
692 @note MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY is defined as MSR_PKG_HDC_SHALLOW_RESIDENCY in SDM.
694 #define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655
698 Package. Package Cx HDC Idle Residency. (R/O). Pkg_Cx_Duty_Cycle_Cnt.
700 @param ECX MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY (0x00000656)
701 @param EAX Lower 32-bits of MSR value.
702 @param EDX Upper 32-bits of MSR value.
708 Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY);
710 @note MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY is defined as MSR_PKG_HDC_DEEP_RESIDENCY in SDM.
712 #define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656
716 Package. Core-count Weighted C0 Residency. (R/O). Increment at the same rate
717 as the TSC. The increment each cycle is weighted by the number of processor
718 cores in the package that reside in C0. If N cores are simultaneously in C0,
719 then each cycle the counter increments by N.
721 @param ECX MSR_SKYLAKE_WEIGHTED_CORE_C0 (0x00000658)
722 @param EAX Lower 32-bits of MSR value.
723 @param EDX Upper 32-bits of MSR value.
729 Msr = AsmReadMsr64 (MSR_SKYLAKE_WEIGHTED_CORE_C0);
731 @note MSR_SKYLAKE_WEIGHTED_CORE_C0 is defined as MSR_WEIGHTED_CORE_C0 in SDM.
733 #define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658
737 Package. Any Core C0 Residency. (R/O). Increment at the same rate as the
738 TSC. The increment each cycle is one if any processor core in the package is
741 @param ECX MSR_SKYLAKE_ANY_CORE_C0 (0x00000659)
742 @param EAX Lower 32-bits of MSR value.
743 @param EDX Upper 32-bits of MSR value.
749 Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_CORE_C0);
751 @note MSR_SKYLAKE_ANY_CORE_C0 is defined as MSR_ANY_CORE_C0 in SDM.
753 #define MSR_SKYLAKE_ANY_CORE_C0 0x00000659
757 Package. Any Graphics Engine C0 Residency. (R/O). Increment at the same rate
758 as the TSC. The increment each cycle is one if any processor graphic
759 device's compute engines are in C0.
761 @param ECX MSR_SKYLAKE_ANY_GFXE_C0 (0x0000065A)
762 @param EAX Lower 32-bits of MSR value.
763 @param EDX Upper 32-bits of MSR value.
769 Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_GFXE_C0);
771 @note MSR_SKYLAKE_ANY_GFXE_C0 is defined as MSR_ANY_GFXE_C0 in SDM.
773 #define MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A
777 Package. Core and Graphics Engine Overlapped C0 Residency. (R/O). Increment
778 at the same rate as the TSC. The increment each cycle is one if at least one
779 compute engine of the processor graphics is in C0 and at least one processor
780 core in the package is also in C0.
782 @param ECX MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 (0x0000065B)
783 @param EAX Lower 32-bits of MSR value.
784 @param EDX Upper 32-bits of MSR value.
790 Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0);
792 @note MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 is defined as MSR_CORE_GFXE_OVERLAP_C0 in SDM.
794 #define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B
798 Platform*. Platform Power Limit Control (R/W-L) Allows platform BIOS to
799 limit power consumption of the platform devices to the specified values. The
800 Long Duration power consumption is specified via Platform_Power_Limit_1 and
801 Platform_Power_Limit_1_Time. The Short Duration power consumption limit is
802 specified via the Platform_Power_Limit_2 with duration chosen by the
803 processor. The processor implements an exponential-weighted algorithm in the
804 placement of the time windows.
806 @param ECX MSR_SKYLAKE_PLATFORM_POWER_LIMIT (0x0000065C)
807 @param EAX Lower 32-bits of MSR value.
808 Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.
809 @param EDX Upper 32-bits of MSR value.
810 Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.
814 MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER Msr;
816 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT);
817 AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT, Msr.Uint64);
819 @note MSR_SKYLAKE_PLATFORM_POWER_LIMIT is defined as MSR_PLATFORM_POWER_LIMIT in SDM.
821 #define MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C
824 MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_POWER_LIMIT
828 /// Individual bit fields
832 /// [Bits 14:0] Platform Power Limit #1. Average Power limit value which
833 /// the platform must not exceed over a time window as specified by
834 /// Power_Limit_1_TIME field. The default value is the Thermal Design
835 /// Power (TDP) and varies with product skus. The unit is specified in
836 /// MSR_RAPLPOWER_UNIT.
838 UINT32 PlatformPowerLimit1
:15;
840 /// [Bit 15] Enable Platform Power Limit #1. When set, enables the
841 /// processor to apply control policy such that the platform power does
842 /// not exceed Platform Power limit #1 over the time window specified by
843 /// Power Limit #1 Time Window.
845 UINT32 EnablePlatformPowerLimit1
:1;
847 /// [Bit 16] Platform Clamping Limitation #1. When set, allows the
848 /// processor to go below the OS requested P states in order to maintain
849 /// the power below specified Platform Power Limit #1 value. This bit is
850 /// writeable only when CPUID (EAX=6):EAX[4] is set.
852 UINT32 PlatformClampingLimitation1
:1;
854 /// [Bits 23:17] Time Window for Platform Power Limit #1. Specifies the
855 /// duration of the time window over which Platform Power Limit 1 value
856 /// should be maintained for sustained long duration. This field is made
857 /// up of two numbers from the following equation: Time Window = (float)
858 /// ((1+(X/4))*(2^Y)), where: X. = POWER_LIMIT_1_TIME[23:22] Y. =
859 /// POWER_LIMIT_1_TIME[21:17]. The maximum allowed value in this field is
860 /// defined in MSR_PKG_POWER_INFO[PKG_MAX_WIN]. The default value is 0DH,
861 /// The unit is specified in MSR_RAPLPOWER_UNIT[Time Unit].
866 /// [Bits 46:32] Platform Power Limit #2. Average Power limit value which
867 /// the platform must not exceed over the Short Duration time window
868 /// chosen by the processor. The recommended default value is 1.25 times
869 /// the Long Duration Power Limit (i.e. Platform Power Limit # 1).
871 UINT32 PlatformPowerLimit2
:15;
873 /// [Bit 47] Enable Platform Power Limit #2. When set, enables the
874 /// processor to apply control policy such that the platform power does
875 /// not exceed Platform Power limit #2 over the Short Duration time window.
877 UINT32 EnablePlatformPowerLimit2
:1;
879 /// [Bit 48] Platform Clamping Limitation #2. When set, allows the
880 /// processor to go below the OS requested P states in order to maintain
881 /// the power below specified Platform Power Limit #2 value.
883 UINT32 PlatformClampingLimitation2
:1;
886 /// [Bit 63] Lock. Setting this bit will lock all other bits of this MSR
887 /// until system RESET.
892 /// All bit fields as a 64-bit value
895 } MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
;
899 Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last
900 branch record registers on the last branch record stack. This part of the
901 stack contains pointers to the source instruction. See also: - Last Branch
902 Record Stack TOS at 1C9H - Section 17.9.
904 @param ECX MSR_SKYLAKE_LASTBRANCH_n_FROM_IP
905 @param EAX Lower 32-bits of MSR value.
906 @param EDX Upper 32-bits of MSR value.
912 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP);
913 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP, Msr);
915 @note MSR_SKYLAKE_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM.
916 MSR_SKYLAKE_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM.
917 MSR_SKYLAKE_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM.
918 MSR_SKYLAKE_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM.
919 MSR_SKYLAKE_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM.
920 MSR_SKYLAKE_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM.
921 MSR_SKYLAKE_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM.
922 MSR_SKYLAKE_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM.
923 MSR_SKYLAKE_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM.
924 MSR_SKYLAKE_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM.
925 MSR_SKYLAKE_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM.
926 MSR_SKYLAKE_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM.
927 MSR_SKYLAKE_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM.
928 MSR_SKYLAKE_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM.
929 MSR_SKYLAKE_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM.
930 MSR_SKYLAKE_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.
933 #define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690
934 #define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP 0x00000691
935 #define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP 0x00000692
936 #define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP 0x00000693
937 #define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP 0x00000694
938 #define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP 0x00000695
939 #define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP 0x00000696
940 #define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP 0x00000697
941 #define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP 0x00000698
942 #define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP 0x00000699
943 #define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP 0x0000069A
944 #define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP 0x0000069B
945 #define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP 0x0000069C
946 #define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP 0x0000069D
947 #define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP 0x0000069E
948 #define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F
952 Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch
953 record registers on the last branch record stack. This part of the stack
954 contains pointers to the destination instruction. See also: - Last Branch
955 Record Stack TOS at 1C9H - Section 17.9.
957 @param ECX MSR_SKYLAKE_LASTBRANCH_n_TO_IP
958 @param EAX Lower 32-bits of MSR value.
959 @param EDX Upper 32-bits of MSR value.
965 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP);
966 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP, Msr);
968 @note MSR_SKYLAKE_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM.
969 MSR_SKYLAKE_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM.
970 MSR_SKYLAKE_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM.
971 MSR_SKYLAKE_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM.
972 MSR_SKYLAKE_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM.
973 MSR_SKYLAKE_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM.
974 MSR_SKYLAKE_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM.
975 MSR_SKYLAKE_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM.
976 MSR_SKYLAKE_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM.
977 MSR_SKYLAKE_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM.
978 MSR_SKYLAKE_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM.
979 MSR_SKYLAKE_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM.
980 MSR_SKYLAKE_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM.
981 MSR_SKYLAKE_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM.
982 MSR_SKYLAKE_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM.
983 MSR_SKYLAKE_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.
986 #define MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0
987 #define MSR_SKYLAKE_LASTBRANCH_17_TO_IP 0x000006D1
988 #define MSR_SKYLAKE_LASTBRANCH_18_TO_IP 0x000006D2
989 #define MSR_SKYLAKE_LASTBRANCH_19_TO_IP 0x000006D3
990 #define MSR_SKYLAKE_LASTBRANCH_20_TO_IP 0x000006D4
991 #define MSR_SKYLAKE_LASTBRANCH_21_TO_IP 0x000006D5
992 #define MSR_SKYLAKE_LASTBRANCH_22_TO_IP 0x000006D6
993 #define MSR_SKYLAKE_LASTBRANCH_23_TO_IP 0x000006D7
994 #define MSR_SKYLAKE_LASTBRANCH_24_TO_IP 0x000006D8
995 #define MSR_SKYLAKE_LASTBRANCH_25_TO_IP 0x000006D9
996 #define MSR_SKYLAKE_LASTBRANCH_26_TO_IP 0x000006DA
997 #define MSR_SKYLAKE_LASTBRANCH_27_TO_IP 0x000006DB
998 #define MSR_SKYLAKE_LASTBRANCH_28_TO_IP 0x000006DC
999 #define MSR_SKYLAKE_LASTBRANCH_29_TO_IP 0x000006DD
1000 #define MSR_SKYLAKE_LASTBRANCH_30_TO_IP 0x000006DE
1001 #define MSR_SKYLAKE_LASTBRANCH_31_TO_IP 0x000006DF
1006 Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet
1007 of last branch record registers on the last branch record stack. This part
1008 of the stack contains flag, TSX-related and elapsed cycle information. See
1009 also: - Last Branch Record Stack TOS at 1C9H - Section 17.6.1, "LBR
1012 @param ECX MSR_SKYLAKE_LBR_INFO_n
1013 @param EAX Lower 32-bits of MSR value.
1014 @param EDX Upper 32-bits of MSR value.
1016 <b>Example usage</b>
1020 Msr = AsmReadMsr64 (MSR_SKYLAKE_LBR_INFO_0);
1021 AsmWriteMsr64 (MSR_SKYLAKE_LBR_INFO_0, Msr);
1023 @note MSR_SKYLAKE_LBR_INFO_0 is defined as MSR_LBR_INFO_0 in SDM.
1024 MSR_SKYLAKE_LBR_INFO_1 is defined as MSR_LBR_INFO_1 in SDM.
1025 MSR_SKYLAKE_LBR_INFO_2 is defined as MSR_LBR_INFO_2 in SDM.
1026 MSR_SKYLAKE_LBR_INFO_3 is defined as MSR_LBR_INFO_3 in SDM.
1027 MSR_SKYLAKE_LBR_INFO_4 is defined as MSR_LBR_INFO_4 in SDM.
1028 MSR_SKYLAKE_LBR_INFO_5 is defined as MSR_LBR_INFO_5 in SDM.
1029 MSR_SKYLAKE_LBR_INFO_6 is defined as MSR_LBR_INFO_6 in SDM.
1030 MSR_SKYLAKE_LBR_INFO_7 is defined as MSR_LBR_INFO_7 in SDM.
1031 MSR_SKYLAKE_LBR_INFO_8 is defined as MSR_LBR_INFO_8 in SDM.
1032 MSR_SKYLAKE_LBR_INFO_9 is defined as MSR_LBR_INFO_9 in SDM.
1033 MSR_SKYLAKE_LBR_INFO_10 is defined as MSR_LBR_INFO_10 in SDM.
1034 MSR_SKYLAKE_LBR_INFO_11 is defined as MSR_LBR_INFO_11 in SDM.
1035 MSR_SKYLAKE_LBR_INFO_12 is defined as MSR_LBR_INFO_12 in SDM.
1036 MSR_SKYLAKE_LBR_INFO_13 is defined as MSR_LBR_INFO_13 in SDM.
1037 MSR_SKYLAKE_LBR_INFO_14 is defined as MSR_LBR_INFO_14 in SDM.
1038 MSR_SKYLAKE_LBR_INFO_15 is defined as MSR_LBR_INFO_15 in SDM.
1039 MSR_SKYLAKE_LBR_INFO_16 is defined as MSR_LBR_INFO_16 in SDM.
1040 MSR_SKYLAKE_LBR_INFO_17 is defined as MSR_LBR_INFO_17 in SDM.
1041 MSR_SKYLAKE_LBR_INFO_18 is defined as MSR_LBR_INFO_18 in SDM.
1042 MSR_SKYLAKE_LBR_INFO_19 is defined as MSR_LBR_INFO_19 in SDM.
1043 MSR_SKYLAKE_LBR_INFO_20 is defined as MSR_LBR_INFO_20 in SDM.
1044 MSR_SKYLAKE_LBR_INFO_21 is defined as MSR_LBR_INFO_21 in SDM.
1045 MSR_SKYLAKE_LBR_INFO_22 is defined as MSR_LBR_INFO_22 in SDM.
1046 MSR_SKYLAKE_LBR_INFO_23 is defined as MSR_LBR_INFO_23 in SDM.
1047 MSR_SKYLAKE_LBR_INFO_24 is defined as MSR_LBR_INFO_24 in SDM.
1048 MSR_SKYLAKE_LBR_INFO_25 is defined as MSR_LBR_INFO_25 in SDM.
1049 MSR_SKYLAKE_LBR_INFO_26 is defined as MSR_LBR_INFO_26 in SDM.
1050 MSR_SKYLAKE_LBR_INFO_27 is defined as MSR_LBR_INFO_27 in SDM.
1051 MSR_SKYLAKE_LBR_INFO_28 is defined as MSR_LBR_INFO_28 in SDM.
1052 MSR_SKYLAKE_LBR_INFO_29 is defined as MSR_LBR_INFO_29 in SDM.
1053 MSR_SKYLAKE_LBR_INFO_30 is defined as MSR_LBR_INFO_30 in SDM.
1054 MSR_SKYLAKE_LBR_INFO_31 is defined as MSR_LBR_INFO_31 in SDM.
1057 #define MSR_SKYLAKE_LBR_INFO_0 0x00000DC0
1058 #define MSR_SKYLAKE_LBR_INFO_1 0x00000DC1
1059 #define MSR_SKYLAKE_LBR_INFO_2 0x00000DC2
1060 #define MSR_SKYLAKE_LBR_INFO_3 0x00000DC3
1061 #define MSR_SKYLAKE_LBR_INFO_4 0x00000DC4
1062 #define MSR_SKYLAKE_LBR_INFO_5 0x00000DC5
1063 #define MSR_SKYLAKE_LBR_INFO_6 0x00000DC6
1064 #define MSR_SKYLAKE_LBR_INFO_7 0x00000DC7
1065 #define MSR_SKYLAKE_LBR_INFO_8 0x00000DC8
1066 #define MSR_SKYLAKE_LBR_INFO_9 0x00000DC9
1067 #define MSR_SKYLAKE_LBR_INFO_10 0x00000DCA
1068 #define MSR_SKYLAKE_LBR_INFO_11 0x00000DCB
1069 #define MSR_SKYLAKE_LBR_INFO_12 0x00000DCC
1070 #define MSR_SKYLAKE_LBR_INFO_13 0x00000DCD
1071 #define MSR_SKYLAKE_LBR_INFO_14 0x00000DCE
1072 #define MSR_SKYLAKE_LBR_INFO_15 0x00000DCF
1073 #define MSR_SKYLAKE_LBR_INFO_16 0x00000DD0
1074 #define MSR_SKYLAKE_LBR_INFO_17 0x00000DD1
1075 #define MSR_SKYLAKE_LBR_INFO_18 0x00000DD2
1076 #define MSR_SKYLAKE_LBR_INFO_19 0x00000DD3
1077 #define MSR_SKYLAKE_LBR_INFO_20 0x00000DD4
1078 #define MSR_SKYLAKE_LBR_INFO_21 0x00000DD5
1079 #define MSR_SKYLAKE_LBR_INFO_22 0x00000DD6
1080 #define MSR_SKYLAKE_LBR_INFO_23 0x00000DD7
1081 #define MSR_SKYLAKE_LBR_INFO_24 0x00000DD8
1082 #define MSR_SKYLAKE_LBR_INFO_25 0x00000DD9
1083 #define MSR_SKYLAKE_LBR_INFO_26 0x00000DDA
1084 #define MSR_SKYLAKE_LBR_INFO_27 0x00000DDB
1085 #define MSR_SKYLAKE_LBR_INFO_28 0x00000DDC
1086 #define MSR_SKYLAKE_LBR_INFO_29 0x00000DDD
1087 #define MSR_SKYLAKE_LBR_INFO_30 0x00000DDE
1088 #define MSR_SKYLAKE_LBR_INFO_31 0x00000DDF