2 MSR Definitions for Intel(R) Xeon(R) Processor D product Family.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-13.
24 #ifndef __XEON_D_MSR_H__
25 #define __XEON_D_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Package. Protected Processor Inventory Number Enable Control (R/W).
32 @param ECX MSR_XEON_D_PPIN_CTL (0x0000004E)
33 @param EAX Lower 32-bits of MSR value.
34 Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.
35 @param EDX Upper 32-bits of MSR value.
36 Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.
40 MSR_XEON_D_PPIN_CTL_REGISTER Msr;
42 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PPIN_CTL);
43 AsmWriteMsr64 (MSR_XEON_D_PPIN_CTL, Msr.Uint64);
46 #define MSR_XEON_D_PPIN_CTL 0x0000004E
49 MSR information returned for MSR index #MSR_XEON_D_PPIN_CTL
53 /// Individual bit fields
57 /// [Bit 0] LockOut (R/WO) See Table 35-21.
61 /// [Bit 1] Enable_PPIN (R/W) See Table 35-21.
68 /// All bit fields as a 32-bit value
72 /// All bit fields as a 64-bit value
75 } MSR_XEON_D_PPIN_CTL_REGISTER
;
79 Package. Protected Processor Inventory Number (R/O). Protected Processor
80 Inventory Number (R/O) See Table 35-21.
82 @param ECX MSR_XEON_D_PPIN (0x0000004F)
83 @param EAX Lower 32-bits of MSR value.
84 @param EDX Upper 32-bits of MSR value.
90 Msr = AsmReadMsr64 (MSR_XEON_D_PPIN);
93 #define MSR_XEON_D_PPIN 0x0000004F
97 Package. See http://biosbits.org.
99 @param ECX MSR_XEON_D_PLATFORM_INFO (0x000000CE)
100 @param EAX Lower 32-bits of MSR value.
101 Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.
102 @param EDX Upper 32-bits of MSR value.
103 Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.
107 MSR_XEON_D_PLATFORM_INFO_REGISTER Msr;
109 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PLATFORM_INFO);
110 AsmWriteMsr64 (MSR_XEON_D_PLATFORM_INFO, Msr.Uint64);
113 #define MSR_XEON_D_PLATFORM_INFO 0x000000CE
116 MSR information returned for MSR index #MSR_XEON_D_PLATFORM_INFO
120 /// Individual bit fields
125 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 35-21.
127 UINT32 MaximumNonTurboRatio
:8;
130 /// [Bit 23] Package. PPIN_CAP (R/O) See Table 35-21.
135 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See
140 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See
145 /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 35-21.
151 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 35-21.
153 UINT32 MaximumEfficiencyRatio
:8;
157 /// All bit fields as a 64-bit value
160 } MSR_XEON_D_PLATFORM_INFO_REGISTER
;
164 Core. C-State Configuration Control (R/W) Note: C-state values are processor
165 specific C-state code names, unrelated to MWAIT extension C-state parameters
166 or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
168 @param ECX MSR_XEON_D_PKG_CST_CONFIG_CONTROL (0x000000E2)
169 @param EAX Lower 32-bits of MSR value.
170 Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.
171 @param EDX Upper 32-bits of MSR value.
172 Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.
176 MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
178 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL);
179 AsmWriteMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
182 #define MSR_XEON_D_PKG_CST_CONFIG_CONTROL 0x000000E2
185 MSR information returned for MSR index #MSR_XEON_D_PKG_CST_CONFIG_CONTROL
189 /// Individual bit fields
193 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
194 /// processor-specific C-state code name (consuming the least power) for
195 /// the package. The default is set as factory-configured package C-state
196 /// limit. The following C-state code name encodings are supported: 000b:
197 /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)
198 /// 011b: C6 (retention) 111b: No Package C state limits. All C states
199 /// supported by the processor are available.
204 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
209 /// [Bit 15] CFG Lock (R/WO).
213 /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor
214 /// will convert HALT or MWAT(C1) to MWAIT(C6).
216 UINT32 CStateConversion
:1;
219 /// [Bit 25] C3 State Auto Demotion Enable (R/W).
221 UINT32 C3AutoDemotion
:1;
223 /// [Bit 26] C1 State Auto Demotion Enable (R/W).
225 UINT32 C1AutoDemotion
:1;
227 /// [Bit 27] Enable C3 Undemotion (R/W).
229 UINT32 C3Undemotion
:1;
231 /// [Bit 28] Enable C1 Undemotion (R/W).
233 UINT32 C1Undemotion
:1;
235 /// [Bit 29] Package C State Demotion Enable (R/W).
237 UINT32 CStateDemotion
:1;
239 /// [Bit 30] Package C State UnDemotion Enable (R/W).
241 UINT32 CStateUndemotion
:1;
246 /// All bit fields as a 32-bit value
250 /// All bit fields as a 64-bit value
253 } MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER
;
257 Thread. Global Machine Check Capability (R/O).
259 @param ECX MSR_XEON_D_IA32_MCG_CAP (0x00000179)
260 @param EAX Lower 32-bits of MSR value.
261 Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.
262 @param EDX Upper 32-bits of MSR value.
263 Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.
267 MSR_XEON_D_IA32_MCG_CAP_REGISTER Msr;
269 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_MCG_CAP);
272 #define MSR_XEON_D_IA32_MCG_CAP 0x00000179
275 MSR information returned for MSR index #MSR_XEON_D_IA32_MCG_CAP
279 /// Individual bit fields
283 /// [Bits 7:0] Count.
287 /// [Bit 8] MCG_CTL_P.
291 /// [Bit 9] MCG_EXT_P.
295 /// [Bit 10] MCP_CMCI_P.
299 /// [Bit 11] MCG_TES_P.
304 /// [Bits 23:16] MCG_EXT_CNT.
306 UINT32 MCG_EXT_CNT
:8;
308 /// [Bit 24] MCG_SER_P.
312 /// [Bit 25] MCG_EM_P.
316 /// [Bit 26] MCG_ELOG_P.
323 /// All bit fields as a 32-bit value
327 /// All bit fields as a 64-bit value
330 } MSR_XEON_D_IA32_MCG_CAP_REGISTER
;
334 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
335 Enhancement. Accessible only while in SMM.
337 @param ECX MSR_XEON_D_SMM_MCA_CAP (0x0000017D)
338 @param EAX Lower 32-bits of MSR value.
339 Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.
340 @param EDX Upper 32-bits of MSR value.
341 Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.
345 MSR_XEON_D_SMM_MCA_CAP_REGISTER Msr;
347 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_SMM_MCA_CAP);
348 AsmWriteMsr64 (MSR_XEON_D_SMM_MCA_CAP, Msr.Uint64);
351 #define MSR_XEON_D_SMM_MCA_CAP 0x0000017D
354 MSR information returned for MSR index #MSR_XEON_D_SMM_MCA_CAP
358 /// Individual bit fields
364 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
365 /// SMM code access restriction is supported and a host-space interface
366 /// available to SMM handler.
368 UINT32 SMM_Code_Access_Chk
:1;
370 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
371 /// SMM long flow indicator is supported and a host-space interface
372 /// available to SMM handler.
374 UINT32 Long_Flow_Indication
:1;
378 /// All bit fields as a 64-bit value
381 } MSR_XEON_D_SMM_MCA_CAP_REGISTER
;
387 @param ECX MSR_XEON_D_TEMPERATURE_TARGET (0x000001A2)
388 @param EAX Lower 32-bits of MSR value.
389 Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.
390 @param EDX Upper 32-bits of MSR value.
391 Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.
395 MSR_XEON_D_TEMPERATURE_TARGET_REGISTER Msr;
397 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TEMPERATURE_TARGET);
398 AsmWriteMsr64 (MSR_XEON_D_TEMPERATURE_TARGET, Msr.Uint64);
401 #define MSR_XEON_D_TEMPERATURE_TARGET 0x000001A2
404 MSR information returned for MSR index #MSR_XEON_D_TEMPERATURE_TARGET
408 /// Individual bit fields
413 /// [Bits 23:16] Temperature Target (RO) See Table 35-21.
415 UINT32 TemperatureTarget
:8;
417 /// [Bits 27:24] TCC Activation Offset (R/W) See Table 35-21.
419 UINT32 TCCActivationOffset
:4;
424 /// All bit fields as a 32-bit value
428 /// All bit fields as a 64-bit value
431 } MSR_XEON_D_TEMPERATURE_TARGET_REGISTER
;
435 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
436 RW if MSR_PLATFORM_INFO.[28] = 1.
438 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT (0x000001AD)
439 @param EAX Lower 32-bits of MSR value.
440 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.
441 @param EDX Upper 32-bits of MSR value.
442 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.
446 MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER Msr;
448 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT);
451 #define MSR_XEON_D_TURBO_RATIO_LIMIT 0x000001AD
454 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT
458 /// Individual bit fields
462 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C.
466 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C.
470 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C.
474 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C.
478 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C.
482 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C.
486 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C.
490 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C.
495 /// All bit fields as a 64-bit value
498 } MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
;
502 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
503 RW if MSR_PLATFORM_INFO.[28] = 1.
505 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT1 (0x000001AE)
506 @param EAX Lower 32-bits of MSR value.
507 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.
508 @param EDX Upper 32-bits of MSR value.
509 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.
513 MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER Msr;
515 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT1);
518 #define MSR_XEON_D_TURBO_RATIO_LIMIT1 0x000001AE
521 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT1
525 /// Individual bit fields
529 /// [Bits 7:0] Package. Maximum Ratio Limit for 9C.
533 /// [Bits 15:8] Package. Maximum Ratio Limit for 10C.
537 /// [Bits 23:16] Package. Maximum Ratio Limit for 11C.
541 /// [Bits 31:24] Package. Maximum Ratio Limit for 12C.
545 /// [Bits 39:32] Package. Maximum Ratio Limit for 13C.
549 /// [Bits 47:40] Package. Maximum Ratio Limit for 14C.
553 /// [Bits 55:48] Package. Maximum Ratio Limit for 15C.
557 /// [Bits 63:56] Package. Maximum Ratio Limit for 16C.
562 /// All bit fields as a 64-bit value
565 } MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
;
569 Package. Unit Multipliers used in RAPL Interfaces (R/O).
571 @param ECX MSR_XEON_D_RAPL_POWER_UNIT (0x00000606)
572 @param EAX Lower 32-bits of MSR value.
573 Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.
574 @param EDX Upper 32-bits of MSR value.
575 Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.
579 MSR_XEON_D_RAPL_POWER_UNIT_REGISTER Msr;
581 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_RAPL_POWER_UNIT);
584 #define MSR_XEON_D_RAPL_POWER_UNIT 0x00000606
587 MSR information returned for MSR index #MSR_XEON_D_RAPL_POWER_UNIT
591 /// Individual bit fields
595 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
600 /// [Bits 12:8] Package. Energy Status Units Energy related information
601 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
602 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
605 UINT32 EnergyStatusUnits
:5;
608 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
616 /// All bit fields as a 32-bit value
620 /// All bit fields as a 64-bit value
623 } MSR_XEON_D_RAPL_POWER_UNIT_REGISTER
;
627 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
630 @param ECX MSR_XEON_D_DRAM_POWER_LIMIT (0x00000618)
631 @param EAX Lower 32-bits of MSR value.
632 @param EDX Upper 32-bits of MSR value.
638 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT);
639 AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT, Msr);
642 #define MSR_XEON_D_DRAM_POWER_LIMIT 0x00000618
646 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
648 @param ECX MSR_XEON_D_DRAM_ENERGY_STATUS (0x00000619)
649 @param EAX Lower 32-bits of MSR value.
650 @param EDX Upper 32-bits of MSR value.
656 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS);
659 #define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619
663 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
666 @param ECX MSR_XEON_D_DRAM_PERF_STATUS (0x0000061B)
667 @param EAX Lower 32-bits of MSR value.
668 @param EDX Upper 32-bits of MSR value.
674 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_PERF_STATUS);
677 #define MSR_XEON_D_DRAM_PERF_STATUS 0x0000061B
681 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
683 @param ECX MSR_XEON_D_DRAM_POWER_INFO (0x0000061C)
684 @param EAX Lower 32-bits of MSR value.
685 @param EDX Upper 32-bits of MSR value.
691 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_INFO);
692 AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_INFO, Msr);
695 #define MSR_XEON_D_DRAM_POWER_INFO 0x0000061C
699 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
700 refers to processor core frequency).
702 @param ECX MSR_XEON_D_CORE_PERF_LIMIT_REASONS (0x00000690)
703 @param EAX Lower 32-bits of MSR value.
704 Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.
705 @param EDX Upper 32-bits of MSR value.
706 Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.
710 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
712 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS);
713 AsmWriteMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
716 #define MSR_XEON_D_CORE_PERF_LIMIT_REASONS 0x00000690
719 MSR information returned for MSR index #MSR_XEON_D_CORE_PERF_LIMIT_REASONS
723 /// Individual bit fields
727 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
728 /// reduced below the operating system request due to assertion of
729 /// external PROCHOT.
731 UINT32 PROCHOT_Status
:1;
733 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
734 /// operating system request due to a thermal event.
736 UINT32 ThermalStatus
:1;
738 /// [Bit 2] Power Budget Management Status (R0) When set, frequency is
739 /// reduced below the operating system request due to PBM limit.
741 UINT32 PowerBudgetManagementStatus
:1;
743 /// [Bit 3] Platform Configuration Services Status (R0) When set,
744 /// frequency is reduced below the operating system request due to PCS
747 UINT32 PlatformConfigurationServicesStatus
:1;
750 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
751 /// When set, frequency is reduced below the operating system request
752 /// because the processor has detected that utilization is low.
754 UINT32 AutonomousUtilizationBasedFrequencyControlStatus
:1;
756 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
757 /// below the operating system request due to a thermal alert from the
758 /// Voltage Regulator.
760 UINT32 VRThermAlertStatus
:1;
763 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
764 /// reduced below the operating system request due to electrical design
765 /// point constraints (e.g. maximum electrical current consumption).
767 UINT32 ElectricalDesignPointStatus
:1;
770 /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced
771 /// below the operating system request due to Multi-Core Turbo limits.
773 UINT32 MultiCoreTurboStatus
:1;
776 /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced
777 /// below max non-turbo P1.
779 UINT32 FrequencyP1Status
:1;
781 /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When
782 /// set, frequency is reduced below max n-core turbo frequency.
784 UINT32 TurboFrequencyLimitingStatus
:1;
786 /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is
787 /// reduced below the operating system request.
789 UINT32 FrequencyLimitingStatus
:1;
791 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
792 /// has asserted since the log bit was last cleared. This log bit will
793 /// remain set until cleared by software writing 0.
795 UINT32 PROCHOT_Log
:1;
797 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
798 /// has asserted since the log bit was last cleared. This log bit will
799 /// remain set until cleared by software writing 0.
803 /// [Bit 18] Power Budget Management Log When set, indicates that the PBM
804 /// Status bit has asserted since the log bit was last cleared. This log
805 /// bit will remain set until cleared by software writing 0.
807 UINT32 PowerBudgetManagementLog
:1;
809 /// [Bit 19] Platform Configuration Services Log When set, indicates that
810 /// the PCS Status bit has asserted since the log bit was last cleared.
811 /// This log bit will remain set until cleared by software writing 0.
813 UINT32 PlatformConfigurationServicesLog
:1;
816 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
817 /// indicates that the AUBFC Status bit has asserted since the log bit was
818 /// last cleared. This log bit will remain set until cleared by software
821 UINT32 AutonomousUtilizationBasedFrequencyControlLog
:1;
823 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
824 /// Alert Status bit has asserted since the log bit was last cleared. This
825 /// log bit will remain set until cleared by software writing 0.
827 UINT32 VRThermAlertLog
:1;
830 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
831 /// Status bit has asserted since the log bit was last cleared. This log
832 /// bit will remain set until cleared by software writing 0.
834 UINT32 ElectricalDesignPointLog
:1;
837 /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core
838 /// Turbo Status bit has asserted since the log bit was last cleared. This
839 /// log bit will remain set until cleared by software writing 0.
841 UINT32 MultiCoreTurboLog
:1;
844 /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core
845 /// Frequency P1 Status bit has asserted since the log bit was last
846 /// cleared. This log bit will remain set until cleared by software
849 UINT32 CoreFrequencyP1Log
:1;
851 /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,
852 /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit
853 /// has asserted since the log bit was last cleared. This log bit will
854 /// remain set until cleared by software writing 0.
856 UINT32 TurboFrequencyLimitingLog
:1;
858 /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core
859 /// Frequency Limiting Status bit has asserted since the log bit was last
860 /// cleared. This log bit will remain set until cleared by software
863 UINT32 CoreFrequencyLimitingLog
:1;
867 /// All bit fields as a 32-bit value
871 /// All bit fields as a 64-bit value
874 } MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
;
878 THREAD. Monitoring Event Select Register (R/W) if CPUID.(EAX=07H,
879 ECX=0):EBX.PQM[bit 12] = 1.
881 @param ECX MSR_XEON_D_IA32_QM_EVTSEL (0x00000C8D)
882 @param EAX Lower 32-bits of MSR value.
883 Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.
884 @param EDX Upper 32-bits of MSR value.
885 Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.
889 MSR_XEON_D_IA32_QM_EVTSEL_REGISTER Msr;
891 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_QM_EVTSEL);
892 AsmWriteMsr64 (MSR_XEON_D_IA32_QM_EVTSEL, Msr.Uint64);
895 #define MSR_XEON_D_IA32_QM_EVTSEL 0x00000C8D
898 MSR information returned for MSR index #MSR_XEON_D_IA32_QM_EVTSEL
902 /// Individual bit fields
906 /// [Bits 7:0] EventID (RW) Event encoding: 0x00: no monitoring 0x01: L3
907 /// occupancy monitoring 0x02: Total memory bandwidth monitoring 0x03:
908 /// Local memory bandwidth monitoring All other encoding reserved.
913 /// [Bits 41:32] RMID (RW).
919 /// All bit fields as a 64-bit value
922 } MSR_XEON_D_IA32_QM_EVTSEL_REGISTER
;
926 THREAD. Resource Association Register (R/W).
928 @param ECX MSR_XEON_D_IA32_PQR_ASSOC (0x00000C8F)
929 @param EAX Lower 32-bits of MSR value.
930 Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.
931 @param EDX Upper 32-bits of MSR value.
932 Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.
936 MSR_XEON_D_IA32_PQR_ASSOC_REGISTER Msr;
938 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_PQR_ASSOC);
939 AsmWriteMsr64 (MSR_XEON_D_IA32_PQR_ASSOC, Msr.Uint64);
942 #define MSR_XEON_D_IA32_PQR_ASSOC 0x00000C8F
945 MSR information returned for MSR index #MSR_XEON_D_IA32_PQR_ASSOC
949 /// Individual bit fields
958 /// [Bits 51:32] COS (R/W).
964 /// All bit fields as a 64-bit value
967 } MSR_XEON_D_IA32_PQR_ASSOC_REGISTER
;
971 Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,
972 ECX=1):EDX.COS_MAX[15:0] >= n.
974 @param ECX MSR_XEON_D_IA32_L3_QOS_MASK_n
975 @param EAX Lower 32-bits of MSR value.
976 Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
977 @param EDX Upper 32-bits of MSR value.
978 Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
982 MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;
984 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);
985 AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);
989 #define MSR_XEON_D_IA32_L3_QOS_MASK_0 0x00000C90
990 #define MSR_XEON_D_IA32_L3_QOS_MASK_1 0x00000C91
991 #define MSR_XEON_D_IA32_L3_QOS_MASK_2 0x00000C92
992 #define MSR_XEON_D_IA32_L3_QOS_MASK_3 0x00000C93
993 #define MSR_XEON_D_IA32_L3_QOS_MASK_4 0x00000C94
994 #define MSR_XEON_D_IA32_L3_QOS_MASK_5 0x00000C95
995 #define MSR_XEON_D_IA32_L3_QOS_MASK_6 0x00000C96
996 #define MSR_XEON_D_IA32_L3_QOS_MASK_7 0x00000C97
997 #define MSR_XEON_D_IA32_L3_QOS_MASK_8 0x00000C98
998 #define MSR_XEON_D_IA32_L3_QOS_MASK_9 0x00000C99
999 #define MSR_XEON_D_IA32_L3_QOS_MASK_10 0x00000C9A
1000 #define MSR_XEON_D_IA32_L3_QOS_MASK_11 0x00000C9B
1001 #define MSR_XEON_D_IA32_L3_QOS_MASK_12 0x00000C9C
1002 #define MSR_XEON_D_IA32_L3_QOS_MASK_13 0x00000C9D
1003 #define MSR_XEON_D_IA32_L3_QOS_MASK_14 0x00000C9E
1004 #define MSR_XEON_D_IA32_L3_QOS_MASK_15 0x00000C9F
1008 MSR information returned for MSR indexes #MSR_XEON_D_IA32_L3_QOS_MASK_0
1009 to #MSR_XEON_D_IA32_L3_QOS_MASK_15.
1013 /// Individual bit fields
1017 /// [Bits 19:0] CBM: Bit vector of available L3 ways for COS 0 enforcement.
1020 UINT32 Reserved2
:12;
1021 UINT32 Reserved3
:32;
1024 /// All bit fields as a 32-bit value
1028 /// All bit fields as a 64-bit value
1031 } MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER
;
1035 Package. Config Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
1036 RW if MSR_PLATFORM_INFO.[28] = 1.
1038 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT3 (0x000001AC)
1039 @param EAX Lower 32-bits of MSR value.
1040 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.
1041 @param EDX Upper 32-bits of MSR value.
1042 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.
1044 <b>Example usage</b>
1046 MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER Msr;
1048 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT3);
1051 #define MSR_XEON_D_TURBO_RATIO_LIMIT3 0x000001AC
1054 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT3
1058 /// Individual bit fields
1061 UINT32 Reserved1
:32;
1062 UINT32 Reserved2
:31;
1064 /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
1065 /// the processor uses override configuration specified in
1066 /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1. If 0, the processor
1067 /// uses factory-set configuration (Default).
1069 UINT32 TurboRatioLimitConfigurationSemaphore
:1;
1072 /// All bit fields as a 64-bit value
1075 } MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER
;
1079 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
1080 15.3.2.4, "IA32_MCi_MISC MSRs.".
1082 * Bank MC5 reports MC error from the Intel QPI 0 module.
1083 * Bank MC6 reports MC error from the integrated I/O module.
1084 * Bank MC7 reports MC error from the home agent HA 0.
1085 * Bank MC8 reports MC error from the home agent HA 1.
1086 * Banks MC9 through MC16 report MC error from each channel of the integrated
1088 * Bank MC17 reports MC error from the following pair of CBo/L3 Slices
1089 (if the pair is present): CBo0, CBo3, CBo6, CBo9, CBo12, CBo15.
1090 * Bank MC18 reports MC error from the following pair of CBo/L3 Slices
1091 (if the pair is present): CBo1, CBo4, CBo7, CBo10, CBo13, CBo16.
1092 * Bank MC19 reports MC error from the following pair of CBo/L3 Slices
1093 (if the pair is present): CBo2, CBo5, CBo8, CBo11, CBo14, CBo17.
1094 * Bank MC20 reports MC error from the Intel QPI 1 module.
1095 * Bank MC21 reports MC error from the Intel QPI 2 module.
1097 @param ECX MSR_XEON_D_MCi_CTL
1098 @param EAX Lower 32-bits of MSR value.
1099 @param EDX Upper 32-bits of MSR value.
1101 <b>Example usage</b>
1105 Msr = AsmReadMsr64 (MSR_XEON_D_MC5_CTL);
1106 AsmWriteMsr64 (MSR_XEON_D_MC5_CTL, Msr);
1110 #define MSR_XEON_D_MC5_CTL 0x00000414
1111 #define MSR_XEON_D_MC6_CTL 0x00000418
1112 #define MSR_XEON_D_MC7_CTL 0x0000041C
1113 #define MSR_XEON_D_MC8_CTL 0x00000420
1114 #define MSR_XEON_D_MC9_CTL 0x00000424
1115 #define MSR_XEON_D_MC10_CTL 0x00000428
1116 #define MSR_XEON_D_MC11_CTL 0x0000042C
1117 #define MSR_XEON_D_MC12_CTL 0x00000430
1118 #define MSR_XEON_D_MC13_CTL 0x00000434
1119 #define MSR_XEON_D_MC14_CTL 0x00000438
1120 #define MSR_XEON_D_MC15_CTL 0x0000043C
1121 #define MSR_XEON_D_MC16_CTL 0x00000440
1122 #define MSR_XEON_D_MC17_CTL 0x00000444
1123 #define MSR_XEON_D_MC18_CTL 0x00000448
1124 #define MSR_XEON_D_MC19_CTL 0x0000044C
1125 #define MSR_XEON_D_MC20_CTL 0x00000450
1126 #define MSR_XEON_D_MC21_CTL 0x00000454
1130 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
1131 15.3.2.4, "IA32_MCi_MISC MSRs.".
1133 @param ECX MSR_XEON_D_MCi_STATUS
1134 @param EAX Lower 32-bits of MSR value.
1135 @param EDX Upper 32-bits of MSR value.
1137 <b>Example usage</b>
1141 Msr = AsmReadMsr64 (MSR_XEON_D_MC6_STATUS);
1142 AsmWriteMsr64 (MSR_XEON_D_MC6_STATUS, Msr);
1146 #define MSR_XEON_D_MC5_STATUS 0x00000415
1147 #define MSR_XEON_D_MC6_STATUS 0x00000419
1148 #define MSR_XEON_D_MC7_STATUS 0x0000041D
1149 #define MSR_XEON_D_MC8_STATUS 0x00000421
1150 #define MSR_XEON_D_MC9_STATUS 0x00000425
1151 #define MSR_XEON_D_MC10_STATUS 0x00000429
1152 #define MSR_XEON_D_MC11_STATUS 0x0000042D
1153 #define MSR_XEON_D_MC12_STATUS 0x00000431
1154 #define MSR_XEON_D_MC13_STATUS 0x00000435
1155 #define MSR_XEON_D_MC14_STATUS 0x00000439
1156 #define MSR_XEON_D_MC15_STATUS 0x0000043D
1157 #define MSR_XEON_D_MC16_STATUS 0x00000441
1158 #define MSR_XEON_D_MC17_STATUS 0x00000445
1159 #define MSR_XEON_D_MC18_STATUS 0x00000449
1160 #define MSR_XEON_D_MC19_STATUS 0x0000044D
1161 #define MSR_XEON_D_MC20_STATUS 0x00000451
1162 #define MSR_XEON_D_MC21_STATUS 0x00000455
1166 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
1167 15.3.2.4, "IA32_MCi_MISC MSRs.".
1169 @param ECX MSR_XEON_D_MCi_ADDR
1170 @param EAX Lower 32-bits of MSR value.
1171 @param EDX Upper 32-bits of MSR value.
1173 <b>Example usage</b>
1177 Msr = AsmReadMsr64 (MSR_XEON_D_MC6_ADDR);
1178 AsmWriteMsr64 (MSR_XEON_D_MC6_ADDR, Msr);
1182 #define MSR_XEON_D_MC5_ADDR 0x00000416
1183 #define MSR_XEON_D_MC6_ADDR 0x0000041A
1184 #define MSR_XEON_D_MC7_ADDR 0x0000041E
1185 #define MSR_XEON_D_MC8_ADDR 0x00000422
1186 #define MSR_XEON_D_MC9_ADDR 0x00000426
1187 #define MSR_XEON_D_MC10_ADDR 0x0000042A
1188 #define MSR_XEON_D_MC11_ADDR 0x0000042E
1189 #define MSR_XEON_D_MC12_ADDR 0x00000432
1190 #define MSR_XEON_D_MC13_ADDR 0x00000436
1191 #define MSR_XEON_D_MC14_ADDR 0x0000043A
1192 #define MSR_XEON_D_MC15_ADDR 0x0000043E
1193 #define MSR_XEON_D_MC16_ADDR 0x00000442
1194 #define MSR_XEON_D_MC17_ADDR 0x00000446
1195 #define MSR_XEON_D_MC18_ADDR 0x0000044A
1196 #define MSR_XEON_D_MC19_ADDR 0x0000044E
1197 #define MSR_XEON_D_MC20_ADDR 0x00000452
1198 #define MSR_XEON_D_MC21_ADDR 0x00000456
1203 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
1204 15.3.2.4, "IA32_MCi_MISC MSRs.".
1206 @param ECX MSR_XEON_D_MCi_MISC
1207 @param EAX Lower 32-bits of MSR value.
1208 @param EDX Upper 32-bits of MSR value.
1210 <b>Example usage</b>
1214 Msr = AsmReadMsr64 (MSR_XEON_D_MC6_MISC);
1215 AsmWriteMsr64 (MSR_XEON_D_MC6_MISC, Msr);
1219 #define MSR_XEON_D_MC5_MISC 0x00000417
1220 #define MSR_XEON_D_MC6_MISC 0x0000041B
1221 #define MSR_XEON_D_MC7_MISC 0x0000041F
1222 #define MSR_XEON_D_MC8_MISC 0x00000423
1223 #define MSR_XEON_D_MC9_MISC 0x00000427
1224 #define MSR_XEON_D_MC10_MISC 0x0000042B
1225 #define MSR_XEON_D_MC11_MISC 0x0000042F
1226 #define MSR_XEON_D_MC12_MISC 0x00000433
1227 #define MSR_XEON_D_MC13_MISC 0x00000437
1228 #define MSR_XEON_D_MC14_MISC 0x0000043B
1229 #define MSR_XEON_D_MC15_MISC 0x0000043F
1230 #define MSR_XEON_D_MC16_MISC 0x00000443
1231 #define MSR_XEON_D_MC17_MISC 0x00000447
1232 #define MSR_XEON_D_MC18_MISC 0x0000044B
1233 #define MSR_XEON_D_MC19_MISC 0x0000044F
1234 #define MSR_XEON_D_MC20_MISC 0x00000453
1235 #define MSR_XEON_D_MC21_MISC 0x00000457
1240 Package. Note: C-state values are processor specific C-state code names,
1241 unrelated to MWAIT extension C-state parameters or ACPI C-States.
1243 @param ECX MSR_XEON_D_PKG_C8_RESIDENCY (0x00000630)
1244 @param EAX Lower 32-bits of MSR value.
1245 Described by the type MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER.
1246 @param EDX Upper 32-bits of MSR value.
1247 Described by the type MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER.
1249 <b>Example usage</b>
1251 MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER Msr;
1253 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C8_RESIDENCY);
1254 AsmWriteMsr64 (MSR_XEON_D_PKG_C8_RESIDENCY, Msr.Uint64);
1257 #define MSR_XEON_D_PKG_C8_RESIDENCY 0x00000630
1260 MSR information returned for MSR index #MSR_XEON_D_PKG_C8_RESIDENCY
1264 /// Individual bit fields
1268 /// [Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset
1269 /// that this package is in processor-specific C8 states. Count at the
1270 /// same frequency as the TSC.
1272 UINT32 C8ResidencyCounter
:32;
1274 /// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last
1275 /// reset that this package is in processor-specific C8 states. Count at
1276 /// the same frequency as the TSC.
1278 UINT32 C8ResidencyCounterHi
:28;
1282 /// All bit fields as a 64-bit value
1285 } MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER
;
1289 Package. Note: C-state values are processor specific C-state code names,
1290 unrelated to MWAIT extension C-state parameters or ACPI C-States.
1292 @param ECX MSR_XEON_D_PKG_C9_RESIDENCY (0x00000631)
1293 @param EAX Lower 32-bits of MSR value.
1294 Described by the type MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER.
1295 @param EDX Upper 32-bits of MSR value.
1296 Described by the type MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER.
1298 <b>Example usage</b>
1300 MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER Msr;
1302 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C9_RESIDENCY);
1303 AsmWriteMsr64 (MSR_XEON_D_PKG_C9_RESIDENCY, Msr.Uint64);
1306 #define MSR_XEON_D_PKG_C9_RESIDENCY 0x00000631
1309 MSR information returned for MSR index #MSR_XEON_D_PKG_C9_RESIDENCY
1313 /// Individual bit fields
1317 /// [Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset
1318 /// that this package is in processor-specific C9 states. Count at the
1319 /// same frequency as the TSC.
1321 UINT32 C9ResidencyCounter
:32;
1323 /// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last
1324 /// reset that this package is in processor-specific C9 states. Count at
1325 /// the same frequency as the TSC.
1327 UINT32 C9ResidencyCounterHi
:28;
1331 /// All bit fields as a 64-bit value
1334 } MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER
;
1338 Package. Note: C-state values are processor specific C-state code names,
1339 unrelated to MWAIT extension C-state parameters or ACPI C-States.
1341 @param ECX MSR_XEON_D_PKG_C10_RESIDENCY (0x00000632)
1342 @param EAX Lower 32-bits of MSR value.
1343 Described by the type MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER.
1344 @param EDX Upper 32-bits of MSR value.
1345 Described by the type MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER.
1347 <b>Example usage</b>
1349 MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER Msr;
1351 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C10_RESIDENCY);
1352 AsmWriteMsr64 (MSR_XEON_D_PKG_C10_RESIDENCY, Msr.Uint64);
1355 #define MSR_XEON_D_PKG_C10_RESIDENCY 0x00000632
1358 MSR information returned for MSR index #MSR_XEON_D_PKG_C10_RESIDENCY
1362 /// Individual bit fields
1366 /// [Bits 31:0] Package C10 Residency Counter. (R/O) Value since last
1367 /// reset that this package is in processor-specific C10 states. Count at
1368 /// the same frequency as the TSC.
1370 UINT32 C10ResidencyCounter
:32;
1372 /// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last
1373 /// reset that this package is in processor-specific C10 states. Count at
1374 /// the same frequency as the TSC.
1376 UINT32 C10ResidencyCounterHi
:28;
1380 /// All bit fields as a 64-bit value
1383 } MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER
;
1387 Package. Cache Allocation Technology Configuration (R/W).
1389 @param ECX MSR_XEON_D_IA32_L3_QOS_CFG (0x00000C81)
1390 @param EAX Lower 32-bits of MSR value.
1391 Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.
1392 @param EDX Upper 32-bits of MSR value.
1393 Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.
1395 <b>Example usage</b>
1397 MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER Msr;
1399 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG);
1400 AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG, Msr.Uint64);
1403 #define MSR_XEON_D_IA32_L3_QOS_CFG 0x00000C81
1406 MSR information returned for MSR index #MSR_XEON_D_IA32_L3_QOS_CFG
1410 /// Individual bit fields
1414 /// [Bit 0] CAT Enable. Set 1 to enable Cache Allocation Technology.
1417 UINT32 Reserved1
:31;
1418 UINT32 Reserved2
:32;
1421 /// All bit fields as a 32-bit value
1425 /// All bit fields as a 64-bit value
1428 } MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER
;