2 MSR Definitions for Intel(R) Xeon(R) Processor D product Family.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
20 May 2018, Volume 4: Model-Specific-Registers (MSR)
24 #ifndef __XEON_D_MSR_H__
25 #define __XEON_D_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Is Intel(R) Xeon(R) Processor D product Family?
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
38 #define IS_XEON_D_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
41 DisplayModel == 0x4F || \
42 DisplayModel == 0x56 \
47 Package. Protected Processor Inventory Number Enable Control (R/W).
49 @param ECX MSR_XEON_D_PPIN_CTL (0x0000004E)
50 @param EAX Lower 32-bits of MSR value.
51 Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.
52 @param EDX Upper 32-bits of MSR value.
53 Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.
57 MSR_XEON_D_PPIN_CTL_REGISTER Msr;
59 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PPIN_CTL);
60 AsmWriteMsr64 (MSR_XEON_D_PPIN_CTL, Msr.Uint64);
62 @note MSR_XEON_D_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.
64 #define MSR_XEON_D_PPIN_CTL 0x0000004E
67 MSR information returned for MSR index #MSR_XEON_D_PPIN_CTL
71 /// Individual bit fields
75 /// [Bit 0] LockOut (R/WO) See Table 2-25.
79 /// [Bit 1] Enable_PPIN (R/W) See Table 2-25.
86 /// All bit fields as a 32-bit value
90 /// All bit fields as a 64-bit value
93 } MSR_XEON_D_PPIN_CTL_REGISTER
;
97 Package. Protected Processor Inventory Number (R/O). Protected Processor
98 Inventory Number (R/O) See Table 2-25.
100 @param ECX MSR_XEON_D_PPIN (0x0000004F)
101 @param EAX Lower 32-bits of MSR value.
102 @param EDX Upper 32-bits of MSR value.
108 Msr = AsmReadMsr64 (MSR_XEON_D_PPIN);
110 @note MSR_XEON_D_PPIN is defined as MSR_PPIN in SDM.
112 #define MSR_XEON_D_PPIN 0x0000004F
116 Package. See http://biosbits.org.
118 @param ECX MSR_XEON_D_PLATFORM_INFO (0x000000CE)
119 @param EAX Lower 32-bits of MSR value.
120 Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.
121 @param EDX Upper 32-bits of MSR value.
122 Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.
126 MSR_XEON_D_PLATFORM_INFO_REGISTER Msr;
128 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PLATFORM_INFO);
129 AsmWriteMsr64 (MSR_XEON_D_PLATFORM_INFO, Msr.Uint64);
131 @note MSR_XEON_D_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
133 #define MSR_XEON_D_PLATFORM_INFO 0x000000CE
136 MSR information returned for MSR index #MSR_XEON_D_PLATFORM_INFO
140 /// Individual bit fields
145 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.
147 UINT32 MaximumNonTurboRatio
:8;
150 /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.
155 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See
160 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See
165 /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.
171 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.
173 UINT32 MaximumEfficiencyRatio
:8;
177 /// All bit fields as a 64-bit value
180 } MSR_XEON_D_PLATFORM_INFO_REGISTER
;
184 Core. C-State Configuration Control (R/W) Note: C-state values are processor
185 specific C-state code names, unrelated to MWAIT extension C-state parameters
186 or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
188 @param ECX MSR_XEON_D_PKG_CST_CONFIG_CONTROL (0x000000E2)
189 @param EAX Lower 32-bits of MSR value.
190 Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.
191 @param EDX Upper 32-bits of MSR value.
192 Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.
196 MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
198 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL);
199 AsmWriteMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
201 @note MSR_XEON_D_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
203 #define MSR_XEON_D_PKG_CST_CONFIG_CONTROL 0x000000E2
206 MSR information returned for MSR index #MSR_XEON_D_PKG_CST_CONFIG_CONTROL
210 /// Individual bit fields
214 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
215 /// processor-specific C-state code name (consuming the least power) for
216 /// the package. The default is set as factory-configured package C-state
217 /// limit. The following C-state code name encodings are supported: 000b:
218 /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)
219 /// 011b: C6 (retention) 111b: No Package C state limits. All C states
220 /// supported by the processor are available.
225 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
230 /// [Bit 15] CFG Lock (R/WO).
234 /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor
235 /// will convert HALT or MWAT(C1) to MWAIT(C6).
237 UINT32 CStateConversion
:1;
240 /// [Bit 25] C3 State Auto Demotion Enable (R/W).
242 UINT32 C3AutoDemotion
:1;
244 /// [Bit 26] C1 State Auto Demotion Enable (R/W).
246 UINT32 C1AutoDemotion
:1;
248 /// [Bit 27] Enable C3 Undemotion (R/W).
250 UINT32 C3Undemotion
:1;
252 /// [Bit 28] Enable C1 Undemotion (R/W).
254 UINT32 C1Undemotion
:1;
256 /// [Bit 29] Package C State Demotion Enable (R/W).
258 UINT32 CStateDemotion
:1;
260 /// [Bit 30] Package C State UnDemotion Enable (R/W).
262 UINT32 CStateUndemotion
:1;
267 /// All bit fields as a 32-bit value
271 /// All bit fields as a 64-bit value
274 } MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER
;
278 Thread. Global Machine Check Capability (R/O).
280 @param ECX MSR_XEON_D_IA32_MCG_CAP (0x00000179)
281 @param EAX Lower 32-bits of MSR value.
282 Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.
283 @param EDX Upper 32-bits of MSR value.
284 Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.
288 MSR_XEON_D_IA32_MCG_CAP_REGISTER Msr;
290 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_MCG_CAP);
292 @note MSR_XEON_D_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
294 #define MSR_XEON_D_IA32_MCG_CAP 0x00000179
297 MSR information returned for MSR index #MSR_XEON_D_IA32_MCG_CAP
301 /// Individual bit fields
305 /// [Bits 7:0] Count.
309 /// [Bit 8] MCG_CTL_P.
313 /// [Bit 9] MCG_EXT_P.
317 /// [Bit 10] MCP_CMCI_P.
321 /// [Bit 11] MCG_TES_P.
326 /// [Bits 23:16] MCG_EXT_CNT.
328 UINT32 MCG_EXT_CNT
:8;
330 /// [Bit 24] MCG_SER_P.
334 /// [Bit 25] MCG_EM_P.
338 /// [Bit 26] MCG_ELOG_P.
345 /// All bit fields as a 32-bit value
349 /// All bit fields as a 64-bit value
352 } MSR_XEON_D_IA32_MCG_CAP_REGISTER
;
356 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
357 Enhancement. Accessible only while in SMM.
359 @param ECX MSR_XEON_D_SMM_MCA_CAP (0x0000017D)
360 @param EAX Lower 32-bits of MSR value.
361 Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.
362 @param EDX Upper 32-bits of MSR value.
363 Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.
367 MSR_XEON_D_SMM_MCA_CAP_REGISTER Msr;
369 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_SMM_MCA_CAP);
370 AsmWriteMsr64 (MSR_XEON_D_SMM_MCA_CAP, Msr.Uint64);
372 @note MSR_XEON_D_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
374 #define MSR_XEON_D_SMM_MCA_CAP 0x0000017D
377 MSR information returned for MSR index #MSR_XEON_D_SMM_MCA_CAP
381 /// Individual bit fields
387 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
388 /// SMM code access restriction is supported and a host-space interface
389 /// available to SMM handler.
391 UINT32 SMM_Code_Access_Chk
:1;
393 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
394 /// SMM long flow indicator is supported and a host-space interface
395 /// available to SMM handler.
397 UINT32 Long_Flow_Indication
:1;
401 /// All bit fields as a 64-bit value
404 } MSR_XEON_D_SMM_MCA_CAP_REGISTER
;
410 @param ECX MSR_XEON_D_TEMPERATURE_TARGET (0x000001A2)
411 @param EAX Lower 32-bits of MSR value.
412 Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.
413 @param EDX Upper 32-bits of MSR value.
414 Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.
418 MSR_XEON_D_TEMPERATURE_TARGET_REGISTER Msr;
420 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TEMPERATURE_TARGET);
421 AsmWriteMsr64 (MSR_XEON_D_TEMPERATURE_TARGET, Msr.Uint64);
423 @note MSR_XEON_D_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
425 #define MSR_XEON_D_TEMPERATURE_TARGET 0x000001A2
428 MSR information returned for MSR index #MSR_XEON_D_TEMPERATURE_TARGET
432 /// Individual bit fields
437 /// [Bits 23:16] Temperature Target (RO) See Table 2-25.
439 UINT32 TemperatureTarget
:8;
441 /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.
443 UINT32 TCCActivationOffset
:4;
448 /// All bit fields as a 32-bit value
452 /// All bit fields as a 64-bit value
455 } MSR_XEON_D_TEMPERATURE_TARGET_REGISTER
;
459 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
460 RW if MSR_PLATFORM_INFO.[28] = 1.
462 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT (0x000001AD)
463 @param EAX Lower 32-bits of MSR value.
464 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.
465 @param EDX Upper 32-bits of MSR value.
466 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.
470 MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER Msr;
472 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT);
474 @note MSR_XEON_D_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
476 #define MSR_XEON_D_TURBO_RATIO_LIMIT 0x000001AD
479 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT
483 /// Individual bit fields
487 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C.
491 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C.
495 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C.
499 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C.
503 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C.
507 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C.
511 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C.
515 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C.
520 /// All bit fields as a 64-bit value
523 } MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
;
527 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
528 RW if MSR_PLATFORM_INFO.[28] = 1.
530 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT1 (0x000001AE)
531 @param EAX Lower 32-bits of MSR value.
532 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.
533 @param EDX Upper 32-bits of MSR value.
534 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.
538 MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER Msr;
540 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT1);
542 @note MSR_XEON_D_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
544 #define MSR_XEON_D_TURBO_RATIO_LIMIT1 0x000001AE
547 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT1
551 /// Individual bit fields
555 /// [Bits 7:0] Package. Maximum Ratio Limit for 9C.
559 /// [Bits 15:8] Package. Maximum Ratio Limit for 10C.
563 /// [Bits 23:16] Package. Maximum Ratio Limit for 11C.
567 /// [Bits 31:24] Package. Maximum Ratio Limit for 12C.
571 /// [Bits 39:32] Package. Maximum Ratio Limit for 13C.
575 /// [Bits 47:40] Package. Maximum Ratio Limit for 14C.
579 /// [Bits 55:48] Package. Maximum Ratio Limit for 15C.
583 /// [Bits 63:56] Package. Maximum Ratio Limit for 16C.
588 /// All bit fields as a 64-bit value
591 } MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
;
595 Package. Unit Multipliers used in RAPL Interfaces (R/O).
597 @param ECX MSR_XEON_D_RAPL_POWER_UNIT (0x00000606)
598 @param EAX Lower 32-bits of MSR value.
599 Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.
600 @param EDX Upper 32-bits of MSR value.
601 Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.
605 MSR_XEON_D_RAPL_POWER_UNIT_REGISTER Msr;
607 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_RAPL_POWER_UNIT);
609 @note MSR_XEON_D_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
611 #define MSR_XEON_D_RAPL_POWER_UNIT 0x00000606
614 MSR information returned for MSR index #MSR_XEON_D_RAPL_POWER_UNIT
618 /// Individual bit fields
622 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
627 /// [Bits 12:8] Package. Energy Status Units Energy related information
628 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
629 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
632 UINT32 EnergyStatusUnits
:5;
635 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
643 /// All bit fields as a 32-bit value
647 /// All bit fields as a 64-bit value
650 } MSR_XEON_D_RAPL_POWER_UNIT_REGISTER
;
654 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
657 @param ECX MSR_XEON_D_DRAM_POWER_LIMIT (0x00000618)
658 @param EAX Lower 32-bits of MSR value.
659 @param EDX Upper 32-bits of MSR value.
665 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT);
666 AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT, Msr);
668 @note MSR_XEON_D_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
670 #define MSR_XEON_D_DRAM_POWER_LIMIT 0x00000618
674 Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.
676 @param ECX MSR_XEON_D_DRAM_ENERGY_STATUS (0x00000619)
677 @param EAX Lower 32-bits of MSR value.
678 Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.
679 @param EDX Upper 32-bits of MSR value.
680 Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.
684 MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER Msr;
686 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS);
688 @note MSR_XEON_D_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
690 #define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619
693 MSR information returned for MSR index #MSR_XEON_D_DRAM_ENERGY_STATUS
697 /// Individual bit fields
701 /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration
702 /// to enable DRAM RAPL mode 0 (Direct VR).
708 /// All bit fields as a 32-bit value
712 /// All bit fields as a 64-bit value
715 } MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER
;
719 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
722 @param ECX MSR_XEON_D_DRAM_PERF_STATUS (0x0000061B)
723 @param EAX Lower 32-bits of MSR value.
724 @param EDX Upper 32-bits of MSR value.
730 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_PERF_STATUS);
732 @note MSR_XEON_D_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
734 #define MSR_XEON_D_DRAM_PERF_STATUS 0x0000061B
738 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
740 @param ECX MSR_XEON_D_DRAM_POWER_INFO (0x0000061C)
741 @param EAX Lower 32-bits of MSR value.
742 @param EDX Upper 32-bits of MSR value.
748 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_INFO);
749 AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_INFO, Msr);
751 @note MSR_XEON_D_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
753 #define MSR_XEON_D_DRAM_POWER_INFO 0x0000061C
757 Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
758 fields represent the widest possible range of uncore frequencies. Writing to
759 these fields allows software to control the minimum and the maximum
760 frequency that hardware will select.
762 @param ECX MSR_XEON_D_MSRUNCORE_RATIO_LIMIT (0x00000620)
763 @param EAX Lower 32-bits of MSR value.
764 Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER.
765 @param EDX Upper 32-bits of MSR value.
766 Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER.
770 MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
772 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT);
773 AsmWriteMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
776 #define MSR_XEON_D_MSRUNCORE_RATIO_LIMIT 0x00000620
779 MSR information returned for MSR index #MSR_XEON_D_MSRUNCORE_RATIO_LIMIT
783 /// Individual bit fields
787 /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
793 /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
794 /// possible ratio of the LLC/Ring.
801 /// All bit fields as a 32-bit value
805 /// All bit fields as a 64-bit value
808 } MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER
;
811 Package. Reserved (R/O) Reads return 0.
813 @param ECX MSR_XEON_D_PP0_ENERGY_STATUS (0x00000639)
814 @param EAX Lower 32-bits of MSR value.
815 @param EDX Upper 32-bits of MSR value.
821 Msr = AsmReadMsr64 (MSR_XEON_D_PP0_ENERGY_STATUS);
823 @note MSR_XEON_D_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
825 #define MSR_XEON_D_PP0_ENERGY_STATUS 0x00000639
829 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
830 refers to processor core frequency).
832 @param ECX MSR_XEON_D_CORE_PERF_LIMIT_REASONS (0x00000690)
833 @param EAX Lower 32-bits of MSR value.
834 Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.
835 @param EDX Upper 32-bits of MSR value.
836 Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.
840 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
842 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS);
843 AsmWriteMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
845 @note MSR_XEON_D_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
847 #define MSR_XEON_D_CORE_PERF_LIMIT_REASONS 0x00000690
850 MSR information returned for MSR index #MSR_XEON_D_CORE_PERF_LIMIT_REASONS
854 /// Individual bit fields
858 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
859 /// reduced below the operating system request due to assertion of
860 /// external PROCHOT.
862 UINT32 PROCHOT_Status
:1;
864 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
865 /// operating system request due to a thermal event.
867 UINT32 ThermalStatus
:1;
869 /// [Bit 2] Power Budget Management Status (R0) When set, frequency is
870 /// reduced below the operating system request due to PBM limit.
872 UINT32 PowerBudgetManagementStatus
:1;
874 /// [Bit 3] Platform Configuration Services Status (R0) When set,
875 /// frequency is reduced below the operating system request due to PCS
878 UINT32 PlatformConfigurationServicesStatus
:1;
881 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
882 /// When set, frequency is reduced below the operating system request
883 /// because the processor has detected that utilization is low.
885 UINT32 AutonomousUtilizationBasedFrequencyControlStatus
:1;
887 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
888 /// below the operating system request due to a thermal alert from the
889 /// Voltage Regulator.
891 UINT32 VRThermAlertStatus
:1;
894 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
895 /// reduced below the operating system request due to electrical design
896 /// point constraints (e.g. maximum electrical current consumption).
898 UINT32 ElectricalDesignPointStatus
:1;
901 /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced
902 /// below the operating system request due to Multi-Core Turbo limits.
904 UINT32 MultiCoreTurboStatus
:1;
907 /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced
908 /// below max non-turbo P1.
910 UINT32 FrequencyP1Status
:1;
912 /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When
913 /// set, frequency is reduced below max n-core turbo frequency.
915 UINT32 TurboFrequencyLimitingStatus
:1;
917 /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is
918 /// reduced below the operating system request.
920 UINT32 FrequencyLimitingStatus
:1;
922 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
923 /// has asserted since the log bit was last cleared. This log bit will
924 /// remain set until cleared by software writing 0.
926 UINT32 PROCHOT_Log
:1;
928 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
929 /// has asserted since the log bit was last cleared. This log bit will
930 /// remain set until cleared by software writing 0.
934 /// [Bit 18] Power Budget Management Log When set, indicates that the PBM
935 /// Status bit has asserted since the log bit was last cleared. This log
936 /// bit will remain set until cleared by software writing 0.
938 UINT32 PowerBudgetManagementLog
:1;
940 /// [Bit 19] Platform Configuration Services Log When set, indicates that
941 /// the PCS Status bit has asserted since the log bit was last cleared.
942 /// This log bit will remain set until cleared by software writing 0.
944 UINT32 PlatformConfigurationServicesLog
:1;
947 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
948 /// indicates that the AUBFC Status bit has asserted since the log bit was
949 /// last cleared. This log bit will remain set until cleared by software
952 UINT32 AutonomousUtilizationBasedFrequencyControlLog
:1;
954 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
955 /// Alert Status bit has asserted since the log bit was last cleared. This
956 /// log bit will remain set until cleared by software writing 0.
958 UINT32 VRThermAlertLog
:1;
961 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
962 /// Status bit has asserted since the log bit was last cleared. This log
963 /// bit will remain set until cleared by software writing 0.
965 UINT32 ElectricalDesignPointLog
:1;
968 /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core
969 /// Turbo Status bit has asserted since the log bit was last cleared. This
970 /// log bit will remain set until cleared by software writing 0.
972 UINT32 MultiCoreTurboLog
:1;
975 /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core
976 /// Frequency P1 Status bit has asserted since the log bit was last
977 /// cleared. This log bit will remain set until cleared by software
980 UINT32 CoreFrequencyP1Log
:1;
982 /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,
983 /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit
984 /// has asserted since the log bit was last cleared. This log bit will
985 /// remain set until cleared by software writing 0.
987 UINT32 TurboFrequencyLimitingLog
:1;
989 /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core
990 /// Frequency Limiting Status bit has asserted since the log bit was last
991 /// cleared. This log bit will remain set until cleared by software
994 UINT32 CoreFrequencyLimitingLog
:1;
998 /// All bit fields as a 32-bit value
1002 /// All bit fields as a 64-bit value
1005 } MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
;
1009 THREAD. Monitoring Event Select Register (R/W) if CPUID.(EAX=07H,
1010 ECX=0):EBX.RDT-M[bit 12] = 1.
1012 @param ECX MSR_XEON_D_IA32_QM_EVTSEL (0x00000C8D)
1013 @param EAX Lower 32-bits of MSR value.
1014 Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.
1015 @param EDX Upper 32-bits of MSR value.
1016 Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.
1018 <b>Example usage</b>
1020 MSR_XEON_D_IA32_QM_EVTSEL_REGISTER Msr;
1022 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_QM_EVTSEL);
1023 AsmWriteMsr64 (MSR_XEON_D_IA32_QM_EVTSEL, Msr.Uint64);
1025 @note MSR_XEON_D_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
1027 #define MSR_XEON_D_IA32_QM_EVTSEL 0x00000C8D
1030 MSR information returned for MSR index #MSR_XEON_D_IA32_QM_EVTSEL
1034 /// Individual bit fields
1038 /// [Bits 7:0] EventID (RW) Event encoding: 0x00: no monitoring 0x01: L3
1039 /// occupancy monitoring 0x02: Total memory bandwidth monitoring 0x03:
1040 /// Local memory bandwidth monitoring All other encoding reserved.
1043 UINT32 Reserved1
:24;
1045 /// [Bits 41:32] RMID (RW).
1048 UINT32 Reserved2
:22;
1051 /// All bit fields as a 64-bit value
1054 } MSR_XEON_D_IA32_QM_EVTSEL_REGISTER
;
1058 THREAD. Resource Association Register (R/W).
1060 @param ECX MSR_XEON_D_IA32_PQR_ASSOC (0x00000C8F)
1061 @param EAX Lower 32-bits of MSR value.
1062 Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.
1063 @param EDX Upper 32-bits of MSR value.
1064 Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.
1066 <b>Example usage</b>
1068 MSR_XEON_D_IA32_PQR_ASSOC_REGISTER Msr;
1070 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_PQR_ASSOC);
1071 AsmWriteMsr64 (MSR_XEON_D_IA32_PQR_ASSOC, Msr.Uint64);
1073 @note MSR_XEON_D_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
1075 #define MSR_XEON_D_IA32_PQR_ASSOC 0x00000C8F
1078 MSR information returned for MSR index #MSR_XEON_D_IA32_PQR_ASSOC
1082 /// Individual bit fields
1086 /// [Bits 9:0] RMID.
1089 UINT32 Reserved1
:22;
1091 /// [Bits 51:32] COS (R/W).
1094 UINT32 Reserved2
:12;
1097 /// All bit fields as a 64-bit value
1100 } MSR_XEON_D_IA32_PQR_ASSOC_REGISTER
;
1104 Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,
1105 ECX=1):EDX.COS_MAX[15:0] >= n.
1107 @param ECX MSR_XEON_D_IA32_L3_QOS_MASK_n
1108 @param EAX Lower 32-bits of MSR value.
1109 Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
1110 @param EDX Upper 32-bits of MSR value.
1111 Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
1113 <b>Example usage</b>
1115 MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;
1117 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);
1118 AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);
1120 @note MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM.
1121 MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM.
1122 MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM.
1123 MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM.
1124 MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM.
1125 MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM.
1126 MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM.
1127 MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM.
1128 MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM.
1129 MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM.
1130 MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM.
1131 MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM.
1132 MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM.
1133 MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM.
1134 MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM.
1135 MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.
1138 #define MSR_XEON_D_IA32_L3_QOS_MASK_0 0x00000C90
1139 #define MSR_XEON_D_IA32_L3_QOS_MASK_1 0x00000C91
1140 #define MSR_XEON_D_IA32_L3_QOS_MASK_2 0x00000C92
1141 #define MSR_XEON_D_IA32_L3_QOS_MASK_3 0x00000C93
1142 #define MSR_XEON_D_IA32_L3_QOS_MASK_4 0x00000C94
1143 #define MSR_XEON_D_IA32_L3_QOS_MASK_5 0x00000C95
1144 #define MSR_XEON_D_IA32_L3_QOS_MASK_6 0x00000C96
1145 #define MSR_XEON_D_IA32_L3_QOS_MASK_7 0x00000C97
1146 #define MSR_XEON_D_IA32_L3_QOS_MASK_8 0x00000C98
1147 #define MSR_XEON_D_IA32_L3_QOS_MASK_9 0x00000C99
1148 #define MSR_XEON_D_IA32_L3_QOS_MASK_10 0x00000C9A
1149 #define MSR_XEON_D_IA32_L3_QOS_MASK_11 0x00000C9B
1150 #define MSR_XEON_D_IA32_L3_QOS_MASK_12 0x00000C9C
1151 #define MSR_XEON_D_IA32_L3_QOS_MASK_13 0x00000C9D
1152 #define MSR_XEON_D_IA32_L3_QOS_MASK_14 0x00000C9E
1153 #define MSR_XEON_D_IA32_L3_QOS_MASK_15 0x00000C9F
1157 MSR information returned for MSR indexes #MSR_XEON_D_IA32_L3_QOS_MASK_0
1158 to #MSR_XEON_D_IA32_L3_QOS_MASK_15.
1162 /// Individual bit fields
1166 /// [Bits 19:0] CBM: Bit vector of available L3 ways for COS 0 enforcement.
1169 UINT32 Reserved2
:12;
1170 UINT32 Reserved3
:32;
1173 /// All bit fields as a 32-bit value
1177 /// All bit fields as a 64-bit value
1180 } MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER
;
1184 Package. Config Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
1185 RW if MSR_PLATFORM_INFO.[28] = 1.
1187 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT3 (0x000001AC)
1188 @param EAX Lower 32-bits of MSR value.
1189 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.
1190 @param EDX Upper 32-bits of MSR value.
1191 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.
1193 <b>Example usage</b>
1195 MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER Msr;
1197 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT3);
1199 @note MSR_XEON_D_TURBO_RATIO_LIMIT3 is defined as MSR_TURBO_RATIO_LIMIT3 in SDM.
1201 #define MSR_XEON_D_TURBO_RATIO_LIMIT3 0x000001AC
1204 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT3
1208 /// Individual bit fields
1211 UINT32 Reserved1
:32;
1212 UINT32 Reserved2
:31;
1214 /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
1215 /// the processor uses override configuration specified in
1216 /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1. If 0, the processor
1217 /// uses factory-set configuration (Default).
1219 UINT32 TurboRatioLimitConfigurationSemaphore
:1;
1222 /// All bit fields as a 64-bit value
1225 } MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER
;
1229 Package. Cache Allocation Technology Configuration (R/W).
1231 @param ECX MSR_XEON_D_IA32_L3_QOS_CFG (0x00000C81)
1232 @param EAX Lower 32-bits of MSR value.
1233 Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.
1234 @param EDX Upper 32-bits of MSR value.
1235 Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.
1237 <b>Example usage</b>
1239 MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER Msr;
1241 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG);
1242 AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG, Msr.Uint64);
1244 @note MSR_XEON_D_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.
1246 #define MSR_XEON_D_IA32_L3_QOS_CFG 0x00000C81
1249 MSR information returned for MSR index #MSR_XEON_D_IA32_L3_QOS_CFG
1253 /// Individual bit fields
1257 /// [Bit 0] CAT Enable. Set 1 to enable Cache Allocation Technology.
1260 UINT32 Reserved1
:31;
1261 UINT32 Reserved2
:32;
1264 /// All bit fields as a 32-bit value
1268 /// All bit fields as a 64-bit value
1271 } MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER
;