2 MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
18 #ifndef __XEON_PHI_MSR_H__
19 #define __XEON_PHI_MSR_H__
21 #include <Register/ArchitecturalMsr.h>
24 Is Intel(R) Xeon(R) Phi(TM) processor Family?
26 @param DisplayFamily Display Family ID
27 @param DisplayModel Display Model ID
29 @retval TRUE Yes, it is.
30 @retval FALSE No, it isn't.
32 #define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
35 DisplayModel == 0x57 || \
36 DisplayModel == 0x85 \
41 Thread. SMI Counter (R/O).
43 @param ECX MSR_XEON_PHI_SMI_COUNT (0x00000034)
44 @param EAX Lower 32-bits of MSR value.
45 Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
46 @param EDX Upper 32-bits of MSR value.
47 Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
51 MSR_XEON_PHI_SMI_COUNT_REGISTER Msr;
53 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);
55 @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
57 #define MSR_XEON_PHI_SMI_COUNT 0x00000034
60 MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT
64 /// Individual bit fields
68 /// [Bits 31:0] SMI Count (R/O).
74 /// All bit fields as a 32-bit value
78 /// All bit fields as a 64-bit value
81 } MSR_XEON_PHI_SMI_COUNT_REGISTER
;
84 Package. Protected Processor Inventory Number Enable Control (R/W).
86 @param ECX MSR_XEON_PHI_PPIN_CTL (0x0000004E)
87 @param EAX Lower 32-bits of MSR value.
88 Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.
89 @param EDX Upper 32-bits of MSR value.
90 Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.
94 MSR_XEON_PHI_PPIN_CTL_REGISTER Msr;
96 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PPIN_CTL);
97 AsmWriteMsr64 (MSR_XEON_PHI_PPIN_CTL, Msr.Uint64);
100 #define MSR_XEON_PHI_PPIN_CTL 0x0000004E
103 MSR information returned for MSR index #MSR_XEON_PHI_PPIN_CTL
107 /// Individual bit fields
111 /// [Bit 0] LockOut (R/WO) Set 1 to prevent further writes to
112 /// MSR_PPIN_CTL. Writing 1 to MSR_PPINCTL[bit 0] is permitted only if
113 /// MSR_PPIN_CTL[bit 1] is clear. Default is 0. BIOS should provide an
114 /// opt-in menu to enable the user to turn on MSR_PPIN_CTL[bit 1] for a
115 /// privileged inventory initialization agent to access MSR_PPIN. After
116 /// reading MSR_PPIN, the privileged inventory initialization agent should
117 /// write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and
118 /// prevent unauthorized modification to MSR_PPIN_CTL.
122 /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible
123 /// using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0]
124 /// will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP.
127 UINT32 Enable_PPIN
:1;
132 /// All bit fields as a 32-bit value
136 /// All bit fields as a 64-bit value
139 } MSR_XEON_PHI_PPIN_CTL_REGISTER
;
143 Package. Protected Processor Inventory Number (R/O). Protected Processor
144 Inventory Number (R/O) A unique value within a given CPUID
145 family/model/stepping signature that a privileged inventory initialization
146 agent can access to identify each physical processor, when access to
147 MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if
148 MSR_PPIN_CTL[bits 1:0] = '10b'.
150 @param ECX MSR_XEON_PHI_PPIN (0x0000004F)
151 @param EAX Lower 32-bits of MSR value.
152 @param EDX Upper 32-bits of MSR value.
158 Msr = AsmReadMsr64 (MSR_XEON_PHI_PPIN);
161 #define MSR_XEON_PHI_PPIN 0x0000004F
164 Package. Platform Information Contains power management and other model
165 specific features enumeration. See http://biosbits.org.
167 @param ECX MSR_XEON_PHI_PLATFORM_INFO (0x000000CE)
168 @param EAX Lower 32-bits of MSR value.
169 Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
170 @param EDX Upper 32-bits of MSR value.
171 Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
175 MSR_XEON_PHI_PLATFORM_INFO_REGISTER Msr;
177 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);
178 AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);
180 @note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
182 #define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE
185 MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO
189 /// Individual bit fields
194 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
195 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
198 UINT32 MaximumNonTurboRatio
:8;
201 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
202 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
203 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
204 /// Turbo mode is disabled.
208 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
209 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
210 /// and when set to 0, indicates TDP Limit for Turbo mode is not
217 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
218 /// minimum ratio (maximum efficiency) that the processor can operates, in
221 UINT32 MaximumEfficiencyRatio
:8;
225 /// All bit fields as a 64-bit value
228 } MSR_XEON_PHI_PLATFORM_INFO_REGISTER
;
232 Module. C-State Configuration Control (R/W).
234 @param ECX MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x000000E2)
235 @param EAX Lower 32-bits of MSR value.
236 Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.
237 @param EDX Upper 32-bits of MSR value.
238 Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.
242 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
244 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);
245 AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
247 @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
249 #define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2
252 MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL
256 /// Individual bit fields
260 /// [Bits 2:0] Package C-State Limit (R/W) The following C-state code
261 /// name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No
262 /// Retention 011b: C6 Retention 111b: No limit.
267 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
272 /// [Bit 15] CFG Lock (R/WO).
277 /// [Bit 26] C1 State Auto Demotion Enable (R/W) When set, the processor
278 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
279 /// auto-demote information.
281 UINT32 C1StateAutoDemotionEnable
:1;
284 /// [Bit 28] C1 State Auto Undemotion Enable (R/W) When set, enables
285 /// Undemotion from Demoted C1.
287 UINT32 C1StateAutoUndemotionEnable
:1;
289 /// [Bit 29] PKG C-State Auto Demotion Enable (R/W) When set, enables
290 /// Package C state demotion.
292 UINT32 PKGC_StateAutoDemotionEnable
:1;
297 /// All bit fields as a 32-bit value
301 /// All bit fields as a 64-bit value
304 } MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
;
308 Module. Power Management IO Redirection in C-state (R/W).
310 @param ECX MSR_XEON_PHI_PMG_IO_CAPTURE_BASE (0x000000E4)
311 @param EAX Lower 32-bits of MSR value.
312 Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.
313 @param EDX Upper 32-bits of MSR value.
314 Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.
318 MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER Msr;
320 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);
321 AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);
323 @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
325 #define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4
328 MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE
332 /// Individual bit fields
336 /// [Bits 15:0] LVL_2 Base Address (R/W).
340 /// [Bits 22:16] C-State Range (R/W) The IO-port block size in which
341 /// IO-redirection will be executed (0-127). Should be programmed based on
342 /// the number of LVLx registers existing in the chipset.
344 UINT32 CStateRange
:7;
349 /// All bit fields as a 32-bit value
353 /// All bit fields as a 64-bit value
356 } MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER
;
360 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
361 handler to handle unsuccessful read of this MSR.
363 @param ECX MSR_XEON_PHI_FEATURE_CONFIG (0x0000013C)
364 @param EAX Lower 32-bits of MSR value.
365 Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.
366 @param EDX Upper 32-bits of MSR value.
367 Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.
371 MSR_XEON_PHI_FEATURE_CONFIG_REGISTER Msr;
373 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);
374 AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);
376 @note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
378 #define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C
381 MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG
385 /// Individual bit fields
389 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
390 /// MSR, the configuration of AES instruction set availability is as
391 /// follows: 11b: AES instructions are not available until next RESET.
392 /// otherwise, AES instructions are available. Note, AES instruction set
393 /// is not available if read is unsuccessful. If the configuration is not
394 /// 01b, AES instruction can be mis-configured if a privileged agent
395 /// unintentionally writes 11b.
397 UINT32 AESConfiguration
:2;
402 /// All bit fields as a 32-bit value
406 /// All bit fields as a 64-bit value
409 } MSR_XEON_PHI_FEATURE_CONFIG_REGISTER
;
413 Thread. MISC_FEATURE_ENABLES.
415 @param ECX MSR_XEON_PHI_MISC_FEATURE_ENABLES (0x00000140)
416 @param EAX Lower 32-bits of MSR value.
417 Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.
418 @param EDX Upper 32-bits of MSR value.
419 Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.
423 MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER Msr;
425 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES);
426 AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES, Msr.Uint64);
429 #define MSR_XEON_PHI_MISC_FEATURE_ENABLES 0x00000140
432 MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_ENABLES
436 /// Individual bit fields
441 /// [Bit 1] User Mode MONITOR and MWAIT (R/W) If set to 1, the MONITOR and
442 /// MWAIT instructions do not cause invalid-opcode exceptions when
443 /// executed with CPL > 0 or in virtual-8086 mode. If MWAIT is executed
444 /// when CPL > 0 or in virtual-8086 mode, and if EAX indicates a C-state
445 /// other than C0 or C1, the instruction operates as if EAX indicated the
448 UINT32 UserModeMonitorAndMwait
:1;
453 /// All bit fields as a 32-bit value
457 /// All bit fields as a 64-bit value
460 } MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER
;
463 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
464 Enhancement. Accessible only while in SMM.
466 @param ECX MSR_XEON_PHI_SMM_MCA_CAP (0x0000017D)
467 @param EAX Lower 32-bits of MSR value.
468 Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.
469 @param EDX Upper 32-bits of MSR value.
470 Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.
474 MSR_XEON_PHI_SMM_MCA_CAP_REGISTER Msr;
476 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMM_MCA_CAP);
477 AsmWriteMsr64 (MSR_XEON_PHI_SMM_MCA_CAP, Msr.Uint64);
479 @note MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
481 #define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D
484 MSR information returned for MSR index #MSR_XEON_PHI_SMM_MCA_CAP
488 /// Individual bit fields
492 /// [Bits 31:0] Bank Support (SMM-RO) One bit per MCA bank. If the bit is
493 /// set, that bank supports Enhanced MCA (Default all 0; does not support
496 UINT32 BankSupport
:32;
499 /// [Bit 56] Targeted SMI (SMM-RO) Set if targeted SMI is supported.
501 UINT32 TargetedSMI
:1;
503 /// [Bit 57] SMM_CPU_SVRSTR (SMM-RO) Set if SMM SRAM save/restore feature
506 UINT32 SMM_CPU_SVRSTR
:1;
508 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
509 /// SMM code access restriction is supported and a host-space interface
510 /// available to SMM handler.
512 UINT32 SMM_Code_Access_Chk
:1;
514 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
515 /// SMM long flow indicator is supported and a host-space interface
516 /// available to SMM handler.
518 UINT32 Long_Flow_Indication
:1;
522 /// All bit fields as a 64-bit value
525 } MSR_XEON_PHI_SMM_MCA_CAP_REGISTER
;
529 Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor
530 functions to be enabled and disabled.
532 @param ECX MSR_XEON_PHI_IA32_MISC_ENABLE (0x000001A0)
533 @param EAX Lower 32-bits of MSR value.
534 Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.
535 @param EDX Upper 32-bits of MSR value.
536 Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.
540 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER Msr;
542 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);
543 AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);
545 @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
547 #define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0
550 MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE
554 /// Individual bit fields
558 /// [Bit 0] Fast-Strings Enable.
560 UINT32 FastStrings
:1;
563 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value
566 UINT32 AutomaticThermalControlCircuit
:1;
569 /// [Bit 7] Performance Monitoring Available (R).
571 UINT32 PerformanceMonitoring
:1;
574 /// [Bit 11] Branch Trace Storage Unavailable (RO).
578 /// [Bit 12] Processor Event Based Sampling Unavailable (RO).
583 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).
588 /// [Bit 18] ENABLE MONITOR FSM (R/W).
593 /// [Bit 22] Limit CPUID Maxval (R/W).
595 UINT32 LimitCpuidMaxval
:1;
597 /// [Bit 23] xTPR Message Disable (R/W).
599 UINT32 xTPR_Message_Disable
:1;
603 /// [Bit 34] XD Bit Disable (R/W).
608 /// [Bit 38] Turbo Mode Disable (R/W).
610 UINT32 TurboModeDisable
:1;
611 UINT32 Reserved10
:25;
614 /// All bit fields as a 64-bit value
617 } MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
;
623 @param ECX MSR_XEON_PHI_TEMPERATURE_TARGET (0x000001A2)
624 @param EAX Lower 32-bits of MSR value.
625 Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.
626 @param EDX Upper 32-bits of MSR value.
627 Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.
631 MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER Msr;
633 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);
634 AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);
636 @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
638 #define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2
641 MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET
645 /// Individual bit fields
650 /// [Bits 23:16] Temperature Target (R).
652 UINT32 TemperatureTarget
:8;
654 /// [Bits 29:24] Target Offset (R/W).
656 UINT32 TargetOffset
:6;
661 /// All bit fields as a 32-bit value
665 /// All bit fields as a 64-bit value
668 } MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER
;
672 Miscellaneous Feature Control (R/W).
674 @param ECX MSR_XEON_PHI_MISC_FEATURE_CONTROL (0x000001A4)
675 @param EAX Lower 32-bits of MSR value.
676 Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.
677 @param EDX Upper 32-bits of MSR value.
678 Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.
682 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER Msr;
684 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL);
685 AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL, Msr.Uint64);
687 @note MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
689 #define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4
692 MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_CONTROL
696 /// Individual bit fields
700 /// [Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the
701 /// L1 data cache prefetcher.
703 UINT32 DCUHardwarePrefetcherDisable
:1;
705 /// [Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
706 /// L2 hardware prefetcher.
708 UINT32 L2HardwarePrefetcherDisable
:1;
713 /// All bit fields as a 32-bit value
717 /// All bit fields as a 64-bit value
720 } MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER
;
724 Shared. Offcore Response Event Select Register (R/W).
726 @param ECX MSR_XEON_PHI_OFFCORE_RSP_0 (0x000001A6)
727 @param EAX Lower 32-bits of MSR value.
728 @param EDX Upper 32-bits of MSR value.
734 Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);
735 AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);
737 @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
739 #define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6
743 Shared. Offcore Response Event Select Register (R/W).
745 @param ECX MSR_XEON_PHI_OFFCORE_RSP_1 (0x000001A7)
746 @param EAX Lower 32-bits of MSR value.
747 @param EDX Upper 32-bits of MSR value.
753 Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);
754 AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);
756 @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
758 #define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7
762 Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW).
764 @param ECX MSR_XEON_PHI_TURBO_RATIO_LIMIT (0x000001AD)
765 @param EAX Lower 32-bits of MSR value.
766 Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.
767 @param EDX Upper 32-bits of MSR value.
768 Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.
772 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER Msr;
774 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);
775 AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);
777 @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
779 #define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD
782 MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT
786 /// Individual bit fields
791 /// [Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active
792 /// processor cores which operates under the maximum ratio limit for group
795 UINT32 MaxCoresGroup0
:7;
797 /// [Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo
798 /// ratio limit when the number of active cores are not more than the
799 /// group 0 maximum core count.
801 UINT32 MaxRatioLimitGroup0
:8;
803 /// [Bits 20:16] Package. Number of Incremental Cores Added to Group 1
804 /// Group 1, which includes the specified number of additional cores plus
805 /// the cores in group 0, operates under the group 1 turbo max ratio limit
806 /// = "group 0 Max ratio limit" - "group ratio delta for group 1".
808 UINT32 MaxIncrementalCoresGroup1
:5;
810 /// [Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned
811 /// integer specifying the ratio decrement relative to the Max ratio limit
814 UINT32 DeltaRatioGroup1
:3;
816 /// [Bits 28:24] Package. Number of Incremental Cores Added to Group 2
817 /// Group 2, which includes the specified number of additional cores plus
818 /// all the cores in group 1, operates under the group 2 turbo max ratio
819 /// limit = "group 1 Max ratio limit" - "group ratio delta for group 2".
821 UINT32 MaxIncrementalCoresGroup2
:5;
823 /// [Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned
824 /// integer specifying the ratio decrement relative to the Max ratio limit
827 UINT32 DeltaRatioGroup2
:3;
829 /// [Bits 36:32] Package. Number of Incremental Cores Added to Group 3
830 /// Group 3, which includes the specified number of additional cores plus
831 /// all the cores in group 2, operates under the group 3 turbo max ratio
832 /// limit = "group 2 Max ratio limit" - "group ratio delta for group 3".
834 UINT32 MaxIncrementalCoresGroup3
:5;
836 /// [Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned
837 /// integer specifying the ratio decrement relative to the Max ratio limit
840 UINT32 DeltaRatioGroup3
:3;
842 /// [Bits 44:40] Package. Number of Incremental Cores Added to Group 4
843 /// Group 4, which includes the specified number of additional cores plus
844 /// all the cores in group 3, operates under the group 4 turbo max ratio
845 /// limit = "group 3 Max ratio limit" - "group ratio delta for group 4".
847 UINT32 MaxIncrementalCoresGroup4
:5;
849 /// [Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned
850 /// integer specifying the ratio decrement relative to the Max ratio limit
853 UINT32 DeltaRatioGroup4
:3;
855 /// [Bits 52:48] Package. Number of Incremental Cores Added to Group 5
856 /// Group 5, which includes the specified number of additional cores plus
857 /// all the cores in group 4, operates under the group 5 turbo max ratio
858 /// limit = "group 4 Max ratio limit" - "group ratio delta for group 5".
860 UINT32 MaxIncrementalCoresGroup5
:5;
862 /// [Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned
863 /// integer specifying the ratio decrement relative to the Max ratio limit
866 UINT32 DeltaRatioGroup5
:3;
868 /// [Bits 60:56] Package. Number of Incremental Cores Added to Group 6
869 /// Group 6, which includes the specified number of additional cores plus
870 /// all the cores in group 5, operates under the group 6 turbo max ratio
871 /// limit = "group 5 Max ratio limit" - "group ratio delta for group 6".
873 UINT32 MaxIncrementalCoresGroup6
:5;
875 /// [Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned
876 /// integer specifying the ratio decrement relative to the Max ratio limit
879 UINT32 DeltaRatioGroup6
:3;
882 /// All bit fields as a 64-bit value
885 } MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
;
889 Thread. Last Branch Record Filtering Select Register (R/W).
891 @param ECX MSR_XEON_PHI_LBR_SELECT (0x000001C8)
892 @param EAX Lower 32-bits of MSR value.
893 @param EDX Upper 32-bits of MSR value.
899 Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);
900 AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);
902 @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
904 #define MSR_XEON_PHI_LBR_SELECT 0x000001C8
908 MSR information returned for MSR index #MSR_XEON_PHI_LBR_SELECT
912 /// Individual bit fields
916 /// [Bit 0] CPL_EQ_0.
920 /// [Bit 1] CPL_NEQ_0.
928 /// [Bit 3] NEAR_REL_CALL.
930 UINT32 NEAR_REL_CALL
:1;
932 /// [Bit 4] NEAR_IND_CALL.
934 UINT32 NEAR_IND_CALL
:1;
936 /// [Bit 5] NEAR_RET.
940 /// [Bit 6] NEAR_IND_JMP.
942 UINT32 NEAR_IND_JMP
:1;
944 /// [Bit 7] NEAR_REL_JMP.
946 UINT32 NEAR_REL_JMP
:1;
948 /// [Bit 8] FAR_BRANCH.
955 /// All bit fields as a 32-bit value
959 /// All bit fields as a 64-bit value
962 } MSR_XEON_PHI_LBR_SELECT_REGISTER
;
965 Thread. Last Branch Record Stack TOS (R/W).
967 @param ECX MSR_XEON_PHI_LASTBRANCH_TOS (0x000001C9)
968 @param EAX Lower 32-bits of MSR value.
969 @param EDX Upper 32-bits of MSR value.
975 Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);
976 AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);
978 @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
980 #define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9
984 Thread. Last Exception Record From Linear IP (R).
986 @param ECX MSR_XEON_PHI_LER_FROM_LIP (0x000001DD)
987 @param EAX Lower 32-bits of MSR value.
988 @param EDX Upper 32-bits of MSR value.
994 Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);
996 @note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
998 #define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD
1002 Thread. Last Exception Record To Linear IP (R).
1004 @param ECX MSR_XEON_PHI_LER_TO_LIP (0x000001DE)
1005 @param EAX Lower 32-bits of MSR value.
1006 @param EDX Upper 32-bits of MSR value.
1008 <b>Example usage</b>
1012 Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);
1014 @note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
1016 #define MSR_XEON_PHI_LER_TO_LIP 0x000001DE
1020 Thread. See Table 2-2.
1022 @param ECX MSR_XEON_PHI_PEBS_ENABLE (0x000003F1)
1023 @param EAX Lower 32-bits of MSR value.
1024 @param EDX Upper 32-bits of MSR value.
1026 <b>Example usage</b>
1030 Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE);
1031 AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr);
1033 @note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1035 #define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1
1039 Package. Note: C-state values are processor specific C-state code names,
1040 unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3
1041 Residency Counter. (R/O).
1043 @param ECX MSR_XEON_PHI_PKG_C3_RESIDENCY (0x000003F8)
1044 @param EAX Lower 32-bits of MSR value.
1045 @param EDX Upper 32-bits of MSR value.
1047 <b>Example usage</b>
1051 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY);
1052 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr);
1054 @note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
1056 #define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8
1060 Package. Package C6 Residency Counter. (R/O).
1062 @param ECX MSR_XEON_PHI_PKG_C6_RESIDENCY (0x000003F9)
1063 @param EAX Lower 32-bits of MSR value.
1064 @param EDX Upper 32-bits of MSR value.
1066 <b>Example usage</b>
1070 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY);
1071 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr);
1073 @note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
1075 #define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9
1079 Package. Package C7 Residency Counter. (R/O).
1081 @param ECX MSR_XEON_PHI_PKG_C7_RESIDENCY (0x000003FA)
1082 @param EAX Lower 32-bits of MSR value.
1083 @param EDX Upper 32-bits of MSR value.
1085 <b>Example usage</b>
1089 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY);
1090 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr);
1092 @note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
1094 #define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA
1098 Module. Note: C-state values are processor specific C-state code names,
1099 unrelated to MWAIT extension C-state parameters or ACPI C-States. Module C0
1100 Residency Counter. (R/O).
1102 @param ECX MSR_XEON_PHI_MC0_RESIDENCY (0x000003FC)
1103 @param EAX Lower 32-bits of MSR value.
1104 @param EDX Upper 32-bits of MSR value.
1106 <b>Example usage</b>
1110 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY);
1111 AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr);
1113 @note MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM.
1115 #define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC
1119 Module. Module C6 Residency Counter. (R/O).
1121 @param ECX MSR_XEON_PHI_MC6_RESIDENCY (0x000003FD)
1122 @param EAX Lower 32-bits of MSR value.
1123 @param EDX Upper 32-bits of MSR value.
1125 <b>Example usage</b>
1129 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY);
1130 AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr);
1132 @note MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM.
1134 #define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD
1138 Core. Note: C-state values are processor specific C-state code names,
1139 unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6
1140 Residency Counter. (R/O).
1142 @param ECX MSR_XEON_PHI_CORE_C6_RESIDENCY (0x000003FF)
1143 @param EAX Lower 32-bits of MSR value.
1144 @param EDX Upper 32-bits of MSR value.
1146 <b>Example usage</b>
1150 Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY);
1151 AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr);
1153 @note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
1155 #define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF
1159 Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.
1161 @param ECX MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
1162 @param EAX Lower 32-bits of MSR value.
1163 @param EDX Upper 32-bits of MSR value.
1165 <b>Example usage</b>
1169 Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM);
1171 @note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
1173 #define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C
1177 Core. Capability Reporting Register of VM-Function Controls (R/O) See Table
1180 @param ECX MSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491)
1181 @param EAX Lower 32-bits of MSR value.
1182 @param EDX Upper 32-bits of MSR value.
1184 <b>Example usage</b>
1188 Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC);
1190 @note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.
1192 #define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491
1196 Package. Unit Multipliers used in RAPL Interfaces (R/O).
1198 @param ECX MSR_XEON_PHI_RAPL_POWER_UNIT (0x00000606)
1199 @param EAX Lower 32-bits of MSR value.
1200 Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.
1201 @param EDX Upper 32-bits of MSR value.
1202 Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.
1204 <b>Example usage</b>
1206 MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER Msr;
1208 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT);
1210 @note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
1212 #define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606
1215 MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT
1219 /// Individual bit fields
1223 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
1225 UINT32 PowerUnits
:4;
1228 /// [Bits 12:8] Package. Energy Status Units Energy related information
1229 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
1230 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
1233 UINT32 EnergyStatusUnits
:5;
1236 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
1240 UINT32 Reserved3
:12;
1241 UINT32 Reserved4
:32;
1244 /// All bit fields as a 32-bit value
1248 /// All bit fields as a 64-bit value
1251 } MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER
;
1255 Package. Note: C-state values are processor specific C-state code names,
1256 unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2
1257 Residency Counter. (R/O).
1259 @param ECX MSR_XEON_PHI_PKG_C2_RESIDENCY (0x0000060D)
1260 @param EAX Lower 32-bits of MSR value.
1261 @param EDX Upper 32-bits of MSR value.
1263 <b>Example usage</b>
1267 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY);
1268 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr);
1270 @note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
1272 #define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D
1276 Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
1279 @param ECX MSR_XEON_PHI_PKG_POWER_LIMIT (0x00000610)
1280 @param EAX Lower 32-bits of MSR value.
1281 @param EDX Upper 32-bits of MSR value.
1283 <b>Example usage</b>
1287 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT);
1288 AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr);
1290 @note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
1292 #define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610
1296 Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1298 @param ECX MSR_XEON_PHI_PKG_ENERGY_STATUS (0x00000611)
1299 @param EAX Lower 32-bits of MSR value.
1300 @param EDX Upper 32-bits of MSR value.
1302 <b>Example usage</b>
1306 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS);
1308 @note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
1310 #define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611
1314 Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1316 @param ECX MSR_XEON_PHI_PKG_PERF_STATUS (0x00000613)
1317 @param EAX Lower 32-bits of MSR value.
1318 @param EDX Upper 32-bits of MSR value.
1320 <b>Example usage</b>
1324 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS);
1326 @note MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
1328 #define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613
1332 Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL
1335 @param ECX MSR_XEON_PHI_PKG_POWER_INFO (0x00000614)
1336 @param EAX Lower 32-bits of MSR value.
1337 @param EDX Upper 32-bits of MSR value.
1339 <b>Example usage</b>
1343 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO);
1344 AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr);
1346 @note MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
1348 #define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614
1352 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
1355 @param ECX MSR_XEON_PHI_DRAM_POWER_LIMIT (0x00000618)
1356 @param EAX Lower 32-bits of MSR value.
1357 @param EDX Upper 32-bits of MSR value.
1359 <b>Example usage</b>
1363 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT);
1364 AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr);
1366 @note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
1368 #define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618
1372 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
1374 @param ECX MSR_XEON_PHI_DRAM_ENERGY_STATUS (0x00000619)
1375 @param EAX Lower 32-bits of MSR value.
1376 @param EDX Upper 32-bits of MSR value.
1378 <b>Example usage</b>
1382 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS);
1384 @note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
1386 #define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619
1390 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
1393 @param ECX MSR_XEON_PHI_DRAM_PERF_STATUS (0x0000061B)
1394 @param EAX Lower 32-bits of MSR value.
1395 @param EDX Upper 32-bits of MSR value.
1397 <b>Example usage</b>
1401 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS);
1403 @note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
1405 #define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B
1409 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
1411 @param ECX MSR_XEON_PHI_DRAM_POWER_INFO (0x0000061C)
1412 @param EAX Lower 32-bits of MSR value.
1413 @param EDX Upper 32-bits of MSR value.
1415 <b>Example usage</b>
1419 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO);
1420 AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr);
1422 @note MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
1424 #define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C
1428 Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
1429 fields represent the widest possible range of uncore frequencies. Writing to
1430 these fields allows software to control the minimum and the maximum
1431 frequency that hardware will select.
1433 @param ECX MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT (0x00000620)
1434 @param EAX Lower 32-bits of MSR value.
1435 Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.
1436 @param EDX Upper 32-bits of MSR value.
1437 Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.
1439 <b>Example usage</b>
1441 MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
1443 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT);
1444 AsmWriteMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
1447 #define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 0x00000620
1450 MSR information returned for MSR index #MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT
1454 /// Individual bit fields
1458 /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
1464 /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
1465 /// possible ratio of the LLC/Ring.
1468 UINT32 Reserved2
:17;
1469 UINT32 Reserved3
:32;
1472 /// All bit fields as a 32-bit value
1476 /// All bit fields as a 64-bit value
1479 } MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER
;
1483 Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
1486 @param ECX MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638)
1487 @param EAX Lower 32-bits of MSR value.
1488 @param EDX Upper 32-bits of MSR value.
1490 <b>Example usage</b>
1494 Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT);
1495 AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr);
1497 @note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
1499 #define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638
1503 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1506 @param ECX MSR_XEON_PHI_PP0_ENERGY_STATUS (0x00000639)
1507 @param EAX Lower 32-bits of MSR value.
1508 @param EDX Upper 32-bits of MSR value.
1510 <b>Example usage</b>
1514 Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS);
1516 @note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
1518 #define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639
1522 Package. Base TDP Ratio (R/O) See Table 2-24.
1524 @param ECX MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)
1525 @param EAX Lower 32-bits of MSR value.
1526 @param EDX Upper 32-bits of MSR value.
1528 <b>Example usage</b>
1532 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL);
1534 @note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
1536 #define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648
1540 Package. ConfigTDP Level 1 ratio and power level (R/O) See Table 2-24.
1542 @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)
1543 @param EAX Lower 32-bits of MSR value.
1544 @param EDX Upper 32-bits of MSR value.
1546 <b>Example usage</b>
1550 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1);
1552 @note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
1554 #define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649
1558 Package. ConfigTDP Level 2 ratio and power level (R/O) See Table 2-24.
1560 @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)
1561 @param EAX Lower 32-bits of MSR value.
1562 @param EDX Upper 32-bits of MSR value.
1564 <b>Example usage</b>
1568 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2);
1570 @note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
1572 #define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A
1576 Package. ConfigTDP Control (R/W) See Table 2-24.
1578 @param ECX MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)
1579 @param EAX Lower 32-bits of MSR value.
1580 @param EDX Upper 32-bits of MSR value.
1582 <b>Example usage</b>
1586 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL);
1587 AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr);
1589 @note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
1591 #define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B
1595 Package. ConfigTDP Control (R/W) See Table 2-24.
1597 @param ECX MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)
1598 @param EAX Lower 32-bits of MSR value.
1599 @param EDX Upper 32-bits of MSR value.
1601 <b>Example usage</b>
1605 Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO);
1606 AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr);
1608 @note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
1610 #define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C
1614 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
1615 refers to processor core frequency).
1617 @param ECX MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS (0x00000690)
1618 @param EAX Lower 32-bits of MSR value.
1619 Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.
1620 @param EDX Upper 32-bits of MSR value.
1621 Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.
1623 <b>Example usage</b>
1625 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
1627 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS);
1628 AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
1630 @note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
1632 #define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690
1635 MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS
1639 /// Individual bit fields
1643 /// [Bit 0] PROCHOT Status (R0).
1645 UINT32 PROCHOT_Status
:1;
1647 /// [Bit 1] Thermal Status (R0).
1649 UINT32 ThermalStatus
:1;
1652 /// [Bit 6] VR Therm Alert Status (R0).
1654 UINT32 VRThermAlertStatus
:1;
1657 /// [Bit 8] Electrical Design Point Status (R0).
1659 UINT32 ElectricalDesignPointStatus
:1;
1660 UINT32 Reserved3
:23;
1661 UINT32 Reserved4
:32;
1664 /// All bit fields as a 32-bit value
1668 /// All bit fields as a 64-bit value
1671 } MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER
;