2 MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
20 May 2018, Volume 4: Model-Specific-Registers (MSR)
24 #ifndef __XEON_PHI_MSR_H__
25 #define __XEON_PHI_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Is Intel(R) Xeon(R) Phi(TM) processor Family?
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
38 #define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
41 DisplayModel == 0x57 || \
42 DisplayModel == 0x85 \
47 Thread. SMI Counter (R/O).
49 @param ECX MSR_XEON_PHI_SMI_COUNT (0x00000034)
50 @param EAX Lower 32-bits of MSR value.
51 Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
52 @param EDX Upper 32-bits of MSR value.
53 Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
57 MSR_XEON_PHI_SMI_COUNT_REGISTER Msr;
59 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);
61 @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
63 #define MSR_XEON_PHI_SMI_COUNT 0x00000034
66 MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT
70 /// Individual bit fields
74 /// [Bits 31:0] SMI Count (R/O).
80 /// All bit fields as a 32-bit value
84 /// All bit fields as a 64-bit value
87 } MSR_XEON_PHI_SMI_COUNT_REGISTER
;
90 Package. Protected Processor Inventory Number Enable Control (R/W).
92 @param ECX MSR_XEON_PHI_PPIN_CTL (0x0000004E)
93 @param EAX Lower 32-bits of MSR value.
94 Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.
95 @param EDX Upper 32-bits of MSR value.
96 Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.
100 MSR_XEON_PHI_PPIN_CTL_REGISTER Msr;
102 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PPIN_CTL);
103 AsmWriteMsr64 (MSR_XEON_PHI_PPIN_CTL, Msr.Uint64);
106 #define MSR_XEON_PHI_PPIN_CTL 0x0000004E
109 MSR information returned for MSR index #MSR_XEON_PHI_PPIN_CTL
113 /// Individual bit fields
117 /// [Bit 0] LockOut (R/WO) Set 1 to prevent further writes to
118 /// MSR_PPIN_CTL. Writing 1 to MSR_PPINCTL[bit 0] is permitted only if
119 /// MSR_PPIN_CTL[bit 1] is clear. Default is 0. BIOS should provide an
120 /// opt-in menu to enable the user to turn on MSR_PPIN_CTL[bit 1] for a
121 /// privileged inventory initialization agent to access MSR_PPIN. After
122 /// reading MSR_PPIN, the privileged inventory initialization agent should
123 /// write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and
124 /// prevent unauthorized modification to MSR_PPIN_CTL.
128 /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible
129 /// using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0]
130 /// will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP.
133 UINT32 Enable_PPIN
:1;
138 /// All bit fields as a 32-bit value
142 /// All bit fields as a 64-bit value
145 } MSR_XEON_PHI_PPIN_CTL_REGISTER
;
149 Package. Protected Processor Inventory Number (R/O). Protected Processor
150 Inventory Number (R/O) A unique value within a given CPUID
151 family/model/stepping signature that a privileged inventory initialization
152 agent can access to identify each physical processor, when access to
153 MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if
154 MSR_PPIN_CTL[bits 1:0] = '10b'.
156 @param ECX MSR_XEON_PHI_PPIN (0x0000004F)
157 @param EAX Lower 32-bits of MSR value.
158 @param EDX Upper 32-bits of MSR value.
164 Msr = AsmReadMsr64 (MSR_XEON_PHI_PPIN);
167 #define MSR_XEON_PHI_PPIN 0x0000004F
170 Package. Platform Information Contains power management and other model
171 specific features enumeration. See http://biosbits.org.
173 @param ECX MSR_XEON_PHI_PLATFORM_INFO (0x000000CE)
174 @param EAX Lower 32-bits of MSR value.
175 Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
176 @param EDX Upper 32-bits of MSR value.
177 Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
181 MSR_XEON_PHI_PLATFORM_INFO_REGISTER Msr;
183 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);
184 AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);
186 @note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
188 #define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE
191 MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO
195 /// Individual bit fields
200 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
201 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
204 UINT32 MaximumNonTurboRatio
:8;
207 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
208 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
209 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
210 /// Turbo mode is disabled.
214 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
215 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
216 /// and when set to 0, indicates TDP Limit for Turbo mode is not
223 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
224 /// minimum ratio (maximum efficiency) that the processor can operates, in
227 UINT32 MaximumEfficiencyRatio
:8;
231 /// All bit fields as a 64-bit value
234 } MSR_XEON_PHI_PLATFORM_INFO_REGISTER
;
238 Module. C-State Configuration Control (R/W).
240 @param ECX MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x000000E2)
241 @param EAX Lower 32-bits of MSR value.
242 Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.
243 @param EDX Upper 32-bits of MSR value.
244 Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.
248 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
250 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);
251 AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
253 @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
255 #define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2
258 MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL
262 /// Individual bit fields
266 /// [Bits 2:0] Package C-State Limit (R/W) The following C-state code
267 /// name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No
268 /// Retention 011b: C6 Retention 111b: No limit.
273 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
278 /// [Bit 15] CFG Lock (R/WO).
285 /// All bit fields as a 32-bit value
289 /// All bit fields as a 64-bit value
292 } MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
;
296 Module. Power Management IO Redirection in C-state (R/W).
298 @param ECX MSR_XEON_PHI_PMG_IO_CAPTURE_BASE (0x000000E4)
299 @param EAX Lower 32-bits of MSR value.
300 Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.
301 @param EDX Upper 32-bits of MSR value.
302 Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.
306 MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER Msr;
308 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);
309 AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);
311 @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
313 #define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4
316 MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE
320 /// Individual bit fields
324 /// [Bits 15:0] LVL_2 Base Address (R/W).
328 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
329 /// maximum C-State code name to be included when IO read to MWAIT
330 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4
331 /// is the max C-State to include 110b - C6 is the max C-State to include.
333 UINT32 CStateRange
:3;
338 /// All bit fields as a 32-bit value
342 /// All bit fields as a 64-bit value
345 } MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER
;
349 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
350 handler to handle unsuccessful read of this MSR.
352 @param ECX MSR_XEON_PHI_FEATURE_CONFIG (0x0000013C)
353 @param EAX Lower 32-bits of MSR value.
354 Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.
355 @param EDX Upper 32-bits of MSR value.
356 Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.
360 MSR_XEON_PHI_FEATURE_CONFIG_REGISTER Msr;
362 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);
363 AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);
365 @note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
367 #define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C
370 MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG
374 /// Individual bit fields
378 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
379 /// MSR, the configuration of AES instruction set availability is as
380 /// follows: 11b: AES instructions are not available until next RESET.
381 /// otherwise, AES instructions are available. Note, AES instruction set
382 /// is not available if read is unsuccessful. If the configuration is not
383 /// 01b, AES instruction can be mis-configured if a privileged agent
384 /// unintentionally writes 11b.
386 UINT32 AESConfiguration
:2;
391 /// All bit fields as a 32-bit value
395 /// All bit fields as a 64-bit value
398 } MSR_XEON_PHI_FEATURE_CONFIG_REGISTER
;
402 Thread. MISC_FEATURE_ENABLES.
404 @param ECX MSR_XEON_PHI_MISC_FEATURE_ENABLES (0x00000140)
405 @param EAX Lower 32-bits of MSR value.
406 Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.
407 @param EDX Upper 32-bits of MSR value.
408 Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.
412 MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER Msr;
414 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES);
415 AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES, Msr.Uint64);
418 #define MSR_XEON_PHI_MISC_FEATURE_ENABLES 0x00000140
421 MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_ENABLES
425 /// Individual bit fields
430 /// [Bit 1] User Mode MONITOR and MWAIT (R/W) If set to 1, the MONITOR and
431 /// MWAIT instructions do not cause invalid-opcode exceptions when
432 /// executed with CPL > 0 or in virtual-8086 mode. If MWAIT is executed
433 /// when CPL > 0 or in virtual-8086 mode, and if EAX indicates a C-state
434 /// other than C0 or C1, the instruction operates as if EAX indicated the
437 UINT32 UserModeMonitorAndMwait
:1;
442 /// All bit fields as a 32-bit value
446 /// All bit fields as a 64-bit value
449 } MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER
;
452 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
453 Enhancement. Accessible only while in SMM.
455 @param ECX MSR_XEON_PHI_SMM_MCA_CAP (0x0000017D)
456 @param EAX Lower 32-bits of MSR value.
457 Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.
458 @param EDX Upper 32-bits of MSR value.
459 Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.
463 MSR_XEON_PHI_SMM_MCA_CAP_REGISTER Msr;
465 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMM_MCA_CAP);
466 AsmWriteMsr64 (MSR_XEON_PHI_SMM_MCA_CAP, Msr.Uint64);
468 @note MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
470 #define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D
473 MSR information returned for MSR index #MSR_XEON_PHI_SMM_MCA_CAP
477 /// Individual bit fields
483 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
484 /// SMM code access restriction is supported and a host-space interface
485 /// available to SMM handler.
487 UINT32 SMM_Code_Access_Chk
:1;
489 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
490 /// SMM long flow indicator is supported and a host-space interface
491 /// available to SMM handler.
493 UINT32 Long_Flow_Indication
:1;
497 /// All bit fields as a 64-bit value
500 } MSR_XEON_PHI_SMM_MCA_CAP_REGISTER
;
504 Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor
505 functions to be enabled and disabled.
507 @param ECX MSR_XEON_PHI_IA32_MISC_ENABLE (0x000001A0)
508 @param EAX Lower 32-bits of MSR value.
509 Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.
510 @param EDX Upper 32-bits of MSR value.
511 Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.
515 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER Msr;
517 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);
518 AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);
520 @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
522 #define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0
525 MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE
529 /// Individual bit fields
533 /// [Bit 0] Fast-Strings Enable.
535 UINT32 FastStrings
:1;
538 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value
541 UINT32 AutomaticThermalControlCircuit
:1;
544 /// [Bit 7] Performance Monitoring Available (R).
546 UINT32 PerformanceMonitoring
:1;
549 /// [Bit 11] Branch Trace Storage Unavailable (RO).
553 /// [Bit 12] Processor Event Based Sampling Unavailable (RO).
558 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).
563 /// [Bit 18] ENABLE MONITOR FSM (R/W).
568 /// [Bit 22] Limit CPUID Maxval (R/W).
570 UINT32 LimitCpuidMaxval
:1;
572 /// [Bit 23] xTPR Message Disable (R/W).
574 UINT32 xTPR_Message_Disable
:1;
578 /// [Bit 34] XD Bit Disable (R/W).
583 /// [Bit 38] Turbo Mode Disable (R/W).
585 UINT32 TurboModeDisable
:1;
586 UINT32 Reserved10
:25;
589 /// All bit fields as a 64-bit value
592 } MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
;
598 @param ECX MSR_XEON_PHI_TEMPERATURE_TARGET (0x000001A2)
599 @param EAX Lower 32-bits of MSR value.
600 Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.
601 @param EDX Upper 32-bits of MSR value.
602 Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.
606 MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER Msr;
608 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);
609 AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);
611 @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
613 #define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2
616 MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET
620 /// Individual bit fields
625 /// [Bits 23:16] Temperature Target (R).
627 UINT32 TemperatureTarget
:8;
629 /// [Bits 29:24] Target Offset (R/W).
631 UINT32 TargetOffset
:6;
636 /// All bit fields as a 32-bit value
640 /// All bit fields as a 64-bit value
643 } MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER
;
647 Miscellaneous Feature Control (R/W).
649 @param ECX MSR_XEON_PHI_MISC_FEATURE_CONTROL (0x000001A4)
650 @param EAX Lower 32-bits of MSR value.
651 Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.
652 @param EDX Upper 32-bits of MSR value.
653 Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.
657 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER Msr;
659 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL);
660 AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL, Msr.Uint64);
662 @note MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
664 #define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4
667 MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_CONTROL
671 /// Individual bit fields
675 /// [Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the
676 /// L1 data cache prefetcher.
678 UINT32 DCUHardwarePrefetcherDisable
:1;
680 /// [Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
681 /// L2 hardware prefetcher.
683 UINT32 L2HardwarePrefetcherDisable
:1;
688 /// All bit fields as a 32-bit value
692 /// All bit fields as a 64-bit value
695 } MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER
;
699 Shared. Offcore Response Event Select Register (R/W).
701 @param ECX MSR_XEON_PHI_OFFCORE_RSP_0 (0x000001A6)
702 @param EAX Lower 32-bits of MSR value.
703 @param EDX Upper 32-bits of MSR value.
709 Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);
710 AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);
712 @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
714 #define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6
718 Shared. Offcore Response Event Select Register (R/W).
720 @param ECX MSR_XEON_PHI_OFFCORE_RSP_1 (0x000001A7)
721 @param EAX Lower 32-bits of MSR value.
722 @param EDX Upper 32-bits of MSR value.
728 Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);
729 AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);
731 @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
733 #define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7
737 Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW).
739 @param ECX MSR_XEON_PHI_TURBO_RATIO_LIMIT (0x000001AD)
740 @param EAX Lower 32-bits of MSR value.
741 Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.
742 @param EDX Upper 32-bits of MSR value.
743 Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.
747 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER Msr;
749 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);
750 AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);
752 @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
754 #define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD
757 MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT
761 /// Individual bit fields
766 /// [Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active
767 /// processor cores which operates under the maximum ratio limit for group
770 UINT32 MaxCoresGroup0
:7;
772 /// [Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo
773 /// ratio limit when the number of active cores are not more than the
774 /// group 0 maximum core count.
776 UINT32 MaxRatioLimitGroup0
:8;
778 /// [Bits 20:16] Package. Number of Incremental Cores Added to Group 1
779 /// Group 1, which includes the specified number of additional cores plus
780 /// the cores in group 0, operates under the group 1 turbo max ratio limit
781 /// = "group 0 Max ratio limit" - "group ratio delta for group 1".
783 UINT32 MaxIncrementalCoresGroup1
:5;
785 /// [Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned
786 /// integer specifying the ratio decrement relative to the Max ratio limit
789 UINT32 DeltaRatioGroup1
:3;
791 /// [Bits 28:24] Package. Number of Incremental Cores Added to Group 2
792 /// Group 2, which includes the specified number of additional cores plus
793 /// all the cores in group 1, operates under the group 2 turbo max ratio
794 /// limit = "group 1 Max ratio limit" - "group ratio delta for group 2".
796 UINT32 MaxIncrementalCoresGroup2
:5;
798 /// [Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned
799 /// integer specifying the ratio decrement relative to the Max ratio limit
802 UINT32 DeltaRatioGroup2
:3;
804 /// [Bits 36:32] Package. Number of Incremental Cores Added to Group 3
805 /// Group 3, which includes the specified number of additional cores plus
806 /// all the cores in group 2, operates under the group 3 turbo max ratio
807 /// limit = "group 2 Max ratio limit" - "group ratio delta for group 3".
809 UINT32 MaxIncrementalCoresGroup3
:5;
811 /// [Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned
812 /// integer specifying the ratio decrement relative to the Max ratio limit
815 UINT32 DeltaRatioGroup3
:3;
817 /// [Bits 44:40] Package. Number of Incremental Cores Added to Group 4
818 /// Group 4, which includes the specified number of additional cores plus
819 /// all the cores in group 3, operates under the group 4 turbo max ratio
820 /// limit = "group 3 Max ratio limit" - "group ratio delta for group 4".
822 UINT32 MaxIncrementalCoresGroup4
:5;
824 /// [Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned
825 /// integer specifying the ratio decrement relative to the Max ratio limit
828 UINT32 DeltaRatioGroup4
:3;
830 /// [Bits 52:48] Package. Number of Incremental Cores Added to Group 5
831 /// Group 5, which includes the specified number of additional cores plus
832 /// all the cores in group 4, operates under the group 5 turbo max ratio
833 /// limit = "group 4 Max ratio limit" - "group ratio delta for group 5".
835 UINT32 MaxIncrementalCoresGroup5
:5;
837 /// [Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned
838 /// integer specifying the ratio decrement relative to the Max ratio limit
841 UINT32 DeltaRatioGroup5
:3;
843 /// [Bits 60:56] Package. Number of Incremental Cores Added to Group 6
844 /// Group 6, which includes the specified number of additional cores plus
845 /// all the cores in group 5, operates under the group 6 turbo max ratio
846 /// limit = "group 5 Max ratio limit" - "group ratio delta for group 6".
848 UINT32 MaxIncrementalCoresGroup6
:5;
850 /// [Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned
851 /// integer specifying the ratio decrement relative to the Max ratio limit
854 UINT32 DeltaRatioGroup6
:3;
857 /// All bit fields as a 64-bit value
860 } MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
;
864 Thread. Last Branch Record Filtering Select Register (R/W).
866 @param ECX MSR_XEON_PHI_LBR_SELECT (0x000001C8)
867 @param EAX Lower 32-bits of MSR value.
868 @param EDX Upper 32-bits of MSR value.
874 Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);
875 AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);
877 @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
879 #define MSR_XEON_PHI_LBR_SELECT 0x000001C8
883 MSR information returned for MSR index #MSR_XEON_PHI_LBR_SELECT
887 /// Individual bit fields
891 /// [Bit 0] CPL_EQ_0.
895 /// [Bit 1] CPL_NEQ_0.
903 /// [Bit 3] NEAR_REL_CALL.
905 UINT32 NEAR_REL_CALL
:1;
907 /// [Bit 4] NEAR_IND_CALL.
909 UINT32 NEAR_IND_CALL
:1;
911 /// [Bit 5] NEAR_RET.
915 /// [Bit 6] NEAR_IND_JMP.
917 UINT32 NEAR_IND_JMP
:1;
919 /// [Bit 7] NEAR_REL_JMP.
921 UINT32 NEAR_REL_JMP
:1;
923 /// [Bit 8] FAR_BRANCH.
930 /// All bit fields as a 32-bit value
934 /// All bit fields as a 64-bit value
937 } MSR_XEON_PHI_LBR_SELECT_REGISTER
;
940 Thread. Last Branch Record Stack TOS (R/W).
942 @param ECX MSR_XEON_PHI_LASTBRANCH_TOS (0x000001C9)
943 @param EAX Lower 32-bits of MSR value.
944 @param EDX Upper 32-bits of MSR value.
950 Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);
951 AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);
953 @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
955 #define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9
959 Thread. Last Exception Record From Linear IP (R).
961 @param ECX MSR_XEON_PHI_LER_FROM_LIP (0x000001DD)
962 @param EAX Lower 32-bits of MSR value.
963 @param EDX Upper 32-bits of MSR value.
969 Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);
971 @note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
973 #define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD
977 Thread. Last Exception Record To Linear IP (R).
979 @param ECX MSR_XEON_PHI_LER_TO_LIP (0x000001DE)
980 @param EAX Lower 32-bits of MSR value.
981 @param EDX Upper 32-bits of MSR value.
987 Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);
989 @note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
991 #define MSR_XEON_PHI_LER_TO_LIP 0x000001DE
995 Thread. See Table 2-2.
997 @param ECX MSR_XEON_PHI_PEBS_ENABLE (0x000003F1)
998 @param EAX Lower 32-bits of MSR value.
999 @param EDX Upper 32-bits of MSR value.
1001 <b>Example usage</b>
1005 Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE);
1006 AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr);
1008 @note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1010 #define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1
1014 Package. Note: C-state values are processor specific C-state code names,
1015 unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3
1016 Residency Counter. (R/O).
1018 @param ECX MSR_XEON_PHI_PKG_C3_RESIDENCY (0x000003F8)
1019 @param EAX Lower 32-bits of MSR value.
1020 @param EDX Upper 32-bits of MSR value.
1022 <b>Example usage</b>
1026 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY);
1027 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr);
1029 @note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
1031 #define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8
1035 Package. Package C6 Residency Counter. (R/O).
1037 @param ECX MSR_XEON_PHI_PKG_C6_RESIDENCY (0x000003F9)
1038 @param EAX Lower 32-bits of MSR value.
1039 @param EDX Upper 32-bits of MSR value.
1041 <b>Example usage</b>
1045 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY);
1046 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr);
1048 @note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
1050 #define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9
1054 Package. Package C7 Residency Counter. (R/O).
1056 @param ECX MSR_XEON_PHI_PKG_C7_RESIDENCY (0x000003FA)
1057 @param EAX Lower 32-bits of MSR value.
1058 @param EDX Upper 32-bits of MSR value.
1060 <b>Example usage</b>
1064 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY);
1065 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr);
1067 @note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
1069 #define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA
1073 Module. Note: C-state values are processor specific C-state code names,
1074 unrelated to MWAIT extension C-state parameters or ACPI C-States. Module C0
1075 Residency Counter. (R/O).
1077 @param ECX MSR_XEON_PHI_MC0_RESIDENCY (0x000003FC)
1078 @param EAX Lower 32-bits of MSR value.
1079 @param EDX Upper 32-bits of MSR value.
1081 <b>Example usage</b>
1085 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY);
1086 AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr);
1088 @note MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM.
1090 #define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC
1094 Module. Module C6 Residency Counter. (R/O).
1096 @param ECX MSR_XEON_PHI_MC6_RESIDENCY (0x000003FD)
1097 @param EAX Lower 32-bits of MSR value.
1098 @param EDX Upper 32-bits of MSR value.
1100 <b>Example usage</b>
1104 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY);
1105 AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr);
1107 @note MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM.
1109 #define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD
1113 Core. Note: C-state values are processor specific C-state code names,
1114 unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6
1115 Residency Counter. (R/O).
1117 @param ECX MSR_XEON_PHI_CORE_C6_RESIDENCY (0x000003FF)
1118 @param EAX Lower 32-bits of MSR value.
1119 @param EDX Upper 32-bits of MSR value.
1121 <b>Example usage</b>
1125 Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY);
1126 AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr);
1128 @note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
1130 #define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF
1134 Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.
1136 @param ECX MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
1137 @param EAX Lower 32-bits of MSR value.
1138 @param EDX Upper 32-bits of MSR value.
1140 <b>Example usage</b>
1144 Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM);
1146 @note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
1148 #define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C
1152 Core. Capability Reporting Register of VM-Function Controls (R/O) See Table
1155 @param ECX MSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491)
1156 @param EAX Lower 32-bits of MSR value.
1157 @param EDX Upper 32-bits of MSR value.
1159 <b>Example usage</b>
1163 Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC);
1165 @note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.
1167 #define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491
1171 Package. Unit Multipliers used in RAPL Interfaces (R/O).
1173 @param ECX MSR_XEON_PHI_RAPL_POWER_UNIT (0x00000606)
1174 @param EAX Lower 32-bits of MSR value.
1175 Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.
1176 @param EDX Upper 32-bits of MSR value.
1177 Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.
1179 <b>Example usage</b>
1181 MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER Msr;
1183 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT);
1185 @note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
1187 #define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606
1190 MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT
1194 /// Individual bit fields
1198 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
1200 UINT32 PowerUnits
:4;
1203 /// [Bits 12:8] Package. Energy Status Units Energy related information
1204 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
1205 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
1208 UINT32 EnergyStatusUnits
:5;
1211 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
1215 UINT32 Reserved3
:12;
1216 UINT32 Reserved4
:32;
1219 /// All bit fields as a 32-bit value
1223 /// All bit fields as a 64-bit value
1226 } MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER
;
1230 Package. Note: C-state values are processor specific C-state code names,
1231 unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2
1232 Residency Counter. (R/O).
1234 @param ECX MSR_XEON_PHI_PKG_C2_RESIDENCY (0x0000060D)
1235 @param EAX Lower 32-bits of MSR value.
1236 @param EDX Upper 32-bits of MSR value.
1238 <b>Example usage</b>
1242 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY);
1243 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr);
1245 @note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
1247 #define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D
1251 Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
1254 @param ECX MSR_XEON_PHI_PKG_POWER_LIMIT (0x00000610)
1255 @param EAX Lower 32-bits of MSR value.
1256 @param EDX Upper 32-bits of MSR value.
1258 <b>Example usage</b>
1262 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT);
1263 AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr);
1265 @note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
1267 #define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610
1271 Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1273 @param ECX MSR_XEON_PHI_PKG_ENERGY_STATUS (0x00000611)
1274 @param EAX Lower 32-bits of MSR value.
1275 @param EDX Upper 32-bits of MSR value.
1277 <b>Example usage</b>
1281 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS);
1283 @note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
1285 #define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611
1289 Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1291 @param ECX MSR_XEON_PHI_PKG_PERF_STATUS (0x00000613)
1292 @param EAX Lower 32-bits of MSR value.
1293 @param EDX Upper 32-bits of MSR value.
1295 <b>Example usage</b>
1299 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS);
1301 @note MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
1303 #define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613
1307 Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL
1310 @param ECX MSR_XEON_PHI_PKG_POWER_INFO (0x00000614)
1311 @param EAX Lower 32-bits of MSR value.
1312 @param EDX Upper 32-bits of MSR value.
1314 <b>Example usage</b>
1318 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO);
1319 AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr);
1321 @note MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
1323 #define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614
1327 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
1330 @param ECX MSR_XEON_PHI_DRAM_POWER_LIMIT (0x00000618)
1331 @param EAX Lower 32-bits of MSR value.
1332 @param EDX Upper 32-bits of MSR value.
1334 <b>Example usage</b>
1338 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT);
1339 AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr);
1341 @note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
1343 #define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618
1347 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
1349 @param ECX MSR_XEON_PHI_DRAM_ENERGY_STATUS (0x00000619)
1350 @param EAX Lower 32-bits of MSR value.
1351 @param EDX Upper 32-bits of MSR value.
1353 <b>Example usage</b>
1357 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS);
1359 @note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
1361 #define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619
1365 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
1368 @param ECX MSR_XEON_PHI_DRAM_PERF_STATUS (0x0000061B)
1369 @param EAX Lower 32-bits of MSR value.
1370 @param EDX Upper 32-bits of MSR value.
1372 <b>Example usage</b>
1376 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS);
1378 @note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
1380 #define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B
1384 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
1386 @param ECX MSR_XEON_PHI_DRAM_POWER_INFO (0x0000061C)
1387 @param EAX Lower 32-bits of MSR value.
1388 @param EDX Upper 32-bits of MSR value.
1390 <b>Example usage</b>
1394 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO);
1395 AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr);
1397 @note MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
1399 #define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C
1403 Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
1404 fields represent the widest possible range of uncore frequencies. Writing to
1405 these fields allows software to control the minimum and the maximum
1406 frequency that hardware will select.
1408 @param ECX MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT (0x00000620)
1409 @param EAX Lower 32-bits of MSR value.
1410 Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.
1411 @param EDX Upper 32-bits of MSR value.
1412 Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.
1414 <b>Example usage</b>
1416 MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
1418 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT);
1419 AsmWriteMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
1422 #define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 0x00000620
1425 MSR information returned for MSR index #MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT
1429 /// Individual bit fields
1433 /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
1439 /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
1440 /// possible ratio of the LLC/Ring.
1443 UINT32 Reserved2
:17;
1444 UINT32 Reserved3
:32;
1447 /// All bit fields as a 32-bit value
1451 /// All bit fields as a 64-bit value
1454 } MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER
;
1458 Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
1461 @param ECX MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638)
1462 @param EAX Lower 32-bits of MSR value.
1463 @param EDX Upper 32-bits of MSR value.
1465 <b>Example usage</b>
1469 Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT);
1470 AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr);
1472 @note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
1474 #define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638
1478 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1481 @param ECX MSR_XEON_PHI_PP0_ENERGY_STATUS (0x00000639)
1482 @param EAX Lower 32-bits of MSR value.
1483 @param EDX Upper 32-bits of MSR value.
1485 <b>Example usage</b>
1489 Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS);
1491 @note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
1493 #define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639
1497 Package. Base TDP Ratio (R/O) See Table 2-24.
1499 @param ECX MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)
1500 @param EAX Lower 32-bits of MSR value.
1501 @param EDX Upper 32-bits of MSR value.
1503 <b>Example usage</b>
1507 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL);
1509 @note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
1511 #define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648
1515 Package. ConfigTDP Level 1 ratio and power level (R/O) See Table 2-24.
1517 @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)
1518 @param EAX Lower 32-bits of MSR value.
1519 @param EDX Upper 32-bits of MSR value.
1521 <b>Example usage</b>
1525 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1);
1527 @note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
1529 #define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649
1533 Package. ConfigTDP Level 2 ratio and power level (R/O) See Table 2-24.
1535 @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)
1536 @param EAX Lower 32-bits of MSR value.
1537 @param EDX Upper 32-bits of MSR value.
1539 <b>Example usage</b>
1543 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2);
1545 @note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
1547 #define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A
1551 Package. ConfigTDP Control (R/W) See Table 2-24.
1553 @param ECX MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)
1554 @param EAX Lower 32-bits of MSR value.
1555 @param EDX Upper 32-bits of MSR value.
1557 <b>Example usage</b>
1561 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL);
1562 AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr);
1564 @note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
1566 #define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B
1570 Package. ConfigTDP Control (R/W) See Table 2-24.
1572 @param ECX MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)
1573 @param EAX Lower 32-bits of MSR value.
1574 @param EDX Upper 32-bits of MSR value.
1576 <b>Example usage</b>
1580 Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO);
1581 AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr);
1583 @note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
1585 #define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C
1589 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
1590 refers to processor core frequency).
1592 @param ECX MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS (0x00000690)
1593 @param EAX Lower 32-bits of MSR value.
1594 Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.
1595 @param EDX Upper 32-bits of MSR value.
1596 Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.
1598 <b>Example usage</b>
1600 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
1602 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS);
1603 AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
1605 @note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
1607 #define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690
1610 MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS
1614 /// Individual bit fields
1618 /// [Bit 0] PROCHOT Status (R0).
1620 UINT32 PROCHOT_Status
:1;
1622 /// [Bit 1] Thermal Status (R0).
1624 UINT32 ThermalStatus
:1;
1627 /// [Bit 6] VR Therm Alert Status (R0).
1629 UINT32 VRThermAlertStatus
:1;
1632 /// [Bit 8] Electrical Design Point Status (R0).
1634 UINT32 ElectricalDesignPointStatus
:1;
1635 UINT32 Reserved3
:23;
1636 UINT32 Reserved4
:32;
1639 /// All bit fields as a 32-bit value
1643 /// All bit fields as a 64-bit value
1646 } MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER
;