UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h

   1 /** @file
   2   MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
  10   This program and the accompanying materials
  11   are licensed and made available under the terms and conditions of the BSD License
  12   which accompanies this distribution.  The full text of the license may be found at
  13   http://opensource.org/licenses/bsd-license.php
  14
  15   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17
  18   @par Specification Reference:
  19   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
  20   December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-15.
  21
  22 **/
  23
  24 #ifndef __XEON_PHI_MSR_H__
  25 #define __XEON_PHI_MSR_H__
  26
  27 #include <Register/ArchitecturalMsr.h>
  28
  29 /**
  30   Thread. SMI Counter (R/O).
  31
  32   @param  ECX  MSR_XEON_PHI_SMI_COUNT (0x00000034)
  33   @param  EAX  Lower 32-bits of MSR value.
  34                Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
  35   @param  EDX  Upper 32-bits of MSR value.
  36                Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
  37
  38   <b>Example usage</b>
  39   @code
  40   MSR_XEON_PHI_SMI_COUNT_REGISTER  Msr;
  41
  42   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);
  43   @endcode
  44 **/
  45 #define MSR_XEON_PHI_SMI_COUNT                   0x00000034
  46
  47 /**
  48   MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT
  49 **/
  50 typedef union {
  51   ///
  52   /// Individual bit fields
  53   ///
  54   struct {
  55     ///
  56     /// [Bits 31:0] SMI Count (R/O).
  57     ///
  58     UINT32  SMICount:32;
  59     UINT32  Reserved:32;
  60   } Bits;
  61   ///
  62   /// All bit fields as a 32-bit value
  63   ///
  64   UINT32  Uint32;
  65   ///
  66   /// All bit fields as a 64-bit value
  67   ///
  68   UINT64  Uint64;
  69 } MSR_XEON_PHI_SMI_COUNT_REGISTER;
  70
  71
  72 /**
  73   Package. See http://biosbits.org.
  74
  75   @param  ECX  MSR_XEON_PHI_PLATFORM_INFO (0x000000CE)
  76   @param  EAX  Lower 32-bits of MSR value.
  77                Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
  78   @param  EDX  Upper 32-bits of MSR value.
  79                Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
  80
  81   <b>Example usage</b>
  82   @code
  83   MSR_XEON_PHI_PLATFORM_INFO_REGISTER  Msr;
  84
  85   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);
  86   AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);
  87   @endcode
  88 **/
  89 #define MSR_XEON_PHI_PLATFORM_INFO               0x000000CE
  90
  91 /**
  92   MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO
  93 **/
  94 typedef union {
  95   ///
  96   /// Individual bit fields
  97   ///
  98   struct {
  99     UINT32  Reserved1:8;
 100     ///
 101     /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
 102     /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
 103     /// MHz.
 104     ///
 105     UINT32  MaximumNonTurboRatio:8;
 106     UINT32  Reserved2:12;
 107     ///
 108     /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
 109     /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
 110     /// enabled, and when set to 0, indicates Programmable Ratio Limits for
 111     /// Turbo mode is disabled.
 112     ///
 113     UINT32  RatioLimit:1;
 114     ///
 115     /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
 116     /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
 117     /// and when set to 0, indicates TDP Limit for Turbo mode is not
 118     /// programmable.
 119     ///
 120     UINT32  TDPLimit:1;
 121     UINT32  Reserved3:2;
 122     UINT32  Reserved4:8;
 123     ///
 124     /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
 125     /// minimum ratio (maximum efficiency) that the processor can operates, in
 126     /// units of 100MHz.
 127     ///
 128     UINT32  MaximumEfficiencyRatio:8;
 129     UINT32  Reserved5:16;
 130   } Bits;
 131   ///
 132   /// All bit fields as a 64-bit value
 133   ///
 134   UINT64  Uint64;
 135 } MSR_XEON_PHI_PLATFORM_INFO_REGISTER;
 136
 137
 138 /**
 139   Module. C-State Configuration Control (R/W).
 140
 141   @param  ECX  MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x000000E2)
 142   @param  EAX  Lower 32-bits of MSR value.
 143                Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.
 144   @param  EDX  Upper 32-bits of MSR value.
 145                Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.
 146
 147   <b>Example usage</b>
 148   @code
 149   MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
 150
 151   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);
 152   AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
 153   @endcode
 154 **/
 155 #define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL      0x000000E2
 156
 157 /**
 158   MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL
 159 **/
 160 typedef union {
 161   ///
 162   /// Individual bit fields
 163   ///
 164   struct {
 165     ///
 166     /// [Bits 2:0] Package C-State Limit (R/W)  The following C-state code
 167     /// name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No
 168     /// Retention 011b: C6 Retention 111b: No limit.
 169     ///
 170     UINT32  Limit:3;
 171     UINT32  Reserved1:7;
 172     ///
 173     /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
 174     ///
 175     UINT32  IO_MWAIT:1;
 176     UINT32  Reserved2:4;
 177     ///
 178     /// [Bit 15] CFG Lock (R/WO).
 179     ///
 180     UINT32  CFGLock:1;
 181     UINT32  Reserved3:16;
 182     UINT32  Reserved4:32;
 183   } Bits;
 184   ///
 185   /// All bit fields as a 32-bit value
 186   ///
 187   UINT32  Uint32;
 188   ///
 189   /// All bit fields as a 64-bit value
 190   ///
 191   UINT64  Uint64;
 192 } MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER;
 193
 194
 195 /**
 196   Module. Power Management IO Redirection in C-state (R/W).
 197
 198   @param  ECX  MSR_XEON_PHI_PMG_IO_CAPTURE_BASE (0x000000E4)
 199   @param  EAX  Lower 32-bits of MSR value.
 200                Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.
 201   @param  EDX  Upper 32-bits of MSR value.
 202                Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.
 203
 204   <b>Example usage</b>
 205   @code
 206   MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER  Msr;
 207
 208   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);
 209   AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);
 210   @endcode
 211 **/
 212 #define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE         0x000000E4
 213
 214 /**
 215   MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE
 216 **/
 217 typedef union {
 218   ///
 219   /// Individual bit fields
 220   ///
 221   struct {
 222     ///
 223     /// [Bits 15:0] LVL_2 Base Address (R/W).
 224     ///
 225     UINT32  Lvl2Base:16;
 226     ///
 227     /// [Bits 18:16] C-state Range (R/W)  Specifies the encoding value of the
 228     /// maximum C-State code name to be included when IO read to MWAIT
 229     /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4
 230     /// is the max C-State to include 110b - C6 is the max C-State to include.
 231     ///
 232     UINT32  CStateRange:3;
 233     UINT32  Reserved1:13;
 234     UINT32  Reserved2:32;
 235   } Bits;
 236   ///
 237   /// All bit fields as a 32-bit value
 238   ///
 239   UINT32  Uint32;
 240   ///
 241   /// All bit fields as a 64-bit value
 242   ///
 243   UINT64  Uint64;
 244 } MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER;
 245
 246
 247 /**
 248   Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
 249   handler to handle unsuccessful read of this MSR.
 250
 251   @param  ECX  MSR_XEON_PHI_FEATURE_CONFIG (0x0000013C)
 252   @param  EAX  Lower 32-bits of MSR value.
 253                Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.
 254   @param  EDX  Upper 32-bits of MSR value.
 255                Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.
 256
 257   <b>Example usage</b>
 258   @code
 259   MSR_XEON_PHI_FEATURE_CONFIG_REGISTER  Msr;
 260
 261   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);
 262   AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);
 263   @endcode
 264 **/
 265 #define MSR_XEON_PHI_FEATURE_CONFIG              0x0000013C
 266
 267 /**
 268   MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG
 269 **/
 270 typedef union {
 271   ///
 272   /// Individual bit fields
 273   ///
 274   struct {
 275     ///
 276     /// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this
 277     /// MSR, the configuration of AES instruction set availability is as
 278     /// follows: 11b: AES instructions are not available until next RESET.
 279     /// otherwise, AES instructions are available. Note, AES instruction set
 280     /// is not available if read is unsuccessful. If the configuration is not
 281     /// 01b, AES instruction can be mis-configured if a privileged agent
 282     /// unintentionally writes 11b.
 283     ///
 284     UINT32  AESConfiguration:2;
 285     UINT32  Reserved1:30;
 286     UINT32  Reserved2:32;
 287   } Bits;
 288   ///
 289   /// All bit fields as a 32-bit value
 290   ///
 291   UINT32  Uint32;
 292   ///
 293   /// All bit fields as a 64-bit value
 294   ///
 295   UINT64  Uint64;
 296 } MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;
 297
 298
 299 /**
 300   Thread. Enable Misc. Processor Features (R/W)  Allows a variety of processor
 301   functions to be enabled and disabled.
 302
 303   @param  ECX  MSR_XEON_PHI_IA32_MISC_ENABLE (0x000001A0)
 304   @param  EAX  Lower 32-bits of MSR value.
 305                Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.
 306   @param  EDX  Upper 32-bits of MSR value.
 307                Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.
 308
 309   <b>Example usage</b>
 310   @code
 311   MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER  Msr;
 312
 313   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);
 314   AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);
 315   @endcode
 316 **/
 317 #define MSR_XEON_PHI_IA32_MISC_ENABLE            0x000001A0
 318
 319 /**
 320   MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE
 321 **/
 322 typedef union {
 323   ///
 324   /// Individual bit fields
 325   ///
 326   struct {
 327     ///
 328     /// [Bit 0] Fast-Strings Enable.
 329     ///
 330     UINT32  FastStrings:1;
 331     UINT32  Reserved1:2;
 332     ///
 333     /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W).
 334     ///
 335     UINT32  AutomaticThermalControlCircuit:1;
 336     UINT32  Reserved2:3;
 337     ///
 338     /// [Bit 7] Performance Monitoring Available (R).
 339     ///
 340     UINT32  PerformanceMonitoring:1;
 341     UINT32  Reserved3:3;
 342     ///
 343     /// [Bit 11] Branch Trace Storage Unavailable (RO).
 344     ///
 345     UINT32  BTS:1;
 346     ///
 347     /// [Bit 12] Precise Event Based Sampling Unavailable (RO).
 348     ///
 349     UINT32  PEBS:1;
 350     UINT32  Reserved4:3;
 351     ///
 352     /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).
 353     ///
 354     UINT32  EIST:1;
 355     UINT32  Reserved5:1;
 356     ///
 357     /// [Bit 18] ENABLE MONITOR FSM (R/W).
 358     ///
 359     UINT32  MONITOR:1;
 360     UINT32  Reserved6:3;
 361     ///
 362     /// [Bit 22] Limit CPUID Maxval (R/W).
 363     ///
 364     UINT32  LimitCpuidMaxval:1;
 365     ///
 366     /// [Bit 23] xTPR Message Disable (R/W).
 367     ///
 368     UINT32  xTPR_Message_Disable:1;
 369     UINT32  Reserved7:8;
 370     UINT32  Reserved8:2;
 371     ///
 372     /// [Bit 34] XD Bit Disable (R/W).
 373     ///
 374     UINT32  XD:1;
 375     UINT32  Reserved9:3;
 376     ///
 377     /// [Bit 38] Turbo Mode Disable (R/W).
 378     ///
 379     UINT32  TurboModeDisable:1;
 380     UINT32  Reserved10:25;
 381   } Bits;
 382   ///
 383   /// All bit fields as a 64-bit value
 384   ///
 385   UINT64  Uint64;
 386 } MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER;
 387
 388
 389 /**
 390   Package.
 391
 392   @param  ECX  MSR_XEON_PHI_TEMPERATURE_TARGET (0x000001A2)
 393   @param  EAX  Lower 32-bits of MSR value.
 394                Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.
 395   @param  EDX  Upper 32-bits of MSR value.
 396                Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.
 397
 398   <b>Example usage</b>
 399   @code
 400   MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER  Msr;
 401
 402   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);
 403   AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);
 404   @endcode
 405 **/
 406 #define MSR_XEON_PHI_TEMPERATURE_TARGET          0x000001A2
 407
 408 /**
 409   MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET
 410 **/
 411 typedef union {
 412   ///
 413   /// Individual bit fields
 414   ///
 415   struct {
 416     UINT32  Reserved1:16;
 417     ///
 418     /// [Bits 23:16] Temperature Target (R).
 419     ///
 420     UINT32  TemperatureTarget:8;
 421     ///
 422     /// [Bits 29:24] Target Offset (R/W).
 423     ///
 424     UINT32  TargetOffset:6;
 425     UINT32  Reserved2:2;
 426     UINT32  Reserved3:32;
 427   } Bits;
 428   ///
 429   /// All bit fields as a 32-bit value
 430   ///
 431   UINT32  Uint32;
 432   ///
 433   /// All bit fields as a 64-bit value
 434   ///
 435   UINT64  Uint64;
 436 } MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER;
 437
 438
 439 /**
 440   Shared. Offcore Response Event Select Register (R/W).
 441
 442   @param  ECX  MSR_XEON_PHI_OFFCORE_RSP_0 (0x000001A6)
 443   @param  EAX  Lower 32-bits of MSR value.
 444   @param  EDX  Upper 32-bits of MSR value.
 445
 446   <b>Example usage</b>
 447   @code
 448   UINT64  Msr;
 449
 450   Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);
 451   AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);
 452   @endcode
 453 **/
 454 #define MSR_XEON_PHI_OFFCORE_RSP_0               0x000001A6
 455
 456
 457 /**
 458   Shared. Offcore Response Event Select Register (R/W).
 459
 460   @param  ECX  MSR_XEON_PHI_OFFCORE_RSP_1 (0x000001A7)
 461   @param  EAX  Lower 32-bits of MSR value.
 462   @param  EDX  Upper 32-bits of MSR value.
 463
 464   <b>Example usage</b>
 465   @code
 466   UINT64  Msr;
 467
 468   Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);
 469   AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);
 470   @endcode
 471 **/
 472 #define MSR_XEON_PHI_OFFCORE_RSP_1               0x000001A7
 473
 474
 475 /**
 476   Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW).
 477
 478   @param  ECX  MSR_XEON_PHI_TURBO_RATIO_LIMIT (0x000001AD)
 479   @param  EAX  Lower 32-bits of MSR value.
 480                Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.
 481   @param  EDX  Upper 32-bits of MSR value.
 482                Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.
 483
 484   <b>Example usage</b>
 485   @code
 486   MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER  Msr;
 487
 488   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);
 489   AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);
 490   @endcode
 491 **/
 492 #define MSR_XEON_PHI_TURBO_RATIO_LIMIT           0x000001AD
 493
 494 /**
 495   MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT
 496 **/
 497 typedef union {
 498   ///
 499   /// Individual bit fields
 500   ///
 501   struct {
 502     UINT32  Reserved:1;
 503     ///
 504     /// [Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active
 505     /// processor cores which operates under the maximum ratio limit for group
 506     /// 0.
 507     ///
 508     UINT32  MaxCoresGroup0:7;
 509     ///
 510     /// [Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo
 511     /// ratio limit when the number of active cores are not more than the
 512     /// group 0 maximum core count.
 513     ///
 514     UINT32  MaxRatioLimitGroup0:8;
 515     ///
 516     /// [Bits 20:16] Package. Number of Incremental Cores Added to Group 1
 517     /// Group 1, which includes the specified number of additional cores plus
 518     /// the cores in group 0, operates under the group 1 turbo max ratio limit
 519     /// = "group 0 Max ratio limit" - "group ratio delta for group 1".
 520     ///
 521     UINT32  MaxIncrementalCoresGroup1:5;
 522     ///
 523     /// [Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned
 524     /// integer specifying the ratio decrement relative to the Max ratio limit
 525     /// to Group 0.
 526     ///
 527     UINT32  DeltaRatioGroup1:3;
 528     ///
 529     /// [Bits 28:24] Package. Number of Incremental Cores Added to Group 2
 530     /// Group 2, which includes the specified number of additional cores plus
 531     /// all the cores in group 1, operates under the group 2 turbo max ratio
 532     /// limit = "group 1 Max ratio limit" - "group ratio delta for group 2".
 533     ///
 534     UINT32  MaxIncrementalCoresGroup2:5;
 535     ///
 536     /// [Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned
 537     /// integer specifying the ratio decrement relative to the Max ratio limit
 538     /// for Group 1.
 539     ///
 540     UINT32  DeltaRatioGroup2:3;
 541     ///
 542     /// [Bits 36:32] Package. Number of Incremental Cores Added to Group 3
 543     /// Group 3, which includes the specified number of additional cores plus
 544     /// all the cores in group 2, operates under the group 3 turbo max ratio
 545     /// limit = "group 2 Max ratio limit" - "group ratio delta for group 3".
 546     ///
 547     UINT32  MaxIncrementalCoresGroup3:5;
 548     ///
 549     /// [Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned
 550     /// integer specifying the ratio decrement relative to the Max ratio limit
 551     /// for Group 2.
 552     ///
 553     UINT32  DeltaRatioGroup3:3;
 554     ///
 555     /// [Bits 44:40] Package. Number of Incremental Cores Added to Group 4
 556     /// Group 4, which includes the specified number of additional cores plus
 557     /// all the cores in group 3, operates under the group 4 turbo max ratio
 558     /// limit = "group 3 Max ratio limit" - "group ratio delta for group 4".
 559     ///
 560     UINT32  MaxIncrementalCoresGroup4:5;
 561     ///
 562     /// [Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned
 563     /// integer specifying the ratio decrement relative to the Max ratio limit
 564     /// for Group 3.
 565     ///
 566     UINT32  DeltaRatioGroup4:3;
 567     ///
 568     /// [Bits 52:48] Package. Number of Incremental Cores Added to Group 5
 569     /// Group 5, which includes the specified number of additional cores plus
 570     /// all the cores in group 4, operates under the group 5 turbo max ratio
 571     /// limit = "group 4 Max ratio limit" - "group ratio delta for group 5".
 572     ///
 573     UINT32  MaxIncrementalCoresGroup5:5;
 574     ///
 575     /// [Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned
 576     /// integer specifying the ratio decrement relative to the Max ratio limit
 577     /// for Group 4.
 578     ///
 579     UINT32  DeltaRatioGroup5:3;
 580     ///
 581     /// [Bits 60:56] Package. Number of Incremental Cores Added to Group 6
 582     /// Group 6, which includes the specified number of additional cores plus
 583     /// all the cores in group 5, operates under the group 6 turbo max ratio
 584     /// limit = "group 5 Max ratio limit" - "group ratio delta for group 6".
 585     ///
 586     UINT32  MaxIncrementalCoresGroup6:5;
 587     ///
 588     /// [Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned
 589     /// integer specifying the ratio decrement relative to the Max ratio limit
 590     /// for Group 5.
 591     ///
 592     UINT32  DeltaRatioGroup6:3;
 593   } Bits;
 594   ///
 595   /// All bit fields as a 64-bit value
 596   ///
 597   UINT64  Uint64;
 598 } MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER;
 599
 600
 601 /**
 602   Thread. Last Branch Record Filtering Select Register (R/W).
 603
 604   @param  ECX  MSR_XEON_PHI_LBR_SELECT (0x000001C8)
 605   @param  EAX  Lower 32-bits of MSR value.
 606   @param  EDX  Upper 32-bits of MSR value.
 607
 608   <b>Example usage</b>
 609   @code
 610   UINT64  Msr;
 611
 612   Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);
 613   AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);
 614   @endcode
 615 **/
 616 #define MSR_XEON_PHI_LBR_SELECT                  0x000001C8
 617
 618
 619 /**
 620   Thread. Last Branch Record Stack TOS (R/W).
 621
 622   @param  ECX  MSR_XEON_PHI_LASTBRANCH_TOS (0x000001C9)
 623   @param  EAX  Lower 32-bits of MSR value.
 624   @param  EDX  Upper 32-bits of MSR value.
 625
 626   <b>Example usage</b>
 627   @code
 628   UINT64  Msr;
 629
 630   Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);
 631   AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);
 632   @endcode
 633 **/
 634 #define MSR_XEON_PHI_LASTBRANCH_TOS              0x000001C9
 635
 636
 637 /**
 638   Thread. Last Exception Record From Linear IP (R).
 639
 640   @param  ECX  MSR_XEON_PHI_LER_FROM_LIP (0x000001DD)
 641   @param  EAX  Lower 32-bits of MSR value.
 642   @param  EDX  Upper 32-bits of MSR value.
 643
 644   <b>Example usage</b>
 645   @code
 646   UINT64  Msr;
 647
 648   Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);
 649   @endcode
 650 **/
 651 #define MSR_XEON_PHI_LER_FROM_LIP                0x000001DD
 652
 653
 654 /**
 655   Thread. Last Exception Record To Linear IP (R).
 656
 657   @param  ECX  MSR_XEON_PHI_LER_TO_LIP (0x000001DE)
 658   @param  EAX  Lower 32-bits of MSR value.
 659   @param  EDX  Upper 32-bits of MSR value.
 660
 661   <b>Example usage</b>
 662   @code
 663   UINT64  Msr;
 664
 665   Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);
 666   @endcode
 667 **/
 668 #define MSR_XEON_PHI_LER_TO_LIP                  0x000001DE
 669
 670
 671 /**
 672   Thread. See Table 35-2.
 673
 674   @param  ECX  MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS (0x0000038E)
 675   @param  EAX  Lower 32-bits of MSR value.
 676   @param  EDX  Upper 32-bits of MSR value.
 677
 678   <b>Example usage</b>
 679   @code
 680   UINT64  Msr;
 681
 682   Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS);
 683   AsmWriteMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS, Msr);
 684   @endcode
 685 **/
 686 #define MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS      0x0000038E
 687
 688
 689 /**
 690   Thread. See Table 35-2.
 691
 692   @param  ECX  MSR_XEON_PHI_PEBS_ENABLE (0x000003F1)
 693   @param  EAX  Lower 32-bits of MSR value.
 694   @param  EDX  Upper 32-bits of MSR value.
 695
 696   <b>Example usage</b>
 697   @code
 698   UINT64  Msr;
 699
 700   Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE);
 701   AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr);
 702   @endcode
 703 **/
 704 #define MSR_XEON_PHI_PEBS_ENABLE                 0x000003F1
 705
 706
 707 /**
 708   Package. Note: C-state values are processor specific C-state code names,
 709   unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3
 710   Residency Counter. (R/O).
 711
 712   @param  ECX  MSR_XEON_PHI_PKG_C3_RESIDENCY (0x000003F8)
 713   @param  EAX  Lower 32-bits of MSR value.
 714   @param  EDX  Upper 32-bits of MSR value.
 715
 716   <b>Example usage</b>
 717   @code
 718   UINT64  Msr;
 719
 720   Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY);
 721   AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr);
 722   @endcode
 723 **/
 724 #define MSR_XEON_PHI_PKG_C3_RESIDENCY            0x000003F8
 725
 726
 727 /**
 728   Package. Package C6 Residency Counter. (R/O).
 729
 730   @param  ECX  MSR_XEON_PHI_PKG_C6_RESIDENCY (0x000003F9)
 731   @param  EAX  Lower 32-bits of MSR value.
 732   @param  EDX  Upper 32-bits of MSR value.
 733
 734   <b>Example usage</b>
 735   @code
 736   UINT64  Msr;
 737
 738   Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY);
 739   AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr);
 740   @endcode
 741 **/
 742 #define MSR_XEON_PHI_PKG_C6_RESIDENCY            0x000003F9
 743
 744
 745 /**
 746   Package. Package C7 Residency Counter. (R/O).
 747
 748   @param  ECX  MSR_XEON_PHI_PKG_C7_RESIDENCY (0x000003FA)
 749   @param  EAX  Lower 32-bits of MSR value.
 750   @param  EDX  Upper 32-bits of MSR value.
 751
 752   <b>Example usage</b>
 753   @code
 754   UINT64  Msr;
 755
 756   Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY);
 757   AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr);
 758   @endcode
 759 **/
 760 #define MSR_XEON_PHI_PKG_C7_RESIDENCY            0x000003FA
 761
 762
 763 /**
 764   Module. Note: C-state values are processor specific C-state code names,
 765   unrelated to MWAIT extension C-state parameters or ACPI C-States. Module C0
 766   Residency Counter. (R/O).
 767
 768   @param  ECX  MSR_XEON_PHI_MC0_RESIDENCY (0x000003FC)
 769   @param  EAX  Lower 32-bits of MSR value.
 770   @param  EDX  Upper 32-bits of MSR value.
 771
 772   <b>Example usage</b>
 773   @code
 774   UINT64  Msr;
 775
 776   Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY);
 777   AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr);
 778   @endcode
 779 **/
 780 #define MSR_XEON_PHI_MC0_RESIDENCY               0x000003FC
 781
 782
 783 /**
 784   Module. Module C6 Residency Counter. (R/O).
 785
 786   @param  ECX  MSR_XEON_PHI_MC6_RESIDENCY (0x000003FD)
 787   @param  EAX  Lower 32-bits of MSR value.
 788   @param  EDX  Upper 32-bits of MSR value.
 789
 790   <b>Example usage</b>
 791   @code
 792   UINT64  Msr;
 793
 794   Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY);
 795   AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr);
 796   @endcode
 797 **/
 798 #define MSR_XEON_PHI_MC6_RESIDENCY               0x000003FD
 799
 800
 801 /**
 802   Core. Note: C-state values are processor specific C-state code names,
 803   unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6
 804   Residency Counter. (R/O).
 805
 806   @param  ECX  MSR_XEON_PHI_CORE_C6_RESIDENCY (0x000003FF)
 807   @param  EAX  Lower 32-bits of MSR value.
 808   @param  EDX  Upper 32-bits of MSR value.
 809
 810   <b>Example usage</b>
 811   @code
 812   UINT64  Msr;
 813
 814   Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY);
 815   AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr);
 816   @endcode
 817 **/
 818 #define MSR_XEON_PHI_CORE_C6_RESIDENCY           0x000003FF
 819
 820
 821 /**
 822   Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
 823
 824   @param  ECX  MSR_XEON_PHI_MC3_CTL (0x0000040C)
 825   @param  EAX  Lower 32-bits of MSR value.
 826   @param  EDX  Upper 32-bits of MSR value.
 827
 828   <b>Example usage</b>
 829   @code
 830   UINT64  Msr;
 831
 832   Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_CTL);
 833   AsmWriteMsr64 (MSR_XEON_PHI_MC3_CTL, Msr);
 834   @endcode
 835 **/
 836 #define MSR_XEON_PHI_MC3_CTL                     0x0000040C
 837
 838
 839 /**
 840   Core. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
 841
 842   @param  ECX  MSR_XEON_PHI_MC3_STATUS (0x0000040D)
 843   @param  EAX  Lower 32-bits of MSR value.
 844   @param  EDX  Upper 32-bits of MSR value.
 845
 846   <b>Example usage</b>
 847   @code
 848   UINT64  Msr;
 849
 850   Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_STATUS);
 851   AsmWriteMsr64 (MSR_XEON_PHI_MC3_STATUS, Msr);
 852   @endcode
 853 **/
 854 #define MSR_XEON_PHI_MC3_STATUS                  0x0000040D
 855
 856
 857 /**
 858   Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs.".
 859
 860   @param  ECX  MSR_XEON_PHI_MC3_ADDR (0x0000040E)
 861   @param  EAX  Lower 32-bits of MSR value.
 862   @param  EDX  Upper 32-bits of MSR value.
 863
 864   <b>Example usage</b>
 865   @code
 866   UINT64  Msr;
 867
 868   Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_ADDR);
 869   AsmWriteMsr64 (MSR_XEON_PHI_MC3_ADDR, Msr);
 870   @endcode
 871 **/
 872 #define MSR_XEON_PHI_MC3_ADDR                    0x0000040E
 873
 874
 875 /**
 876   Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
 877
 878   @param  ECX  MSR_XEON_PHI_MC4_CTL (0x00000410)
 879   @param  EAX  Lower 32-bits of MSR value.
 880   @param  EDX  Upper 32-bits of MSR value.
 881
 882   <b>Example usage</b>
 883   @code
 884   UINT64  Msr;
 885
 886   Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_CTL);
 887   AsmWriteMsr64 (MSR_XEON_PHI_MC4_CTL, Msr);
 888   @endcode
 889 **/
 890 #define MSR_XEON_PHI_MC4_CTL                     0x00000410
 891
 892
 893 /**
 894   Core. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
 895
 896   @param  ECX  MSR_XEON_PHI_MC4_STATUS (0x00000411)
 897   @param  EAX  Lower 32-bits of MSR value.
 898   @param  EDX  Upper 32-bits of MSR value.
 899
 900   <b>Example usage</b>
 901   @code
 902   UINT64  Msr;
 903
 904   Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_STATUS);
 905   AsmWriteMsr64 (MSR_XEON_PHI_MC4_STATUS, Msr);
 906   @endcode
 907 **/
 908 #define MSR_XEON_PHI_MC4_STATUS                  0x00000411
 909
 910
 911 /**
 912   Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register
 913   is either not implemented or contains no address if the ADDRV flag in the
 914   MSR_MC4_STATUS register is clear. When not implemented in the processor, all
 915   reads and writes to this MSR will cause a general-protection exception.
 916
 917   @param  ECX  MSR_XEON_PHI_MC4_ADDR (0x00000412)
 918   @param  EAX  Lower 32-bits of MSR value.
 919   @param  EDX  Upper 32-bits of MSR value.
 920
 921   <b>Example usage</b>
 922   @code
 923   UINT64  Msr;
 924
 925   Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_ADDR);
 926   AsmWriteMsr64 (MSR_XEON_PHI_MC4_ADDR, Msr);
 927   @endcode
 928 **/
 929 #define MSR_XEON_PHI_MC4_ADDR                    0x00000412
 930
 931
 932 /**
 933   Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
 934
 935   @param  ECX  MSR_XEON_PHI_MC5_CTL (0x00000414)
 936   @param  EAX  Lower 32-bits of MSR value.
 937   @param  EDX  Upper 32-bits of MSR value.
 938
 939   <b>Example usage</b>
 940   @code
 941   UINT64  Msr;
 942
 943   Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_CTL);
 944   AsmWriteMsr64 (MSR_XEON_PHI_MC5_CTL, Msr);
 945   @endcode
 946 **/
 947 #define MSR_XEON_PHI_MC5_CTL                     0x00000414
 948
 949
 950 /**
 951   Package. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
 952
 953   @param  ECX  MSR_XEON_PHI_MC5_STATUS (0x00000415)
 954   @param  EAX  Lower 32-bits of MSR value.
 955   @param  EDX  Upper 32-bits of MSR value.
 956
 957   <b>Example usage</b>
 958   @code
 959   UINT64  Msr;
 960
 961   Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_STATUS);
 962   AsmWriteMsr64 (MSR_XEON_PHI_MC5_STATUS, Msr);
 963   @endcode
 964 **/
 965 #define MSR_XEON_PHI_MC5_STATUS                  0x00000415
 966
 967
 968 /**
 969   Package. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs.".
 970
 971   @param  ECX  MSR_XEON_PHI_MC5_ADDR (0x00000416)
 972   @param  EAX  Lower 32-bits of MSR value.
 973   @param  EDX  Upper 32-bits of MSR value.
 974
 975   <b>Example usage</b>
 976   @code
 977   UINT64  Msr;
 978
 979   Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_ADDR);
 980   AsmWriteMsr64 (MSR_XEON_PHI_MC5_ADDR, Msr);
 981   @endcode
 982 **/
 983 #define MSR_XEON_PHI_MC5_ADDR                    0x00000416
 984
 985
 986 /**
 987   Core. Capability Reporting Register of EPT and VPID (R/O)  See Table 35-2.
 988
 989   @param  ECX  MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
 990   @param  EAX  Lower 32-bits of MSR value.
 991   @param  EDX  Upper 32-bits of MSR value.
 992
 993   <b>Example usage</b>
 994   @code
 995   UINT64  Msr;
 996
 997   Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM);
 998   @endcode
 999 **/
1000 #define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM      0x0000048C
1001
1002
1003 /**
1004   Core. Capability Reporting Register of VM-function Controls (R/O) See Table
1005   35-2.
1006
1007   @param  ECX  MSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491)
1008   @param  EAX  Lower 32-bits of MSR value.
1009   @param  EDX  Upper 32-bits of MSR value.
1010
1011   <b>Example usage</b>
1012   @code
1013   UINT64  Msr;
1014
1015   Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC);
1016   @endcode
1017 **/
1018 #define MSR_XEON_PHI_IA32_VMX_FMFUNC             0x00000491
1019
1020
1021 /**
1022   Package. Unit Multipliers used in RAPL Interfaces (R/O).
1023
1024   @param  ECX  MSR_XEON_PHI_RAPL_POWER_UNIT (0x00000606)
1025   @param  EAX  Lower 32-bits of MSR value.
1026                Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.
1027   @param  EDX  Upper 32-bits of MSR value.
1028                Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.
1029
1030   <b>Example usage</b>
1031   @code
1032   MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER  Msr;
1033
1034   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT);
1035   @endcode
1036 **/
1037 #define MSR_XEON_PHI_RAPL_POWER_UNIT             0x00000606
1038
1039 /**
1040   MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT
1041 **/
1042 typedef union {
1043   ///
1044   /// Individual bit fields
1045   ///
1046   struct {
1047     ///
1048     /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
1049     ///
1050     UINT32  PowerUnits:4;
1051     UINT32  Reserved1:4;
1052     ///
1053     /// [Bits 12:8] Package. Energy Status Units Energy related information
1054     /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
1055     /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
1056     /// micro-joules).
1057     ///
1058     UINT32  EnergyStatusUnits:5;
1059     UINT32  Reserved2:3;
1060     ///
1061     /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
1062     /// Interfaces.".
1063     ///
1064     UINT32  TimeUnits:4;
1065     UINT32  Reserved3:12;
1066     UINT32  Reserved4:32;
1067   } Bits;
1068   ///
1069   /// All bit fields as a 32-bit value
1070   ///
1071   UINT32  Uint32;
1072   ///
1073   /// All bit fields as a 64-bit value
1074   ///
1075   UINT64  Uint64;
1076 } MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER;
1077
1078
1079 /**
1080   Package. Note: C-state values are processor specific C-state code names,
1081   unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2
1082   Residency Counter. (R/O).
1083
1084   @param  ECX  MSR_XEON_PHI_PKG_C2_RESIDENCY (0x0000060D)
1085   @param  EAX  Lower 32-bits of MSR value.
1086   @param  EDX  Upper 32-bits of MSR value.
1087
1088   <b>Example usage</b>
1089   @code
1090   UINT64  Msr;
1091
1092   Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY);
1093   AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr);
1094   @endcode
1095 **/
1096 #define MSR_XEON_PHI_PKG_C2_RESIDENCY            0x0000060D
1097
1098
1099 /**
1100   Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
1101   RAPL Domain.".
1102
1103   @param  ECX  MSR_XEON_PHI_PKG_POWER_LIMIT (0x00000610)
1104   @param  EAX  Lower 32-bits of MSR value.
1105   @param  EDX  Upper 32-bits of MSR value.
1106
1107   <b>Example usage</b>
1108   @code
1109   UINT64  Msr;
1110
1111   Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT);
1112   AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr);
1113   @endcode
1114 **/
1115 #define MSR_XEON_PHI_PKG_POWER_LIMIT             0x00000610
1116
1117
1118 /**
1119   Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1120
1121   @param  ECX  MSR_XEON_PHI_PKG_ENERGY_STATUS (0x00000611)
1122   @param  EAX  Lower 32-bits of MSR value.
1123   @param  EDX  Upper 32-bits of MSR value.
1124
1125   <b>Example usage</b>
1126   @code
1127   UINT64  Msr;
1128
1129   Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS);
1130   @endcode
1131 **/
1132 #define MSR_XEON_PHI_PKG_ENERGY_STATUS           0x00000611
1133
1134
1135 /**
1136   Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1137
1138   @param  ECX  MSR_XEON_PHI_PKG_PERF_STATUS (0x00000613)
1139   @param  EAX  Lower 32-bits of MSR value.
1140   @param  EDX  Upper 32-bits of MSR value.
1141
1142   <b>Example usage</b>
1143   @code
1144   UINT64  Msr;
1145
1146   Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS);
1147   @endcode
1148 **/
1149 #define MSR_XEON_PHI_PKG_PERF_STATUS             0x00000613
1150
1151
1152 /**
1153   Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL
1154   Domain.".
1155
1156   @param  ECX  MSR_XEON_PHI_PKG_POWER_INFO (0x00000614)
1157   @param  EAX  Lower 32-bits of MSR value.
1158   @param  EDX  Upper 32-bits of MSR value.
1159
1160   <b>Example usage</b>
1161   @code
1162   UINT64  Msr;
1163
1164   Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO);
1165   AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr);
1166   @endcode
1167 **/
1168 #define MSR_XEON_PHI_PKG_POWER_INFO              0x00000614
1169
1170
1171 /**
1172   Package. DRAM RAPL Power Limit Control (R/W)  See Section 14.9.5, "DRAM RAPL
1173   Domain.".
1174
1175   @param  ECX  MSR_XEON_PHI_DRAM_POWER_LIMIT (0x00000618)
1176   @param  EAX  Lower 32-bits of MSR value.
1177   @param  EDX  Upper 32-bits of MSR value.
1178
1179   <b>Example usage</b>
1180   @code
1181   UINT64  Msr;
1182
1183   Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT);
1184   AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr);
1185   @endcode
1186 **/
1187 #define MSR_XEON_PHI_DRAM_POWER_LIMIT            0x00000618
1188
1189
1190 /**
1191   Package. DRAM Energy Status (R/O)  See Section 14.9.5, "DRAM RAPL Domain.".
1192
1193   @param  ECX  MSR_XEON_PHI_DRAM_ENERGY_STATUS (0x00000619)
1194   @param  EAX  Lower 32-bits of MSR value.
1195   @param  EDX  Upper 32-bits of MSR value.
1196
1197   <b>Example usage</b>
1198   @code
1199   UINT64  Msr;
1200
1201   Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS);
1202   @endcode
1203 **/
1204 #define MSR_XEON_PHI_DRAM_ENERGY_STATUS          0x00000619
1205
1206
1207 /**
1208   Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
1209   RAPL Domain.".
1210
1211   @param  ECX  MSR_XEON_PHI_DRAM_PERF_STATUS (0x0000061B)
1212   @param  EAX  Lower 32-bits of MSR value.
1213   @param  EDX  Upper 32-bits of MSR value.
1214
1215   <b>Example usage</b>
1216   @code
1217   UINT64  Msr;
1218
1219   Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS);
1220   @endcode
1221 **/
1222 #define MSR_XEON_PHI_DRAM_PERF_STATUS            0x0000061B
1223
1224
1225 /**
1226   Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
1227
1228   @param  ECX  MSR_XEON_PHI_DRAM_POWER_INFO (0x0000061C)
1229   @param  EAX  Lower 32-bits of MSR value.
1230   @param  EDX  Upper 32-bits of MSR value.
1231
1232   <b>Example usage</b>
1233   @code
1234   UINT64  Msr;
1235
1236   Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO);
1237   AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr);
1238   @endcode
1239 **/
1240 #define MSR_XEON_PHI_DRAM_POWER_INFO             0x0000061C
1241
1242
1243 /**
1244   Package. PP0 RAPL Power Limit Control (R/W)  See Section 14.9.4, "PP0/PP1
1245   RAPL Domains.".
1246
1247   @param  ECX  MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638)
1248   @param  EAX  Lower 32-bits of MSR value.
1249   @param  EDX  Upper 32-bits of MSR value.
1250
1251   <b>Example usage</b>
1252   @code
1253   UINT64  Msr;
1254
1255   Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT);
1256   AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr);
1257   @endcode
1258 **/
1259 #define MSR_XEON_PHI_PP0_POWER_LIMIT             0x00000638
1260
1261
1262 /**
1263   Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
1264   Domains.".
1265
1266   @param  ECX  MSR_XEON_PHI_PP0_ENERGY_STATUS (0x00000639)
1267   @param  EAX  Lower 32-bits of MSR value.
1268   @param  EDX  Upper 32-bits of MSR value.
1269
1270   <b>Example usage</b>
1271   @code
1272   UINT64  Msr;
1273
1274   Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS);
1275   @endcode
1276 **/
1277 #define MSR_XEON_PHI_PP0_ENERGY_STATUS           0x00000639
1278
1279
1280 /**
1281   Package. Base TDP Ratio (R/O) See Table 35-20.
1282
1283   @param  ECX  MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)
1284   @param  EAX  Lower 32-bits of MSR value.
1285   @param  EDX  Upper 32-bits of MSR value.
1286
1287   <b>Example usage</b>
1288   @code
1289   UINT64  Msr;
1290
1291   Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL);
1292   @endcode
1293 **/
1294 #define MSR_XEON_PHI_CONFIG_TDP_NOMINAL          0x00000648
1295
1296
1297 /**
1298   Package. ConfigTDP Level 1 ratio and power level (R/O). See Table 35-20.
1299
1300   @param  ECX  MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)
1301   @param  EAX  Lower 32-bits of MSR value.
1302   @param  EDX  Upper 32-bits of MSR value.
1303
1304   <b>Example usage</b>
1305   @code
1306   UINT64  Msr;
1307
1308   Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1);
1309   @endcode
1310 **/
1311 #define MSR_XEON_PHI_CONFIG_TDP_LEVEL1           0x00000649
1312
1313
1314 /**
1315   Package. ConfigTDP Level 2 ratio and power level (R/O). See Table 35-20.
1316
1317   @param  ECX  MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)
1318   @param  EAX  Lower 32-bits of MSR value.
1319   @param  EDX  Upper 32-bits of MSR value.
1320
1321   <b>Example usage</b>
1322   @code
1323   UINT64  Msr;
1324
1325   Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2);
1326   @endcode
1327 **/
1328 #define MSR_XEON_PHI_CONFIG_TDP_LEVEL2           0x0000064A
1329
1330
1331 /**
1332   Package. ConfigTDP Control (R/W) See Table 35-20.
1333
1334   @param  ECX  MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)
1335   @param  EAX  Lower 32-bits of MSR value.
1336   @param  EDX  Upper 32-bits of MSR value.
1337
1338   <b>Example usage</b>
1339   @code
1340   UINT64  Msr;
1341
1342   Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL);
1343   AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr);
1344   @endcode
1345 **/
1346 #define MSR_XEON_PHI_CONFIG_TDP_CONTROL          0x0000064B
1347
1348
1349 /**
1350   Package. ConfigTDP Control (R/W) See Table 35-20.
1351
1352   @param  ECX  MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)
1353   @param  EAX  Lower 32-bits of MSR value.
1354   @param  EDX  Upper 32-bits of MSR value.
1355
1356   <b>Example usage</b>
1357   @code
1358   UINT64  Msr;
1359
1360   Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO);
1361   AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr);
1362   @endcode
1363 **/
1364 #define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO      0x0000064C
1365
1366
1367 /**
1368   Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
1369   refers to processor core frequency).
1370
1371   @param  ECX  MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS (0x00000690)
1372   @param  EAX  Lower 32-bits of MSR value.
1373                Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.
1374   @param  EDX  Upper 32-bits of MSR value.
1375                Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.
1376
1377   <b>Example usage</b>
1378   @code
1379   MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER  Msr;
1380
1381   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS);
1382   AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
1383   @endcode
1384 **/
1385 #define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS     0x00000690
1386
1387 /**
1388   MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS
1389 **/
1390 typedef union {
1391   ///
1392   /// Individual bit fields
1393   ///
1394   struct {
1395     ///
1396     /// [Bit 0] PROCHOT Status (R0).
1397     ///
1398     UINT32  PROCHOT_Status:1;
1399     ///
1400     /// [Bit 1] Thermal Status (R0).
1401     ///
1402     UINT32  ThermalStatus:1;
1403     UINT32  Reserved1:4;
1404     ///
1405     /// [Bit 6] VR Therm Alert Status (R0).
1406     ///
1407     UINT32  VRThermAlertStatus:1;
1408     UINT32  Reserved2:1;
1409     ///
1410     /// [Bit 8] Electrical Design Point Status (R0).
1411     ///
1412     UINT32  ElectricalDesignPointStatus:1;
1413     UINT32  Reserved3:23;
1414     UINT32  Reserved4:32;
1415   } Bits;
1416   ///
1417   /// All bit fields as a 32-bit value
1418   ///
1419   UINT32  Uint32;
1420   ///
1421   /// All bit fields as a 64-bit value
1422   ///
1423   UINT64  Uint64;
1424 } MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER;
1425
1426 #endif