UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/SupervisorTrapHandler.S

   1 /** @file
   2   RISC-V Processor supervisor mode trap handler
   3
   4   Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
   5
   6   SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #include <Base.h>
  11 #include "CpuExceptionHandlerLib.h"
  12
  13   .align 3
  14   .section .entry, "ax", %progbits
  15   .globl SupervisorModeTrap
  16 SupervisorModeTrap:
  17   addi sp, sp, -SMODE_TRAP_REGS_SIZE
  18
  19   /* Save all general regisers except SP */
  20   sd    t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
  21
  22   csrr  t0, CSR_SSTATUS
  23   and   t0, t0, (SSTATUS_SIE | SSTATUS_SPIE)
  24   sd    t0, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)
  25   csrr  t0, CSR_SEPC
  26   sd    t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)
  27   csrr  t0, CSR_SIE
  28   sd    t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)
  29   ld    t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
  30
  31   sd    ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)
  32   sd    gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)
  33   sd    tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)
  34   sd    t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)
  35   sd    t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)
  36   sd    s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)
  37   sd    s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)
  38   sd    a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)
  39   sd    a1, SMODE_TRAP_REGS_OFFSET(a1)(sp)
  40   sd    a2, SMODE_TRAP_REGS_OFFSET(a2)(sp)
  41   sd    a3, SMODE_TRAP_REGS_OFFSET(a3)(sp)
  42   sd    a4, SMODE_TRAP_REGS_OFFSET(a4)(sp)
  43   sd    a5, SMODE_TRAP_REGS_OFFSET(a5)(sp)
  44   sd    a6, SMODE_TRAP_REGS_OFFSET(a6)(sp)
  45   sd    a7, SMODE_TRAP_REGS_OFFSET(a7)(sp)
  46   sd    s2, SMODE_TRAP_REGS_OFFSET(s2)(sp)
  47   sd    s3, SMODE_TRAP_REGS_OFFSET(s3)(sp)
  48   sd    s4, SMODE_TRAP_REGS_OFFSET(s4)(sp)
  49   sd    s5, SMODE_TRAP_REGS_OFFSET(s5)(sp)
  50   sd    s6, SMODE_TRAP_REGS_OFFSET(s6)(sp)
  51   sd    s7, SMODE_TRAP_REGS_OFFSET(s7)(sp)
  52   sd    s8, SMODE_TRAP_REGS_OFFSET(s8)(sp)
  53   sd    s9, SMODE_TRAP_REGS_OFFSET(s9)(sp)
  54   sd    s10, SMODE_TRAP_REGS_OFFSET(s10)(sp)
  55   sd    s11, SMODE_TRAP_REGS_OFFSET(s11)(sp)
  56   sd    t3, SMODE_TRAP_REGS_OFFSET(t3)(sp)
  57   sd    t4, SMODE_TRAP_REGS_OFFSET(t4)(sp)
  58   sd    t5, SMODE_TRAP_REGS_OFFSET(t5)(sp)
  59   sd    t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)
  60
  61   /* Call to Supervisor mode trap handler in CpuExceptionHandlerLib.c */
  62   call  RiscVSupervisorModeTrapHandler
  63
  64   /* Restore all general regisers except SP */
  65   ld    ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)
  66   ld    gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)
  67   ld    tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)
  68   ld    t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)
  69   ld    s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)
  70   ld    s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)
  71   ld    a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)
  72   ld    a1, SMODE_TRAP_REGS_OFFSET(a1)(sp)
  73   ld    a2, SMODE_TRAP_REGS_OFFSET(a2)(sp)
  74   ld    a3, SMODE_TRAP_REGS_OFFSET(a3)(sp)
  75   ld    a4, SMODE_TRAP_REGS_OFFSET(a4)(sp)
  76   ld    a5, SMODE_TRAP_REGS_OFFSET(a5)(sp)
  77   ld    a6, SMODE_TRAP_REGS_OFFSET(a6)(sp)
  78   ld    a7, SMODE_TRAP_REGS_OFFSET(a7)(sp)
  79   ld    s2, SMODE_TRAP_REGS_OFFSET(s2)(sp)
  80   ld    s3, SMODE_TRAP_REGS_OFFSET(s3)(sp)
  81   ld    s4, SMODE_TRAP_REGS_OFFSET(s4)(sp)
  82   ld    s5, SMODE_TRAP_REGS_OFFSET(s5)(sp)
  83   ld    s6, SMODE_TRAP_REGS_OFFSET(s6)(sp)
  84   ld    s7, SMODE_TRAP_REGS_OFFSET(s7)(sp)
  85   ld    s8, SMODE_TRAP_REGS_OFFSET(s8)(sp)
  86   ld    s9, SMODE_TRAP_REGS_OFFSET(s9)(sp)
  87   ld    s10, SMODE_TRAP_REGS_OFFSET(s10)(sp)
  88   ld    s11, SMODE_TRAP_REGS_OFFSET(s11)(sp)
  89   ld    t3, SMODE_TRAP_REGS_OFFSET(t3)(sp)
  90   ld    t4, SMODE_TRAP_REGS_OFFSET(t4)(sp)
  91   ld    t5, SMODE_TRAP_REGS_OFFSET(t5)(sp)
  92   ld    t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)
  93
  94   ld    t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)
  95   csrw  CSR_SEPC, t0
  96   ld    t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)
  97   csrw  CSR_SIE, t0
  98   csrr  t0, CSR_SSTATUS
  99   ld    t1, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)
 100   or    t0, t0, t1
 101   csrw  CSR_SSTATUS, t0
 102   ld    t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)
 103   ld    t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
 104   addi  sp, sp, SMODE_TRAP_REGS_SIZE
 105   sret