4 This local APIC library instance supports xAPIC mode only.
6 Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
7 Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
9 SPDX-License-Identifier: BSD-2-Clause-Patent
13 #include <Register/Intel/Cpuid.h>
14 #include <Register/Amd/Cpuid.h>
15 #include <Register/Intel/Msr.h>
16 #include <Register/Intel/LocalApic.h>
18 #include <Library/BaseLib.h>
19 #include <Library/DebugLib.h>
20 #include <Library/LocalApicLib.h>
21 #include <Library/IoLib.h>
22 #include <Library/TimerLib.h>
23 #include <Library/PcdLib.h>
26 // Library internal functions
30 Determine if the standard CPU signature is "AuthenticAMD".
32 @retval TRUE The CPU signature matches.
33 @retval FALSE The CPU signature does not match.
37 StandardSignatureIsAuthenticAMD (
45 AsmCpuid (CPUID_SIGNATURE
, NULL
, &RegEbx
, &RegEcx
, &RegEdx
);
46 return (RegEbx
== CPUID_SIGNATURE_AUTHENTIC_AMD_EBX
&&
47 RegEcx
== CPUID_SIGNATURE_AUTHENTIC_AMD_ECX
&&
48 RegEdx
== CPUID_SIGNATURE_AUTHENTIC_AMD_EDX
);
52 Determine if the CPU supports the Local APIC Base Address MSR.
54 @retval TRUE The CPU supports the Local APIC Base Address MSR.
55 @retval FALSE The CPU does not support the Local APIC Base Address MSR.
59 LocalApicBaseAddressMsrSupported (
66 AsmCpuid (1, &RegEax
, NULL
, NULL
, NULL
);
67 FamilyId
= BitFieldRead32 (RegEax
, 8, 11);
68 if (FamilyId
== 0x04 || FamilyId
== 0x05) {
70 // CPUs with a FamilyId of 0x04 or 0x05 do not support the
71 // Local APIC Base Address MSR
79 Retrieve the base address of local APIC.
81 @return The base address of local APIC.
86 GetLocalApicBaseAddress (
90 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr
;
92 if (!LocalApicBaseAddressMsrSupported ()) {
94 // If CPU does not support Local APIC Base Address MSR, then retrieve
95 // Local APIC Base Address from PCD
97 return PcdGet32 (PcdCpuLocalApicBaseAddress
);
100 ApicBaseMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_APIC_BASE
);
102 return (UINTN
)(LShiftU64 ((UINT64
) ApicBaseMsr
.Bits
.ApicBaseHi
, 32)) +
103 (((UINTN
)ApicBaseMsr
.Bits
.ApicBase
) << 12);
107 Set the base address of local APIC.
109 If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
111 @param[in] BaseAddress Local APIC base address to be set.
116 SetLocalApicBaseAddress (
120 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr
;
122 ASSERT ((BaseAddress
& (SIZE_4KB
- 1)) == 0);
124 if (!LocalApicBaseAddressMsrSupported ()) {
126 // Ignore set request if the CPU does not support APIC Base Address MSR
131 ApicBaseMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_APIC_BASE
);
133 ApicBaseMsr
.Bits
.ApicBase
= (UINT32
) (BaseAddress
>> 12);
134 ApicBaseMsr
.Bits
.ApicBaseHi
= (UINT32
) (RShiftU64((UINT64
) BaseAddress
, 32));
136 AsmWriteMsr64 (MSR_IA32_APIC_BASE
, ApicBaseMsr
.Uint64
);
140 Read from a local APIC register.
142 This function reads from a local APIC register either in xAPIC or x2APIC mode.
143 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
144 accessed using multiple 32-bit loads or stores, so this function only performs
147 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
148 It must be 16-byte aligned.
150 @return 32-bit Value read from the register.
158 ASSERT ((MmioOffset
& 0xf) == 0);
159 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
161 return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset
);
165 Write to a local APIC register.
167 This function writes to a local APIC register either in xAPIC or x2APIC mode.
168 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
169 accessed using multiple 32-bit loads or stores, so this function only performs
172 if the register index is invalid or unsupported in current APIC mode, then ASSERT.
174 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
175 It must be 16-byte aligned.
176 @param Value Value to be written to the register.
185 ASSERT ((MmioOffset
& 0xf) == 0);
186 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
188 MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset
, Value
);
192 Send an IPI by writing to ICR.
194 This function returns after the IPI has been accepted by the target processor.
196 @param IcrLow 32-bit value to be written to the low half of ICR.
197 @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
205 LOCAL_APIC_ICR_LOW IcrLowReg
;
207 BOOLEAN InterruptState
;
209 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
210 ASSERT (ApicId
<= 0xff);
212 InterruptState
= SaveAndDisableInterrupts ();
215 // Save existing contents of ICR high 32 bits
217 IcrHigh
= ReadLocalApicReg (XAPIC_ICR_HIGH_OFFSET
);
220 // Wait for DeliveryStatus clear in case a previous IPI
221 // is still being sent
224 IcrLowReg
.Uint32
= ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET
);
225 } while (IcrLowReg
.Bits
.DeliveryStatus
!= 0);
228 // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
230 WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET
, ApicId
<< 24);
231 WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET
, IcrLow
);
234 // Wait for DeliveryStatus clear again
237 IcrLowReg
.Uint32
= ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET
);
238 } while (IcrLowReg
.Bits
.DeliveryStatus
!= 0);
241 // And restore old contents of ICR high
243 WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET
, IcrHigh
);
245 SetInterruptState (InterruptState
);
250 // Library API implementation functions
254 Get the current local APIC mode.
256 If local APIC is disabled, then ASSERT.
258 @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.
259 @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
269 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr
;
272 // Check to see if the CPU supports the APIC Base Address MSR
274 if (LocalApicBaseAddressMsrSupported ()) {
275 ApicBaseMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_APIC_BASE
);
277 // Local APIC should have been enabled
279 ASSERT (ApicBaseMsr
.Bits
.EN
!= 0);
280 ASSERT (ApicBaseMsr
.Bits
.EXTD
== 0);
284 return LOCAL_APIC_MODE_XAPIC
;
288 Set the current local APIC mode.
290 If the specified local APIC mode is not valid, then ASSERT.
291 If the specified local APIC mode can't be set as current, then ASSERT.
293 @param ApicMode APIC mode to be set.
295 @note This API must not be called from an interrupt handler or SMI handler.
296 It may result in unpredictable behavior.
304 ASSERT (ApicMode
== LOCAL_APIC_MODE_XAPIC
);
305 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
309 Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
311 In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
312 In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
313 the 32-bit local APIC ID is returned as initial APIC ID.
315 @return 32-bit initial local APIC ID of the executing processor.
324 UINT32 MaxCpuIdIndex
;
327 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
330 // Get the max index of basic CPUID
332 AsmCpuid (CPUID_SIGNATURE
, &MaxCpuIdIndex
, NULL
, NULL
, NULL
);
335 // If CPUID Leaf B is supported,
336 // And CPUID.0BH:EBX[15:0] reports a non-zero value,
337 // Then the initial 32-bit APIC ID = CPUID.0BH:EDX
338 // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]
340 if (MaxCpuIdIndex
>= CPUID_EXTENDED_TOPOLOGY
) {
341 AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY
, 0, NULL
, &RegEbx
, NULL
, &ApicId
);
342 if ((RegEbx
& (BIT16
- 1)) != 0) {
347 AsmCpuid (CPUID_VERSION_INFO
, NULL
, &RegEbx
, NULL
, NULL
);
352 Get the local APIC ID of the executing processor.
354 @return 32-bit local APIC ID of the executing processor.
364 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
366 if ((ApicId
= GetInitialApicId ()) < 0x100) {
368 // If the initial local APIC ID is less 0x100, read APIC ID from
369 // XAPIC_ID_OFFSET, otherwise return the initial local APIC ID.
371 ApicId
= ReadLocalApicReg (XAPIC_ID_OFFSET
);
378 Get the value of the local APIC version register.
380 @return the value of the local APIC version register.
388 return ReadLocalApicReg (XAPIC_VERSION_OFFSET
);
392 Send a Fixed IPI to a specified target processor.
394 This function returns after the IPI has been accepted by the target processor.
396 @param ApicId The local APIC ID of the target processor.
397 @param Vector The vector number of the interrupt being sent.
406 LOCAL_APIC_ICR_LOW IcrLow
;
409 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_FIXED
;
410 IcrLow
.Bits
.Level
= 1;
411 IcrLow
.Bits
.Vector
= Vector
;
412 SendIpi (IcrLow
.Uint32
, ApicId
);
416 Send a Fixed IPI to all processors excluding self.
418 This function returns after the IPI has been accepted by the target processors.
420 @param Vector The vector number of the interrupt being sent.
424 SendFixedIpiAllExcludingSelf (
428 LOCAL_APIC_ICR_LOW IcrLow
;
431 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_FIXED
;
432 IcrLow
.Bits
.Level
= 1;
433 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
434 IcrLow
.Bits
.Vector
= Vector
;
435 SendIpi (IcrLow
.Uint32
, 0);
439 Send a SMI IPI to a specified target processor.
441 This function returns after the IPI has been accepted by the target processor.
443 @param ApicId Specify the local APIC ID of the target processor.
451 LOCAL_APIC_ICR_LOW IcrLow
;
454 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_SMI
;
455 IcrLow
.Bits
.Level
= 1;
456 SendIpi (IcrLow
.Uint32
, ApicId
);
460 Send a SMI IPI to all processors excluding self.
462 This function returns after the IPI has been accepted by the target processors.
466 SendSmiIpiAllExcludingSelf (
470 LOCAL_APIC_ICR_LOW IcrLow
;
473 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_SMI
;
474 IcrLow
.Bits
.Level
= 1;
475 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
476 SendIpi (IcrLow
.Uint32
, 0);
480 Send an INIT IPI to a specified target processor.
482 This function returns after the IPI has been accepted by the target processor.
484 @param ApicId Specify the local APIC ID of the target processor.
492 LOCAL_APIC_ICR_LOW IcrLow
;
495 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_INIT
;
496 IcrLow
.Bits
.Level
= 1;
497 SendIpi (IcrLow
.Uint32
, ApicId
);
501 Send an INIT IPI to all processors excluding self.
503 This function returns after the IPI has been accepted by the target processors.
507 SendInitIpiAllExcludingSelf (
511 LOCAL_APIC_ICR_LOW IcrLow
;
514 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_INIT
;
515 IcrLow
.Bits
.Level
= 1;
516 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
517 SendIpi (IcrLow
.Uint32
, 0);
521 Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
523 This function returns after the IPI has been accepted by the target processor.
525 if StartupRoutine >= 1M, then ASSERT.
526 if StartupRoutine is not multiple of 4K, then ASSERT.
528 @param ApicId Specify the local APIC ID of the target processor.
529 @param StartupRoutine Points to a start-up routine which is below 1M physical
530 address and 4K aligned.
536 IN UINT32 StartupRoutine
539 LOCAL_APIC_ICR_LOW IcrLow
;
541 ASSERT (StartupRoutine
< 0x100000);
542 ASSERT ((StartupRoutine
& 0xfff) == 0);
544 SendInitIpi (ApicId
);
545 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds
));
547 IcrLow
.Bits
.Vector
= (StartupRoutine
>> 12);
548 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_STARTUP
;
549 IcrLow
.Bits
.Level
= 1;
550 SendIpi (IcrLow
.Uint32
, ApicId
);
551 if (!StandardSignatureIsAuthenticAMD ()) {
552 MicroSecondDelay (200);
553 SendIpi (IcrLow
.Uint32
, ApicId
);
558 Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
560 This function returns after the IPI has been accepted by the target processors.
562 if StartupRoutine >= 1M, then ASSERT.
563 if StartupRoutine is not multiple of 4K, then ASSERT.
565 @param StartupRoutine Points to a start-up routine which is below 1M physical
566 address and 4K aligned.
570 SendInitSipiSipiAllExcludingSelf (
571 IN UINT32 StartupRoutine
574 LOCAL_APIC_ICR_LOW IcrLow
;
576 ASSERT (StartupRoutine
< 0x100000);
577 ASSERT ((StartupRoutine
& 0xfff) == 0);
579 SendInitIpiAllExcludingSelf ();
580 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds
));
582 IcrLow
.Bits
.Vector
= (StartupRoutine
>> 12);
583 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_STARTUP
;
584 IcrLow
.Bits
.Level
= 1;
585 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
586 SendIpi (IcrLow
.Uint32
, 0);
587 if (!StandardSignatureIsAuthenticAMD ()) {
588 MicroSecondDelay (200);
589 SendIpi (IcrLow
.Uint32
, 0);
594 Initialize the state of the SoftwareEnable bit in the Local APIC
595 Spurious Interrupt Vector register.
597 @param Enable If TRUE, then set SoftwareEnable to 1
598 If FALSE, then set SoftwareEnable to 0.
603 InitializeLocalApicSoftwareEnable (
610 // Set local APIC software-enabled bit.
612 Svr
.Uint32
= ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
);
614 if (Svr
.Bits
.SoftwareEnable
== 0) {
615 Svr
.Bits
.SoftwareEnable
= 1;
616 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
, Svr
.Uint32
);
619 if (Svr
.Bits
.SoftwareEnable
== 1) {
620 Svr
.Bits
.SoftwareEnable
= 0;
621 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
, Svr
.Uint32
);
627 Programming Virtual Wire Mode.
629 This function programs the local APIC for virtual wire mode following
630 the example described in chapter A.3 of the MP 1.4 spec.
632 IOxAPIC is not involved in this type of virtual wire mode.
636 ProgramVirtualWireMode (
641 LOCAL_APIC_LVT_LINT Lint
;
644 // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
646 Svr
.Uint32
= ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
);
647 Svr
.Bits
.SpuriousVector
= 0xf;
648 Svr
.Bits
.SoftwareEnable
= 1;
649 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
, Svr
.Uint32
);
652 // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
654 Lint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET
);
655 Lint
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_EXTINT
;
656 Lint
.Bits
.InputPinPolarity
= 0;
657 Lint
.Bits
.TriggerMode
= 0;
659 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET
, Lint
.Uint32
);
662 // Program the LINT0 vector entry as NMI. Not masked, edge, active high.
664 Lint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET
);
665 Lint
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_NMI
;
666 Lint
.Bits
.InputPinPolarity
= 0;
667 Lint
.Bits
.TriggerMode
= 0;
669 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET
, Lint
.Uint32
);
673 Disable LINT0 & LINT1 interrupts.
675 This function sets the mask flag in the LVT LINT0 & LINT1 registers.
679 DisableLvtInterrupts (
683 LOCAL_APIC_LVT_LINT LvtLint
;
685 LvtLint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET
);
686 LvtLint
.Bits
.Mask
= 1;
687 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET
, LvtLint
.Uint32
);
689 LvtLint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET
);
690 LvtLint
.Bits
.Mask
= 1;
691 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET
, LvtLint
.Uint32
);
695 Read the initial count value from the init-count register.
697 @return The initial count value read from the init-count register.
701 GetApicTimerInitCount (
705 return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET
);
709 Read the current count value from the current-count register.
711 @return The current count value read from the current-count register.
715 GetApicTimerCurrentCount (
719 return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET
);
723 Initialize the local APIC timer.
725 The local APIC timer is initialized and enabled.
727 @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
728 If it is 0, then use the current divide value in the DCR.
729 @param InitCount The initial count value.
730 @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
731 @param Vector The timer interrupt vector number.
735 InitializeApicTimer (
736 IN UINTN DivideValue
,
738 IN BOOLEAN PeriodicMode
,
743 LOCAL_APIC_LVT_TIMER LvtTimer
;
747 // Ensure local APIC is in software-enabled state.
749 InitializeLocalApicSoftwareEnable (TRUE
);
752 // Program init-count register.
754 WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET
, InitCount
);
756 if (DivideValue
!= 0) {
757 ASSERT (DivideValue
<= 128);
758 ASSERT (DivideValue
== GetPowerOfTwo32((UINT32
)DivideValue
));
759 Divisor
= (UINT32
)((HighBitSet32 ((UINT32
)DivideValue
) - 1) & 0x7);
761 Dcr
.Uint32
= ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET
);
762 Dcr
.Bits
.DivideValue1
= (Divisor
& 0x3);
763 Dcr
.Bits
.DivideValue2
= (Divisor
>> 2);
764 WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET
, Dcr
.Uint32
);
768 // Enable APIC timer interrupt with specified timer mode.
770 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
772 LvtTimer
.Bits
.TimerMode
= 1;
774 LvtTimer
.Bits
.TimerMode
= 0;
776 LvtTimer
.Bits
.Mask
= 0;
777 LvtTimer
.Bits
.Vector
= Vector
;
778 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET
, LvtTimer
.Uint32
);
782 Get the state of the local APIC timer.
784 This function will ASSERT if the local APIC is not software enabled.
786 @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
787 @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
788 @param Vector Return the timer interrupt vector number.
793 OUT UINTN
*DivideValue OPTIONAL
,
794 OUT BOOLEAN
*PeriodicMode OPTIONAL
,
795 OUT UINT8
*Vector OPTIONAL
800 LOCAL_APIC_LVT_TIMER LvtTimer
;
803 // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt
805 // This bit will be 1, if local APIC is software enabled.
807 ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET
) & BIT8
) != 0);
809 if (DivideValue
!= NULL
) {
810 Dcr
.Uint32
= ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET
);
811 Divisor
= Dcr
.Bits
.DivideValue1
| (Dcr
.Bits
.DivideValue2
<< 2);
812 Divisor
= (Divisor
+ 1) & 0x7;
813 *DivideValue
= ((UINTN
)1) << Divisor
;
816 if (PeriodicMode
!= NULL
|| Vector
!= NULL
) {
817 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
818 if (PeriodicMode
!= NULL
) {
819 if (LvtTimer
.Bits
.TimerMode
== 1) {
820 *PeriodicMode
= TRUE
;
822 *PeriodicMode
= FALSE
;
825 if (Vector
!= NULL
) {
826 *Vector
= (UINT8
) LvtTimer
.Bits
.Vector
;
832 Enable the local APIC timer interrupt.
836 EnableApicTimerInterrupt (
840 LOCAL_APIC_LVT_TIMER LvtTimer
;
842 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
843 LvtTimer
.Bits
.Mask
= 0;
844 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET
, LvtTimer
.Uint32
);
848 Disable the local APIC timer interrupt.
852 DisableApicTimerInterrupt (
856 LOCAL_APIC_LVT_TIMER LvtTimer
;
858 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
859 LvtTimer
.Bits
.Mask
= 1;
860 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET
, LvtTimer
.Uint32
);
864 Get the local APIC timer interrupt state.
866 @retval TRUE The local APIC timer interrupt is enabled.
867 @retval FALSE The local APIC timer interrupt is disabled.
871 GetApicTimerInterruptState (
875 LOCAL_APIC_LVT_TIMER LvtTimer
;
877 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
878 return (BOOLEAN
)(LvtTimer
.Bits
.Mask
== 0);
882 Send EOI to the local APIC.
890 WriteLocalApicReg (XAPIC_EOI_OFFSET
, 0);
894 Get the 32-bit address that a device should use to send a Message Signaled
895 Interrupt (MSI) to the Local APIC of the currently executing processor.
897 @return 32-bit address used to send an MSI to the Local APIC.
905 LOCAL_APIC_MSI_ADDRESS MsiAddress
;
908 // Return address for an MSI interrupt to be delivered only to the APIC ID
909 // of the currently executing processor.
911 MsiAddress
.Uint32
= 0;
912 MsiAddress
.Bits
.BaseAddress
= 0xFEE;
913 MsiAddress
.Bits
.DestinationId
= GetApicId ();
914 return MsiAddress
.Uint32
;
918 Get the 64-bit data value that a device should use to send a Message Signaled
919 Interrupt (MSI) to the Local APIC of the currently executing processor.
921 If Vector is not in range 0x10..0xFE, then ASSERT().
922 If DeliveryMode is not supported, then ASSERT().
924 @param Vector The 8-bit interrupt vector associated with the MSI.
925 Must be in the range 0x10..0xFE
926 @param DeliveryMode A 3-bit value that specifies how the recept of the MSI
927 is handled. The only supported values are:
928 0: LOCAL_APIC_DELIVERY_MODE_FIXED
929 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
930 2: LOCAL_APIC_DELIVERY_MODE_SMI
931 4: LOCAL_APIC_DELIVERY_MODE_NMI
932 5: LOCAL_APIC_DELIVERY_MODE_INIT
933 7: LOCAL_APIC_DELIVERY_MODE_EXTINT
935 @param LevelTriggered TRUE specifies a level triggered interrupt.
936 FALSE specifies an edge triggered interrupt.
937 @param AssertionLevel Ignored if LevelTriggered is FALSE.
938 TRUE specifies a level triggered interrupt that active
939 when the interrupt line is asserted.
940 FALSE specifies a level triggered interrupt that active
941 when the interrupt line is deasserted.
943 @return 64-bit data value used to send an MSI to the Local APIC.
949 IN UINTN DeliveryMode
,
950 IN BOOLEAN LevelTriggered
,
951 IN BOOLEAN AssertionLevel
954 LOCAL_APIC_MSI_DATA MsiData
;
956 ASSERT (Vector
>= 0x10 && Vector
<= 0xFE);
957 ASSERT (DeliveryMode
< 8 && DeliveryMode
!= 6 && DeliveryMode
!= 3);
960 MsiData
.Bits
.Vector
= Vector
;
961 MsiData
.Bits
.DeliveryMode
= (UINT32
)DeliveryMode
;
962 if (LevelTriggered
) {
963 MsiData
.Bits
.TriggerMode
= 1;
964 if (AssertionLevel
) {
965 MsiData
.Bits
.Level
= 1;
968 return MsiData
.Uint64
;
972 Get Package ID/Core ID/Thread ID of a processor.
974 The algorithm assumes the target system has symmetry across physical
975 package boundaries with respect to the number of logical processors
976 per package, number of cores per package.
978 @param[in] InitialApicId Initial APIC ID of the target logical processor.
979 @param[out] Package Returns the processor package ID.
980 @param[out] Core Returns the processor core ID.
981 @param[out] Thread Returns the processor thread ID.
985 GetProcessorLocationByApicId (
986 IN UINT32 InitialApicId
,
987 OUT UINT32
*Package OPTIONAL
,
988 OUT UINT32
*Core OPTIONAL
,
989 OUT UINT32
*Thread OPTIONAL
992 BOOLEAN TopologyLeafSupported
;
993 CPUID_VERSION_INFO_EBX VersionInfoEbx
;
994 CPUID_VERSION_INFO_EDX VersionInfoEdx
;
995 CPUID_CACHE_PARAMS_EAX CacheParamsEax
;
996 CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax
;
997 CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx
;
998 CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx
;
999 CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx
;
1000 CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx
;
1001 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx
;
1002 UINT32 MaxStandardCpuIdIndex
;
1003 UINT32 MaxExtendedCpuIdIndex
;
1006 UINT32 MaxLogicProcessorsPerPackage
;
1007 UINT32 MaxCoresPerPackage
;
1012 // Check if the processor is capable of supporting more than one logical processor.
1014 AsmCpuid (CPUID_VERSION_INFO
, NULL
, NULL
, NULL
, &VersionInfoEdx
.Uint32
);
1015 if (VersionInfoEdx
.Bits
.HTT
== 0) {
1016 if (Thread
!= NULL
) {
1022 if (Package
!= NULL
) {
1029 // Assume three-level mapping of APIC ID: Package|Core|Thread.
1035 // Get max index of CPUID
1037 AsmCpuid (CPUID_SIGNATURE
, &MaxStandardCpuIdIndex
, NULL
, NULL
, NULL
);
1038 AsmCpuid (CPUID_EXTENDED_FUNCTION
, &MaxExtendedCpuIdIndex
, NULL
, NULL
, NULL
);
1041 // If the extended topology enumeration leaf is available, it
1042 // is the preferred mechanism for enumerating topology.
1044 TopologyLeafSupported
= FALSE
;
1045 if (MaxStandardCpuIdIndex
>= CPUID_EXTENDED_TOPOLOGY
) {
1047 CPUID_EXTENDED_TOPOLOGY
,
1049 &ExtendedTopologyEax
.Uint32
,
1050 &ExtendedTopologyEbx
.Uint32
,
1051 &ExtendedTopologyEcx
.Uint32
,
1055 // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
1056 // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
1057 // supported on that processor.
1059 if (ExtendedTopologyEbx
.Uint32
!= 0) {
1060 TopologyLeafSupported
= TRUE
;
1063 // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
1064 // the SMT sub-field of x2APIC ID.
1066 LevelType
= ExtendedTopologyEcx
.Bits
.LevelType
;
1067 ASSERT (LevelType
== CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT
);
1068 ThreadBits
= ExtendedTopologyEax
.Bits
.ApicIdShift
;
1071 // Software must not assume any "level type" encoding
1072 // value to be related to any sub-leaf index, except sub-leaf 0.
1077 CPUID_EXTENDED_TOPOLOGY
,
1079 &ExtendedTopologyEax
.Uint32
,
1081 &ExtendedTopologyEcx
.Uint32
,
1084 LevelType
= ExtendedTopologyEcx
.Bits
.LevelType
;
1085 if (LevelType
== CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE
) {
1086 CoreBits
= ExtendedTopologyEax
.Bits
.ApicIdShift
- ThreadBits
;
1090 } while (LevelType
!= CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID
);
1094 if (!TopologyLeafSupported
) {
1096 // Get logical processor count
1098 AsmCpuid (CPUID_VERSION_INFO
, NULL
, &VersionInfoEbx
.Uint32
, NULL
, NULL
);
1099 MaxLogicProcessorsPerPackage
= VersionInfoEbx
.Bits
.MaximumAddressableIdsForLogicalProcessors
;
1102 // Assume single-core processor
1104 MaxCoresPerPackage
= 1;
1107 // Check for topology extensions on AMD processor
1109 if (StandardSignatureIsAuthenticAMD()) {
1110 if (MaxExtendedCpuIdIndex
>= CPUID_AMD_PROCESSOR_TOPOLOGY
) {
1111 AsmCpuid (CPUID_EXTENDED_CPU_SIG
, NULL
, NULL
, &AmdExtendedCpuSigEcx
.Uint32
, NULL
);
1112 if (AmdExtendedCpuSigEcx
.Bits
.TopologyExtensions
!= 0) {
1114 // Account for max possible thread count to decode ApicId
1116 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE
, NULL
, NULL
, &AmdVirPhyAddressSizeEcx
.Uint32
, NULL
);
1117 MaxLogicProcessorsPerPackage
= 1 << AmdVirPhyAddressSizeEcx
.Bits
.ApicIdCoreIdSize
;
1120 // Get cores per processor package
1122 AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY
, NULL
, &AmdProcessorTopologyEbx
.Uint32
, NULL
, NULL
);
1123 MaxCoresPerPackage
= MaxLogicProcessorsPerPackage
/ (AmdProcessorTopologyEbx
.Bits
.ThreadsPerCore
+ 1);
1129 // Extract core count based on CACHE information
1131 if (MaxStandardCpuIdIndex
>= CPUID_CACHE_PARAMS
) {
1132 AsmCpuidEx (CPUID_CACHE_PARAMS
, 0, &CacheParamsEax
.Uint32
, NULL
, NULL
, NULL
);
1133 if (CacheParamsEax
.Uint32
!= 0) {
1134 MaxCoresPerPackage
= CacheParamsEax
.Bits
.MaximumAddressableIdsForLogicalProcessors
+ 1;
1139 ThreadBits
= (UINTN
)(HighBitSet32(MaxLogicProcessorsPerPackage
/ MaxCoresPerPackage
- 1) + 1);
1140 CoreBits
= (UINTN
)(HighBitSet32(MaxCoresPerPackage
- 1) + 1);
1143 if (Thread
!= NULL
) {
1144 *Thread
= InitialApicId
& ((1 << ThreadBits
) - 1);
1147 *Core
= (InitialApicId
>> ThreadBits
) & ((1 << CoreBits
) - 1);
1149 if (Package
!= NULL
) {
1150 *Package
= (InitialApicId
>> (ThreadBits
+ CoreBits
));
1155 Get Package ID/Die ID/Tile ID/Module ID/Core ID/Thread ID of a processor.
1157 The algorithm assumes the target system has symmetry across physical
1158 package boundaries with respect to the number of threads per core, number of
1159 cores per module, number of modules per tile, number of tiles per die, number
1160 of dies per package.
1162 @param[in] InitialApicId Initial APIC ID of the target logical processor.
1163 @param[out] Package Returns the processor package ID.
1164 @param[out] Die Returns the processor die ID.
1165 @param[out] Tile Returns the processor tile ID.
1166 @param[out] Module Returns the processor module ID.
1167 @param[out] Core Returns the processor core ID.
1168 @param[out] Thread Returns the processor thread ID.
1172 GetProcessorLocation2ByApicId (
1173 IN UINT32 InitialApicId
,
1174 OUT UINT32
*Package OPTIONAL
,
1175 OUT UINT32
*Die OPTIONAL
,
1176 OUT UINT32
*Tile OPTIONAL
,
1177 OUT UINT32
*Module OPTIONAL
,
1178 OUT UINT32
*Core OPTIONAL
,
1179 OUT UINT32
*Thread OPTIONAL
1182 CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax
;
1183 CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx
;
1184 UINT32 MaxStandardCpuIdIndex
;
1187 UINT32 Bits
[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE
+ 2];
1188 UINT32
*Location
[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE
+ 2];
1190 for (LevelType
= 0; LevelType
< ARRAY_SIZE (Bits
); LevelType
++) {
1191 Bits
[LevelType
] = 0;
1195 // Get max index of CPUID
1197 AsmCpuid (CPUID_SIGNATURE
, &MaxStandardCpuIdIndex
, NULL
, NULL
, NULL
);
1198 if (MaxStandardCpuIdIndex
< CPUID_V2_EXTENDED_TOPOLOGY
) {
1205 if (Module
!= NULL
) {
1208 GetProcessorLocationByApicId (InitialApicId
, Package
, Core
, Thread
);
1213 // If the V2 extended topology enumeration leaf is available, it
1214 // is the preferred mechanism for enumerating topology.
1216 for (Index
= 0; ; Index
++) {
1218 CPUID_V2_EXTENDED_TOPOLOGY
,
1220 &ExtendedTopologyEax
.Uint32
,
1222 &ExtendedTopologyEcx
.Uint32
,
1226 LevelType
= ExtendedTopologyEcx
.Bits
.LevelType
;
1229 // first level reported should be SMT.
1231 ASSERT ((Index
!= 0) || (LevelType
== CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT
));
1232 if (LevelType
== CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID
) {
1235 ASSERT (LevelType
< ARRAY_SIZE (Bits
));
1236 Bits
[LevelType
] = ExtendedTopologyEax
.Bits
.ApicIdShift
;
1239 for (LevelType
= CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE
; LevelType
< ARRAY_SIZE (Bits
); LevelType
++) {
1241 // If there are more levels between level-1 (low-level) and level-2 (high-level), the unknown levels will be ignored
1242 // and treated as an extension of the last known level (i.e., level-1 in this case).
1244 if (Bits
[LevelType
] == 0) {
1245 Bits
[LevelType
] = Bits
[LevelType
- 1];
1249 Location
[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE
+ 1] = Package
;
1250 Location
[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE
] = Die
;
1251 Location
[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE
] = Tile
;
1252 Location
[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE
] = Module
;
1253 Location
[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE
] = Core
;
1254 Location
[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT
] = Thread
;
1256 Bits
[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE
+ 1] = 32;
1258 for ( LevelType
= CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT
1259 ; LevelType
<= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE
+ 1
1262 if (Location
[LevelType
] != NULL
) {
1264 // Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique
1265 // topology ID of the next level type.
1267 *Location
[LevelType
] = InitialApicId
>> Bits
[LevelType
- 1];
1270 // Bits[i] - Bits[i-1] holds the number of bits for the next ONE level type.
1272 *Location
[LevelType
] &= (1 << (Bits
[LevelType
] - Bits
[LevelType
- 1])) - 1;