4 This local APIC library instance supports xAPIC mode only.
6 Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include <Register/LocalApic.h>
19 #include <Library/BaseLib.h>
20 #include <Library/DebugLib.h>
21 #include <Library/LocalApicLib.h>
22 #include <Library/IoLib.h>
23 #include <Library/TimerLib.h>
24 #include <Library/PcdLib.h>
27 // Library internal functions
31 Determine if the CPU supports the Local APIC Base Address MSR.
33 @retval TRUE The CPU supports the Local APIC Base Address MSR.
34 @retval FALSE The CPU does not support the Local APIC Base Address MSR.
38 LocalApicBaseAddressMsrSupported (
45 AsmCpuid (1, &RegEax
, NULL
, NULL
, NULL
);
46 FamilyId
= BitFieldRead32 (RegEax
, 8, 11);
47 if (FamilyId
== 0x04 || FamilyId
== 0x05) {
49 // CPUs with a FamilyId of 0x04 or 0x05 do not support the
50 // Local APIC Base Address MSR
58 Retrieve the base address of local APIC.
60 @return The base address of local APIC.
65 GetLocalApicBaseAddress (
69 MSR_IA32_APIC_BASE ApicBaseMsr
;
71 if (!LocalApicBaseAddressMsrSupported ()) {
73 // If CPU does not support Local APIC Base Address MSR, then retrieve
74 // Local APIC Base Address from PCD
76 return PcdGet32 (PcdCpuLocalApicBaseAddress
);
79 ApicBaseMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS
);
81 return (UINTN
)(LShiftU64 ((UINT64
) ApicBaseMsr
.Bits
.ApicBaseHigh
, 32)) +
82 (((UINTN
)ApicBaseMsr
.Bits
.ApicBaseLow
) << 12);
86 Set the base address of local APIC.
88 If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
90 @param[in] BaseAddress Local APIC base address to be set.
95 SetLocalApicBaseAddress (
99 MSR_IA32_APIC_BASE ApicBaseMsr
;
101 ASSERT ((BaseAddress
& (SIZE_4KB
- 1)) == 0);
103 if (!LocalApicBaseAddressMsrSupported ()) {
105 // Ignore set request if the CPU does not support APIC Base Address MSR
110 ApicBaseMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS
);
112 ApicBaseMsr
.Bits
.ApicBaseLow
= (UINT32
) (BaseAddress
>> 12);
113 ApicBaseMsr
.Bits
.ApicBaseHigh
= (UINT32
) (RShiftU64((UINT64
) BaseAddress
, 32));
115 AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS
, ApicBaseMsr
.Uint64
);
119 Read from a local APIC register.
121 This function reads from a local APIC register either in xAPIC or x2APIC mode.
122 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
123 accessed using multiple 32-bit loads or stores, so this function only performs
126 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
127 It must be 16-byte aligned.
129 @return 32-bit Value read from the register.
137 ASSERT ((MmioOffset
& 0xf) == 0);
138 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
140 return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset
);
144 Write to a local APIC register.
146 This function writes to a local APIC register either in xAPIC or x2APIC mode.
147 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
148 accessed using multiple 32-bit loads or stores, so this function only performs
151 if the register index is invalid or unsupported in current APIC mode, then ASSERT.
153 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
154 It must be 16-byte aligned.
155 @param Value Value to be written to the register.
164 ASSERT ((MmioOffset
& 0xf) == 0);
165 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
167 MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset
, Value
);
171 Send an IPI by writing to ICR.
173 This function returns after the IPI has been accepted by the target processor.
175 @param IcrLow 32-bit value to be written to the low half of ICR.
176 @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
184 LOCAL_APIC_ICR_LOW IcrLowReg
;
186 BOOLEAN InterruptState
;
188 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
189 ASSERT (ApicId
<= 0xff);
191 InterruptState
= SaveAndDisableInterrupts ();
194 // Save existing contents of ICR high 32 bits
196 IcrHigh
= ReadLocalApicReg (XAPIC_ICR_HIGH_OFFSET
);
199 // Wait for DeliveryStatus clear in case a previous IPI
200 // is still being sent
203 IcrLowReg
.Uint32
= ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET
);
204 } while (IcrLowReg
.Bits
.DeliveryStatus
!= 0);
207 // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
209 WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET
, ApicId
<< 24);
210 WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET
, IcrLow
);
213 // Wait for DeliveryStatus clear again
216 IcrLowReg
.Uint32
= ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET
);
217 } while (IcrLowReg
.Bits
.DeliveryStatus
!= 0);
220 // And restore old contents of ICR high
222 WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET
, IcrHigh
);
224 SetInterruptState (InterruptState
);
229 // Library API implementation functions
233 Get the current local APIC mode.
235 If local APIC is disabled, then ASSERT.
237 @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.
238 @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
248 MSR_IA32_APIC_BASE ApicBaseMsr
;
251 // Check to see if the CPU supports the APIC Base Address MSR
253 if (LocalApicBaseAddressMsrSupported ()) {
254 ApicBaseMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS
);
256 // Local APIC should have been enabled
258 ASSERT (ApicBaseMsr
.Bits
.En
!= 0);
259 ASSERT (ApicBaseMsr
.Bits
.Extd
== 0);
263 return LOCAL_APIC_MODE_XAPIC
;
267 Set the current local APIC mode.
269 If the specified local APIC mode is not valid, then ASSERT.
270 If the specified local APIC mode can't be set as current, then ASSERT.
272 @param ApicMode APIC mode to be set.
274 @note This API must not be called from an interrupt handler or SMI handler.
275 It may result in unpredictable behavior.
283 ASSERT (ApicMode
== LOCAL_APIC_MODE_XAPIC
);
284 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
288 Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
290 In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
291 In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
292 the 32-bit local APIC ID is returned as initial APIC ID.
294 @return 32-bit initial local APIC ID of the executing processor.
303 UINT32 MaxCpuIdIndex
;
306 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
309 // Get the max index of basic CPUID
311 AsmCpuid (CPUID_SIGNATURE
, &MaxCpuIdIndex
, NULL
, NULL
, NULL
);
314 // If CPUID Leaf B is supported,
315 // Then the initial 32-bit APIC ID = CPUID.0BH:EDX
316 // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]
318 if (MaxCpuIdIndex
>= CPUID_EXTENDED_TOPOLOGY
) {
319 AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY
, 0, NULL
, NULL
, NULL
, &ApicId
);
323 AsmCpuid (CPUID_VERSION_INFO
, NULL
, &RegEbx
, NULL
, NULL
);
328 Get the local APIC ID of the executing processor.
330 @return 32-bit local APIC ID of the executing processor.
340 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
342 if ((ApicId
= GetInitialApicId ()) < 0x100) {
344 // If the initial local APIC ID is less 0x100, read APIC ID from
345 // XAPIC_ID_OFFSET, otherwise return the initial local APIC ID.
347 ApicId
= ReadLocalApicReg (XAPIC_ID_OFFSET
);
354 Get the value of the local APIC version register.
356 @return the value of the local APIC version register.
364 return ReadLocalApicReg (XAPIC_VERSION_OFFSET
);
368 Send a Fixed IPI to a specified target processor.
370 This function returns after the IPI has been accepted by the target processor.
372 @param ApicId The local APIC ID of the target processor.
373 @param Vector The vector number of the interrupt being sent.
382 LOCAL_APIC_ICR_LOW IcrLow
;
385 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_FIXED
;
386 IcrLow
.Bits
.Level
= 1;
387 IcrLow
.Bits
.Vector
= Vector
;
388 SendIpi (IcrLow
.Uint32
, ApicId
);
392 Send a Fixed IPI to all processors excluding self.
394 This function returns after the IPI has been accepted by the target processors.
396 @param Vector The vector number of the interrupt being sent.
400 SendFixedIpiAllExcludingSelf (
404 LOCAL_APIC_ICR_LOW IcrLow
;
407 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_FIXED
;
408 IcrLow
.Bits
.Level
= 1;
409 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
410 IcrLow
.Bits
.Vector
= Vector
;
411 SendIpi (IcrLow
.Uint32
, 0);
415 Send a SMI IPI to a specified target processor.
417 This function returns after the IPI has been accepted by the target processor.
419 @param ApicId Specify the local APIC ID of the target processor.
427 LOCAL_APIC_ICR_LOW IcrLow
;
430 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_SMI
;
431 IcrLow
.Bits
.Level
= 1;
432 SendIpi (IcrLow
.Uint32
, ApicId
);
436 Send a SMI IPI to all processors excluding self.
438 This function returns after the IPI has been accepted by the target processors.
442 SendSmiIpiAllExcludingSelf (
446 LOCAL_APIC_ICR_LOW IcrLow
;
449 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_SMI
;
450 IcrLow
.Bits
.Level
= 1;
451 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
452 SendIpi (IcrLow
.Uint32
, 0);
456 Send an INIT IPI to a specified target processor.
458 This function returns after the IPI has been accepted by the target processor.
460 @param ApicId Specify the local APIC ID of the target processor.
468 LOCAL_APIC_ICR_LOW IcrLow
;
471 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_INIT
;
472 IcrLow
.Bits
.Level
= 1;
473 SendIpi (IcrLow
.Uint32
, ApicId
);
477 Send an INIT IPI to all processors excluding self.
479 This function returns after the IPI has been accepted by the target processors.
483 SendInitIpiAllExcludingSelf (
487 LOCAL_APIC_ICR_LOW IcrLow
;
490 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_INIT
;
491 IcrLow
.Bits
.Level
= 1;
492 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
493 SendIpi (IcrLow
.Uint32
, 0);
497 Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
499 This function returns after the IPI has been accepted by the target processor.
501 if StartupRoutine >= 1M, then ASSERT.
502 if StartupRoutine is not multiple of 4K, then ASSERT.
504 @param ApicId Specify the local APIC ID of the target processor.
505 @param StartupRoutine Points to a start-up routine which is below 1M physical
506 address and 4K aligned.
512 IN UINT32 StartupRoutine
515 LOCAL_APIC_ICR_LOW IcrLow
;
517 ASSERT (StartupRoutine
< 0x100000);
518 ASSERT ((StartupRoutine
& 0xfff) == 0);
520 SendInitIpi (ApicId
);
521 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds
));
523 IcrLow
.Bits
.Vector
= (StartupRoutine
>> 12);
524 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_STARTUP
;
525 IcrLow
.Bits
.Level
= 1;
526 SendIpi (IcrLow
.Uint32
, ApicId
);
527 MicroSecondDelay (200);
528 SendIpi (IcrLow
.Uint32
, ApicId
);
532 Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
534 This function returns after the IPI has been accepted by the target processors.
536 if StartupRoutine >= 1M, then ASSERT.
537 if StartupRoutine is not multiple of 4K, then ASSERT.
539 @param StartupRoutine Points to a start-up routine which is below 1M physical
540 address and 4K aligned.
544 SendInitSipiSipiAllExcludingSelf (
545 IN UINT32 StartupRoutine
548 LOCAL_APIC_ICR_LOW IcrLow
;
550 ASSERT (StartupRoutine
< 0x100000);
551 ASSERT ((StartupRoutine
& 0xfff) == 0);
553 SendInitIpiAllExcludingSelf ();
554 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds
));
556 IcrLow
.Bits
.Vector
= (StartupRoutine
>> 12);
557 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_STARTUP
;
558 IcrLow
.Bits
.Level
= 1;
559 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
560 SendIpi (IcrLow
.Uint32
, 0);
561 MicroSecondDelay (200);
562 SendIpi (IcrLow
.Uint32
, 0);
566 Programming Virtual Wire Mode.
568 This function programs the local APIC for virtual wire mode following
569 the example described in chapter A.3 of the MP 1.4 spec.
571 IOxAPIC is not involved in this type of virtual wire mode.
575 ProgramVirtualWireMode (
580 LOCAL_APIC_LVT_LINT Lint
;
583 // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
585 Svr
.Uint32
= ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
);
586 Svr
.Bits
.SpuriousVector
= 0xf;
587 Svr
.Bits
.SoftwareEnable
= 1;
588 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
, Svr
.Uint32
);
591 // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
593 Lint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET
);
594 Lint
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_EXTINT
;
595 Lint
.Bits
.InputPinPolarity
= 0;
596 Lint
.Bits
.TriggerMode
= 0;
598 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET
, Lint
.Uint32
);
601 // Program the LINT0 vector entry as NMI. Not masked, edge, active high.
603 Lint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET
);
604 Lint
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_NMI
;
605 Lint
.Bits
.InputPinPolarity
= 0;
606 Lint
.Bits
.TriggerMode
= 0;
608 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET
, Lint
.Uint32
);
612 Disable LINT0 & LINT1 interrupts.
614 This function sets the mask flag in the LVT LINT0 & LINT1 registers.
618 DisableLvtInterrupts (
622 LOCAL_APIC_LVT_LINT LvtLint
;
624 LvtLint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET
);
625 LvtLint
.Bits
.Mask
= 1;
626 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET
, LvtLint
.Uint32
);
628 LvtLint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET
);
629 LvtLint
.Bits
.Mask
= 1;
630 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET
, LvtLint
.Uint32
);
634 Read the initial count value from the init-count register.
636 @return The initial count value read from the init-count register.
640 GetApicTimerInitCount (
644 return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET
);
648 Read the current count value from the current-count register.
650 @return The current count value read from the current-count register.
654 GetApicTimerCurrentCount (
658 return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET
);
662 Initialize the local APIC timer.
664 The local APIC timer is initialized and enabled.
666 @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
667 If it is 0, then use the current divide value in the DCR.
668 @param InitCount The initial count value.
669 @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
670 @param Vector The timer interrupt vector number.
674 InitializeApicTimer (
675 IN UINTN DivideValue
,
677 IN BOOLEAN PeriodicMode
,
683 LOCAL_APIC_LVT_TIMER LvtTimer
;
687 // Ensure local APIC is in software-enabled state.
689 Svr
.Uint32
= ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
);
690 Svr
.Bits
.SoftwareEnable
= 1;
691 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
, Svr
.Uint32
);
694 // Program init-count register.
696 WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET
, InitCount
);
698 if (DivideValue
!= 0) {
699 ASSERT (DivideValue
<= 128);
700 ASSERT (DivideValue
== GetPowerOfTwo32((UINT32
)DivideValue
));
701 Divisor
= (UINT32
)((HighBitSet32 ((UINT32
)DivideValue
) - 1) & 0x7);
703 Dcr
.Uint32
= ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET
);
704 Dcr
.Bits
.DivideValue1
= (Divisor
& 0x3);
705 Dcr
.Bits
.DivideValue2
= (Divisor
>> 2);
706 WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET
, Dcr
.Uint32
);
710 // Enable APIC timer interrupt with specified timer mode.
712 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
714 LvtTimer
.Bits
.TimerMode
= 1;
716 LvtTimer
.Bits
.TimerMode
= 0;
718 LvtTimer
.Bits
.Mask
= 0;
719 LvtTimer
.Bits
.Vector
= Vector
;
720 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET
, LvtTimer
.Uint32
);
724 Get the state of the local APIC timer.
726 @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
727 @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
728 @param Vector Return the timer interrupt vector number.
733 OUT UINTN
*DivideValue OPTIONAL
,
734 OUT BOOLEAN
*PeriodicMode OPTIONAL
,
735 OUT UINT8
*Vector OPTIONAL
740 LOCAL_APIC_LVT_TIMER LvtTimer
;
742 if (DivideValue
!= NULL
) {
743 Dcr
.Uint32
= ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET
);
744 Divisor
= Dcr
.Bits
.DivideValue1
| (Dcr
.Bits
.DivideValue2
<< 2);
745 Divisor
= (Divisor
+ 1) & 0x7;
746 *DivideValue
= ((UINTN
)1) << Divisor
;
749 if (PeriodicMode
!= NULL
|| Vector
!= NULL
) {
750 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
751 if (PeriodicMode
!= NULL
) {
752 if (LvtTimer
.Bits
.TimerMode
== 1) {
753 *PeriodicMode
= TRUE
;
755 *PeriodicMode
= FALSE
;
758 if (Vector
!= NULL
) {
759 *Vector
= (UINT8
) LvtTimer
.Bits
.Vector
;
765 Enable the local APIC timer interrupt.
769 EnableApicTimerInterrupt (
773 LOCAL_APIC_LVT_TIMER LvtTimer
;
775 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
776 LvtTimer
.Bits
.Mask
= 0;
777 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET
, LvtTimer
.Uint32
);
781 Disable the local APIC timer interrupt.
785 DisableApicTimerInterrupt (
789 LOCAL_APIC_LVT_TIMER LvtTimer
;
791 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
792 LvtTimer
.Bits
.Mask
= 1;
793 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET
, LvtTimer
.Uint32
);
797 Get the local APIC timer interrupt state.
799 @retval TRUE The local APIC timer interrupt is enabled.
800 @retval FALSE The local APIC timer interrupt is disabled.
804 GetApicTimerInterruptState (
808 LOCAL_APIC_LVT_TIMER LvtTimer
;
810 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
811 return (BOOLEAN
)(LvtTimer
.Bits
.Mask
== 0);
815 Send EOI to the local APIC.
823 WriteLocalApicReg (XAPIC_EOI_OFFSET
, 0);
827 Get the 32-bit address that a device should use to send a Message Signaled
828 Interrupt (MSI) to the Local APIC of the currently executing processor.
830 @return 32-bit address used to send an MSI to the Local APIC.
838 LOCAL_APIC_MSI_ADDRESS MsiAddress
;
841 // Return address for an MSI interrupt to be delivered only to the APIC ID
842 // of the currently executing processor.
844 MsiAddress
.Uint32
= 0;
845 MsiAddress
.Bits
.BaseAddress
= 0xFEE;
846 MsiAddress
.Bits
.DestinationId
= GetApicId ();
847 return MsiAddress
.Uint32
;
851 Get the 64-bit data value that a device should use to send a Message Signaled
852 Interrupt (MSI) to the Local APIC of the currently executing processor.
854 If Vector is not in range 0x10..0xFE, then ASSERT().
855 If DeliveryMode is not supported, then ASSERT().
857 @param Vector The 8-bit interrupt vector associated with the MSI.
858 Must be in the range 0x10..0xFE
859 @param DeliveryMode A 3-bit value that specifies how the recept of the MSI
860 is handled. The only supported values are:
861 0: LOCAL_APIC_DELIVERY_MODE_FIXED
862 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
863 2: LOCAL_APIC_DELIVERY_MODE_SMI
864 4: LOCAL_APIC_DELIVERY_MODE_NMI
865 5: LOCAL_APIC_DELIVERY_MODE_INIT
866 7: LOCAL_APIC_DELIVERY_MODE_EXTINT
868 @param LevelTriggered TRUE specifies a level triggered interrupt.
869 FALSE specifies an edge triggered interrupt.
870 @param AssertionLevel Ignored if LevelTriggered is FALSE.
871 TRUE specifies a level triggered interrupt that active
872 when the interrupt line is asserted.
873 FALSE specifies a level triggered interrupt that active
874 when the interrupt line is deasserted.
876 @return 64-bit data value used to send an MSI to the Local APIC.
882 IN UINTN DeliveryMode
,
883 IN BOOLEAN LevelTriggered
,
884 IN BOOLEAN AssertionLevel
887 LOCAL_APIC_MSI_DATA MsiData
;
889 ASSERT (Vector
>= 0x10 && Vector
<= 0xFE);
890 ASSERT (DeliveryMode
< 8 && DeliveryMode
!= 6 && DeliveryMode
!= 3);
893 MsiData
.Bits
.Vector
= Vector
;
894 MsiData
.Bits
.DeliveryMode
= (UINT32
)DeliveryMode
;
895 if (LevelTriggered
) {
896 MsiData
.Bits
.TriggerMode
= 1;
897 if (AssertionLevel
) {
898 MsiData
.Bits
.Level
= 1;
901 return MsiData
.Uint64
;