4c4269612746c2840b5c792ce3b85c2f9ee7b622
[mirror_edk2.git] / UefiCpuPkg / Library / BaseXApicX2ApicLib / BaseXApicX2ApicLib.c
1 /** @file
2 Local APIC Library.
3
4 This local APIC library instance supports x2APIC capable processors
5 which have xAPIC and x2APIC modes.
6
7 Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
8 This program and the accompanying materials
9 are licensed and made available under the terms and conditions of the BSD License
10 which accompanies this distribution. The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
12
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15
16 **/
17
18 #include <Register/Cpuid.h>
19 #include <Register/Msr.h>
20 #include <Register/LocalApic.h>
21
22 #include <Library/BaseLib.h>
23 #include <Library/DebugLib.h>
24 #include <Library/LocalApicLib.h>
25 #include <Library/IoLib.h>
26 #include <Library/TimerLib.h>
27 #include <Library/PcdLib.h>
28
29 //
30 // Library internal functions
31 //
32
33 /**
34 Determine if the CPU supports the Local APIC Base Address MSR.
35
36 @retval TRUE The CPU supports the Local APIC Base Address MSR.
37 @retval FALSE The CPU does not support the Local APIC Base Address MSR.
38
39 **/
40 BOOLEAN
41 LocalApicBaseAddressMsrSupported (
42 VOID
43 )
44 {
45 UINT32 RegEax;
46 UINTN FamilyId;
47
48 AsmCpuid (1, &RegEax, NULL, NULL, NULL);
49 FamilyId = BitFieldRead32 (RegEax, 8, 11);
50 if (FamilyId == 0x04 || FamilyId == 0x05) {
51 //
52 // CPUs with a FamilyId of 0x04 or 0x05 do not support the
53 // Local APIC Base Address MSR
54 //
55 return FALSE;
56 }
57 return TRUE;
58 }
59
60 /**
61 Retrieve the base address of local APIC.
62
63 @return The base address of local APIC.
64
65 **/
66 UINTN
67 EFIAPI
68 GetLocalApicBaseAddress (
69 VOID
70 )
71 {
72 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
73
74 if (!LocalApicBaseAddressMsrSupported ()) {
75 //
76 // If CPU does not support Local APIC Base Address MSR, then retrieve
77 // Local APIC Base Address from PCD
78 //
79 return PcdGet32 (PcdCpuLocalApicBaseAddress);
80 }
81
82 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
83
84 return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +
85 (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
86 }
87
88 /**
89 Set the base address of local APIC.
90
91 If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
92
93 @param[in] BaseAddress Local APIC base address to be set.
94
95 **/
96 VOID
97 EFIAPI
98 SetLocalApicBaseAddress (
99 IN UINTN BaseAddress
100 )
101 {
102 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
103
104 ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
105
106 if (!LocalApicBaseAddressMsrSupported ()) {
107 //
108 // Ignore set request of the CPU does not support APIC Base Address MSR
109 //
110 return;
111 }
112
113 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
114
115 ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12);
116 ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
117
118 AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
119 }
120
121 /**
122 Read from a local APIC register.
123
124 This function reads from a local APIC register either in xAPIC or x2APIC mode.
125 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
126 accessed using multiple 32-bit loads or stores, so this function only performs
127 32-bit read.
128
129 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
130 It must be 16-byte aligned.
131
132 @return 32-bit Value read from the register.
133 **/
134 UINT32
135 EFIAPI
136 ReadLocalApicReg (
137 IN UINTN MmioOffset
138 )
139 {
140 UINT32 MsrIndex;
141
142 ASSERT ((MmioOffset & 0xf) == 0);
143
144 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
145 return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);
146 } else {
147 //
148 // DFR is not supported in x2APIC mode.
149 //
150 ASSERT (MmioOffset != XAPIC_ICR_DFR_OFFSET);
151 //
152 // Note that in x2APIC mode, ICR is a 64-bit MSR that needs special treatment. It
153 // is not supported in this function for simplicity.
154 //
155 ASSERT (MmioOffset != XAPIC_ICR_HIGH_OFFSET);
156
157 MsrIndex = (UINT32)(MmioOffset >> 4) + X2APIC_MSR_BASE_ADDRESS;
158 return AsmReadMsr32 (MsrIndex);
159 }
160 }
161
162 /**
163 Write to a local APIC register.
164
165 This function writes to a local APIC register either in xAPIC or x2APIC mode.
166 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
167 accessed using multiple 32-bit loads or stores, so this function only performs
168 32-bit write.
169
170 if the register index is invalid or unsupported in current APIC mode, then ASSERT.
171
172 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
173 It must be 16-byte aligned.
174 @param Value Value to be written to the register.
175 **/
176 VOID
177 EFIAPI
178 WriteLocalApicReg (
179 IN UINTN MmioOffset,
180 IN UINT32 Value
181 )
182 {
183 UINT32 MsrIndex;
184
185 ASSERT ((MmioOffset & 0xf) == 0);
186
187 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
188 MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);
189 } else {
190 //
191 // DFR is not supported in x2APIC mode.
192 //
193 ASSERT (MmioOffset != XAPIC_ICR_DFR_OFFSET);
194 //
195 // Note that in x2APIC mode, ICR is a 64-bit MSR that needs special treatment. It
196 // is not supported in this function for simplicity.
197 //
198 ASSERT (MmioOffset != XAPIC_ICR_HIGH_OFFSET);
199 ASSERT (MmioOffset != XAPIC_ICR_LOW_OFFSET);
200
201 MsrIndex = (UINT32)(MmioOffset >> 4) + X2APIC_MSR_BASE_ADDRESS;
202 //
203 // The serializing semantics of WRMSR are relaxed when writing to the APIC registers.
204 // Use memory fence here to force the serializing semantics to be consisent with xAPIC mode.
205 //
206 MemoryFence ();
207 AsmWriteMsr32 (MsrIndex, Value);
208 }
209 }
210
211 /**
212 Send an IPI by writing to ICR.
213
214 This function returns after the IPI has been accepted by the target processor.
215
216 @param IcrLow 32-bit value to be written to the low half of ICR.
217 @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
218 **/
219 VOID
220 SendIpi (
221 IN UINT32 IcrLow,
222 IN UINT32 ApicId
223 )
224 {
225 UINT64 MsrValue;
226 LOCAL_APIC_ICR_LOW IcrLowReg;
227 UINTN LocalApciBaseAddress;
228 UINT32 IcrHigh;
229 BOOLEAN InterruptState;
230
231 //
232 // Legacy APIC or X2APIC?
233 //
234 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
235 ASSERT (ApicId <= 0xff);
236
237 InterruptState = SaveAndDisableInterrupts ();
238
239 //
240 // Get base address of this LAPIC
241 //
242 LocalApciBaseAddress = GetLocalApicBaseAddress();
243
244 //
245 // Save existing contents of ICR high 32 bits
246 //
247 IcrHigh = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET);
248
249 //
250 // Wait for DeliveryStatus clear in case a previous IPI
251 // is still being sent
252 //
253 do {
254 IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);
255 } while (IcrLowReg.Bits.DeliveryStatus != 0);
256
257 //
258 // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
259 //
260 MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, ApicId << 24);
261 MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET, IcrLow);
262
263 //
264 // Wait for DeliveryStatus clear again
265 //
266 do {
267 IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);
268 } while (IcrLowReg.Bits.DeliveryStatus != 0);
269
270 //
271 // And restore old contents of ICR high
272 //
273 MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, IcrHigh);
274
275 SetInterruptState (InterruptState);
276
277 } else {
278 //
279 // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an
280 // interrupt in x2APIC mode.
281 //
282 MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow;
283 AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue);
284 }
285 }
286
287 //
288 // Library API implementation functions
289 //
290
291 /**
292 Get the current local APIC mode.
293
294 If local APIC is disabled, then ASSERT.
295
296 @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.
297 @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
298 **/
299 UINTN
300 EFIAPI
301 GetApicMode (
302 VOID
303 )
304 {
305 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
306
307 if (!LocalApicBaseAddressMsrSupported ()) {
308 //
309 // If CPU does not support APIC Base Address MSR, then return XAPIC mode
310 //
311 return LOCAL_APIC_MODE_XAPIC;
312 }
313
314 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
315 //
316 // Local APIC should have been enabled
317 //
318 ASSERT (ApicBaseMsr.Bits.EN != 0);
319 if (ApicBaseMsr.Bits.EXTD != 0) {
320 return LOCAL_APIC_MODE_X2APIC;
321 } else {
322 return LOCAL_APIC_MODE_XAPIC;
323 }
324 }
325
326 /**
327 Set the current local APIC mode.
328
329 If the specified local APIC mode is not valid, then ASSERT.
330 If the specified local APIC mode can't be set as current, then ASSERT.
331
332 @param ApicMode APIC mode to be set.
333
334 @note This API must not be called from an interrupt handler or SMI handler.
335 It may result in unpredictable behavior.
336 **/
337 VOID
338 EFIAPI
339 SetApicMode (
340 IN UINTN ApicMode
341 )
342 {
343 UINTN CurrentMode;
344 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
345
346 if (!LocalApicBaseAddressMsrSupported ()) {
347 //
348 // Ignore set request if the CPU does not support APIC Base Address MSR
349 //
350 return;
351 }
352
353 CurrentMode = GetApicMode ();
354 if (CurrentMode == LOCAL_APIC_MODE_XAPIC) {
355 switch (ApicMode) {
356 case LOCAL_APIC_MODE_XAPIC:
357 break;
358 case LOCAL_APIC_MODE_X2APIC:
359 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
360 ApicBaseMsr.Bits.EXTD = 1;
361 AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
362 break;
363 default:
364 ASSERT (FALSE);
365 }
366 } else {
367 switch (ApicMode) {
368 case LOCAL_APIC_MODE_XAPIC:
369 //
370 // Transition from x2APIC mode to xAPIC mode is a two-step process:
371 // x2APIC -> Local APIC disabled -> xAPIC
372 //
373 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
374 ApicBaseMsr.Bits.EXTD = 0;
375 ApicBaseMsr.Bits.EN = 0;
376 AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
377 ApicBaseMsr.Bits.EN = 1;
378 AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
379 break;
380 case LOCAL_APIC_MODE_X2APIC:
381 break;
382 default:
383 ASSERT (FALSE);
384 }
385 }
386 }
387
388 /**
389 Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
390
391 In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
392 In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
393 the 32-bit local APIC ID is returned as initial APIC ID.
394
395 @return 32-bit initial local APIC ID of the executing processor.
396 **/
397 UINT32
398 EFIAPI
399 GetInitialApicId (
400 VOID
401 )
402 {
403 UINT32 ApicId;
404 UINT32 MaxCpuIdIndex;
405 UINT32 RegEbx;
406
407 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
408 //
409 // Get the max index of basic CPUID
410 //
411 AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
412 //
413 // If CPUID Leaf B is supported,
414 // Then the initial 32-bit APIC ID = CPUID.0BH:EDX
415 // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]
416 //
417 if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
418 AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, NULL, NULL, &ApicId);
419 return ApicId;
420 }
421 AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
422 return RegEbx >> 24;
423 } else {
424 return GetApicId ();
425 }
426 }
427
428 /**
429 Get the local APIC ID of the executing processor.
430
431 @return 32-bit local APIC ID of the executing processor.
432 **/
433 UINT32
434 EFIAPI
435 GetApicId (
436 VOID
437 )
438 {
439 UINT32 ApicId;
440 UINT32 InitApicId;
441
442 ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
443 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
444 ApicId = ((InitApicId = GetInitialApicId ()) < 0x100) ? (ApicId >> 24) : InitApicId;
445 }
446
447 return ApicId;
448 }
449
450 /**
451 Get the value of the local APIC version register.
452
453 @return the value of the local APIC version register.
454 **/
455 UINT32
456 EFIAPI
457 GetApicVersion (
458 VOID
459 )
460 {
461 return ReadLocalApicReg (XAPIC_VERSION_OFFSET);
462 }
463
464 /**
465 Send a Fixed IPI to a specified target processor.
466
467 This function returns after the IPI has been accepted by the target processor.
468
469 @param ApicId The local APIC ID of the target processor.
470 @param Vector The vector number of the interrupt being sent.
471 **/
472 VOID
473 EFIAPI
474 SendFixedIpi (
475 IN UINT32 ApicId,
476 IN UINT8 Vector
477 )
478 {
479 LOCAL_APIC_ICR_LOW IcrLow;
480
481 IcrLow.Uint32 = 0;
482 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
483 IcrLow.Bits.Level = 1;
484 IcrLow.Bits.Vector = Vector;
485 SendIpi (IcrLow.Uint32, ApicId);
486 }
487
488 /**
489 Send a Fixed IPI to all processors excluding self.
490
491 This function returns after the IPI has been accepted by the target processors.
492
493 @param Vector The vector number of the interrupt being sent.
494 **/
495 VOID
496 EFIAPI
497 SendFixedIpiAllExcludingSelf (
498 IN UINT8 Vector
499 )
500 {
501 LOCAL_APIC_ICR_LOW IcrLow;
502
503 IcrLow.Uint32 = 0;
504 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
505 IcrLow.Bits.Level = 1;
506 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
507 IcrLow.Bits.Vector = Vector;
508 SendIpi (IcrLow.Uint32, 0);
509 }
510
511 /**
512 Send a SMI IPI to a specified target processor.
513
514 This function returns after the IPI has been accepted by the target processor.
515
516 @param ApicId Specify the local APIC ID of the target processor.
517 **/
518 VOID
519 EFIAPI
520 SendSmiIpi (
521 IN UINT32 ApicId
522 )
523 {
524 LOCAL_APIC_ICR_LOW IcrLow;
525
526 IcrLow.Uint32 = 0;
527 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
528 IcrLow.Bits.Level = 1;
529 SendIpi (IcrLow.Uint32, ApicId);
530 }
531
532 /**
533 Send a SMI IPI to all processors excluding self.
534
535 This function returns after the IPI has been accepted by the target processors.
536 **/
537 VOID
538 EFIAPI
539 SendSmiIpiAllExcludingSelf (
540 VOID
541 )
542 {
543 LOCAL_APIC_ICR_LOW IcrLow;
544
545 IcrLow.Uint32 = 0;
546 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
547 IcrLow.Bits.Level = 1;
548 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
549 SendIpi (IcrLow.Uint32, 0);
550 }
551
552 /**
553 Send an INIT IPI to a specified target processor.
554
555 This function returns after the IPI has been accepted by the target processor.
556
557 @param ApicId Specify the local APIC ID of the target processor.
558 **/
559 VOID
560 EFIAPI
561 SendInitIpi (
562 IN UINT32 ApicId
563 )
564 {
565 LOCAL_APIC_ICR_LOW IcrLow;
566
567 IcrLow.Uint32 = 0;
568 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
569 IcrLow.Bits.Level = 1;
570 SendIpi (IcrLow.Uint32, ApicId);
571 }
572
573 /**
574 Send an INIT IPI to all processors excluding self.
575
576 This function returns after the IPI has been accepted by the target processors.
577 **/
578 VOID
579 EFIAPI
580 SendInitIpiAllExcludingSelf (
581 VOID
582 )
583 {
584 LOCAL_APIC_ICR_LOW IcrLow;
585
586 IcrLow.Uint32 = 0;
587 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
588 IcrLow.Bits.Level = 1;
589 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
590 SendIpi (IcrLow.Uint32, 0);
591 }
592
593 /**
594 Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
595
596 This function returns after the IPI has been accepted by the target processor.
597
598 if StartupRoutine >= 1M, then ASSERT.
599 if StartupRoutine is not multiple of 4K, then ASSERT.
600
601 @param ApicId Specify the local APIC ID of the target processor.
602 @param StartupRoutine Points to a start-up routine which is below 1M physical
603 address and 4K aligned.
604 **/
605 VOID
606 EFIAPI
607 SendInitSipiSipi (
608 IN UINT32 ApicId,
609 IN UINT32 StartupRoutine
610 )
611 {
612 LOCAL_APIC_ICR_LOW IcrLow;
613
614 ASSERT (StartupRoutine < 0x100000);
615 ASSERT ((StartupRoutine & 0xfff) == 0);
616
617 SendInitIpi (ApicId);
618 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
619 IcrLow.Uint32 = 0;
620 IcrLow.Bits.Vector = (StartupRoutine >> 12);
621 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
622 IcrLow.Bits.Level = 1;
623 SendIpi (IcrLow.Uint32, ApicId);
624 MicroSecondDelay (200);
625 SendIpi (IcrLow.Uint32, ApicId);
626 }
627
628 /**
629 Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
630
631 This function returns after the IPI has been accepted by the target processors.
632
633 if StartupRoutine >= 1M, then ASSERT.
634 if StartupRoutine is not multiple of 4K, then ASSERT.
635
636 @param StartupRoutine Points to a start-up routine which is below 1M physical
637 address and 4K aligned.
638 **/
639 VOID
640 EFIAPI
641 SendInitSipiSipiAllExcludingSelf (
642 IN UINT32 StartupRoutine
643 )
644 {
645 LOCAL_APIC_ICR_LOW IcrLow;
646
647 ASSERT (StartupRoutine < 0x100000);
648 ASSERT ((StartupRoutine & 0xfff) == 0);
649
650 SendInitIpiAllExcludingSelf ();
651 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
652 IcrLow.Uint32 = 0;
653 IcrLow.Bits.Vector = (StartupRoutine >> 12);
654 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
655 IcrLow.Bits.Level = 1;
656 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
657 SendIpi (IcrLow.Uint32, 0);
658 MicroSecondDelay (200);
659 SendIpi (IcrLow.Uint32, 0);
660 }
661
662 /**
663 Initialize the state of the SoftwareEnable bit in the Local APIC
664 Spurious Interrupt Vector register.
665
666 @param Enable If TRUE, then set SoftwareEnable to 1
667 If FALSE, then set SoftwareEnable to 0.
668
669 **/
670 VOID
671 EFIAPI
672 InitializeLocalApicSoftwareEnable (
673 IN BOOLEAN Enable
674 )
675 {
676 LOCAL_APIC_SVR Svr;
677
678 //
679 // Set local APIC software-enabled bit.
680 //
681 Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
682 if (Enable) {
683 if (Svr.Bits.SoftwareEnable == 0) {
684 Svr.Bits.SoftwareEnable = 1;
685 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
686 }
687 } else {
688 if (Svr.Bits.SoftwareEnable == 1) {
689 Svr.Bits.SoftwareEnable = 0;
690 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
691 }
692 }
693 }
694
695 /**
696 Programming Virtual Wire Mode.
697
698 This function programs the local APIC for virtual wire mode following
699 the example described in chapter A.3 of the MP 1.4 spec.
700
701 IOxAPIC is not involved in this type of virtual wire mode.
702 **/
703 VOID
704 EFIAPI
705 ProgramVirtualWireMode (
706 VOID
707 )
708 {
709 LOCAL_APIC_SVR Svr;
710 LOCAL_APIC_LVT_LINT Lint;
711
712 //
713 // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
714 //
715 Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
716 Svr.Bits.SpuriousVector = 0xf;
717 Svr.Bits.SoftwareEnable = 1;
718 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
719
720 //
721 // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
722 //
723 Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
724 Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
725 Lint.Bits.InputPinPolarity = 0;
726 Lint.Bits.TriggerMode = 0;
727 Lint.Bits.Mask = 0;
728 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);
729
730 //
731 // Program the LINT0 vector entry as NMI. Not masked, edge, active high.
732 //
733 Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
734 Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
735 Lint.Bits.InputPinPolarity = 0;
736 Lint.Bits.TriggerMode = 0;
737 Lint.Bits.Mask = 0;
738 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);
739 }
740
741 /**
742 Disable LINT0 & LINT1 interrupts.
743
744 This function sets the mask flag in the LVT LINT0 & LINT1 registers.
745 **/
746 VOID
747 EFIAPI
748 DisableLvtInterrupts (
749 VOID
750 )
751 {
752 LOCAL_APIC_LVT_LINT LvtLint;
753
754 LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
755 LvtLint.Bits.Mask = 1;
756 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);
757
758 LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
759 LvtLint.Bits.Mask = 1;
760 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);
761 }
762
763 /**
764 Read the initial count value from the init-count register.
765
766 @return The initial count value read from the init-count register.
767 **/
768 UINT32
769 EFIAPI
770 GetApicTimerInitCount (
771 VOID
772 )
773 {
774 return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);
775 }
776
777 /**
778 Read the current count value from the current-count register.
779
780 @return The current count value read from the current-count register.
781 **/
782 UINT32
783 EFIAPI
784 GetApicTimerCurrentCount (
785 VOID
786 )
787 {
788 return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);
789 }
790
791 /**
792 Initialize the local APIC timer.
793
794 The local APIC timer is initialized and enabled.
795
796 @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
797 If it is 0, then use the current divide value in the DCR.
798 @param InitCount The initial count value.
799 @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
800 @param Vector The timer interrupt vector number.
801 **/
802 VOID
803 EFIAPI
804 InitializeApicTimer (
805 IN UINTN DivideValue,
806 IN UINT32 InitCount,
807 IN BOOLEAN PeriodicMode,
808 IN UINT8 Vector
809 )
810 {
811 LOCAL_APIC_DCR Dcr;
812 LOCAL_APIC_LVT_TIMER LvtTimer;
813 UINT32 Divisor;
814
815 //
816 // Ensure local APIC is in software-enabled state.
817 //
818 InitializeLocalApicSoftwareEnable (TRUE);
819
820 //
821 // Program init-count register.
822 //
823 WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);
824
825 if (DivideValue != 0) {
826 ASSERT (DivideValue <= 128);
827 ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));
828 Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);
829
830 Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
831 Dcr.Bits.DivideValue1 = (Divisor & 0x3);
832 Dcr.Bits.DivideValue2 = (Divisor >> 2);
833 WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
834 }
835
836 //
837 // Enable APIC timer interrupt with specified timer mode.
838 //
839 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
840 if (PeriodicMode) {
841 LvtTimer.Bits.TimerMode = 1;
842 } else {
843 LvtTimer.Bits.TimerMode = 0;
844 }
845 LvtTimer.Bits.Mask = 0;
846 LvtTimer.Bits.Vector = Vector;
847 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
848 }
849
850 /**
851 Get the state of the local APIC timer.
852
853 This function will ASSERT if the local APIC is not software enabled.
854
855 @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
856 @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
857 @param Vector Return the timer interrupt vector number.
858 **/
859 VOID
860 EFIAPI
861 GetApicTimerState (
862 OUT UINTN *DivideValue OPTIONAL,
863 OUT BOOLEAN *PeriodicMode OPTIONAL,
864 OUT UINT8 *Vector OPTIONAL
865 )
866 {
867 UINT32 Divisor;
868 LOCAL_APIC_DCR Dcr;
869 LOCAL_APIC_LVT_TIMER LvtTimer;
870
871 //
872 // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt
873 // Vector Register.
874 // This bit will be 1, if local APIC is software enabled.
875 //
876 ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);
877
878 if (DivideValue != NULL) {
879 Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
880 Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
881 Divisor = (Divisor + 1) & 0x7;
882 *DivideValue = ((UINTN)1) << Divisor;
883 }
884
885 if (PeriodicMode != NULL || Vector != NULL) {
886 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
887 if (PeriodicMode != NULL) {
888 if (LvtTimer.Bits.TimerMode == 1) {
889 *PeriodicMode = TRUE;
890 } else {
891 *PeriodicMode = FALSE;
892 }
893 }
894 if (Vector != NULL) {
895 *Vector = (UINT8) LvtTimer.Bits.Vector;
896 }
897 }
898 }
899
900 /**
901 Enable the local APIC timer interrupt.
902 **/
903 VOID
904 EFIAPI
905 EnableApicTimerInterrupt (
906 VOID
907 )
908 {
909 LOCAL_APIC_LVT_TIMER LvtTimer;
910
911 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
912 LvtTimer.Bits.Mask = 0;
913 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
914 }
915
916 /**
917 Disable the local APIC timer interrupt.
918 **/
919 VOID
920 EFIAPI
921 DisableApicTimerInterrupt (
922 VOID
923 )
924 {
925 LOCAL_APIC_LVT_TIMER LvtTimer;
926
927 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
928 LvtTimer.Bits.Mask = 1;
929 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
930 }
931
932 /**
933 Get the local APIC timer interrupt state.
934
935 @retval TRUE The local APIC timer interrupt is enabled.
936 @retval FALSE The local APIC timer interrupt is disabled.
937 **/
938 BOOLEAN
939 EFIAPI
940 GetApicTimerInterruptState (
941 VOID
942 )
943 {
944 LOCAL_APIC_LVT_TIMER LvtTimer;
945
946 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
947 return (BOOLEAN)(LvtTimer.Bits.Mask == 0);
948 }
949
950 /**
951 Send EOI to the local APIC.
952 **/
953 VOID
954 EFIAPI
955 SendApicEoi (
956 VOID
957 )
958 {
959 WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);
960 }
961
962 /**
963 Get the 32-bit address that a device should use to send a Message Signaled
964 Interrupt (MSI) to the Local APIC of the currently executing processor.
965
966 @return 32-bit address used to send an MSI to the Local APIC.
967 **/
968 UINT32
969 EFIAPI
970 GetApicMsiAddress (
971 VOID
972 )
973 {
974 LOCAL_APIC_MSI_ADDRESS MsiAddress;
975
976 //
977 // Return address for an MSI interrupt to be delivered only to the APIC ID
978 // of the currently executing processor.
979 //
980 MsiAddress.Uint32 = 0;
981 MsiAddress.Bits.BaseAddress = 0xFEE;
982 MsiAddress.Bits.DestinationId = GetApicId ();
983 return MsiAddress.Uint32;
984 }
985
986 /**
987 Get the 64-bit data value that a device should use to send a Message Signaled
988 Interrupt (MSI) to the Local APIC of the currently executing processor.
989
990 If Vector is not in range 0x10..0xFE, then ASSERT().
991 If DeliveryMode is not supported, then ASSERT().
992
993 @param Vector The 8-bit interrupt vector associated with the MSI.
994 Must be in the range 0x10..0xFE
995 @param DeliveryMode A 3-bit value that specifies how the recept of the MSI
996 is handled. The only supported values are:
997 0: LOCAL_APIC_DELIVERY_MODE_FIXED
998 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
999 2: LOCAL_APIC_DELIVERY_MODE_SMI
1000 4: LOCAL_APIC_DELIVERY_MODE_NMI
1001 5: LOCAL_APIC_DELIVERY_MODE_INIT
1002 7: LOCAL_APIC_DELIVERY_MODE_EXTINT
1003
1004 @param LevelTriggered TRUE specifies a level triggered interrupt.
1005 FALSE specifies an edge triggered interrupt.
1006 @param AssertionLevel Ignored if LevelTriggered is FALSE.
1007 TRUE specifies a level triggered interrupt that active
1008 when the interrupt line is asserted.
1009 FALSE specifies a level triggered interrupt that active
1010 when the interrupt line is deasserted.
1011
1012 @return 64-bit data value used to send an MSI to the Local APIC.
1013 **/
1014 UINT64
1015 EFIAPI
1016 GetApicMsiValue (
1017 IN UINT8 Vector,
1018 IN UINTN DeliveryMode,
1019 IN BOOLEAN LevelTriggered,
1020 IN BOOLEAN AssertionLevel
1021 )
1022 {
1023 LOCAL_APIC_MSI_DATA MsiData;
1024
1025 ASSERT (Vector >= 0x10 && Vector <= 0xFE);
1026 ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);
1027
1028 MsiData.Uint64 = 0;
1029 MsiData.Bits.Vector = Vector;
1030 MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;
1031 if (LevelTriggered) {
1032 MsiData.Bits.TriggerMode = 1;
1033 if (AssertionLevel) {
1034 MsiData.Bits.Level = 1;
1035 }
1036 }
1037 return MsiData.Uint64;
1038 }