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1 /** @file
2 Local APIC Library.
3
4 This local APIC library instance supports x2APIC capable processors
5 which have xAPIC and x2APIC modes.
6
7 Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
8 Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
9
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
14
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17
18 **/
19
20 #include <Register/Cpuid.h>
21 #include <Register/Amd/Cpuid.h>
22 #include <Register/Msr.h>
23 #include <Register/LocalApic.h>
24
25 #include <Library/BaseLib.h>
26 #include <Library/DebugLib.h>
27 #include <Library/LocalApicLib.h>
28 #include <Library/IoLib.h>
29 #include <Library/TimerLib.h>
30 #include <Library/PcdLib.h>
31
32 //
33 // Library internal functions
34 //
35
36 /**
37 Determine if the standard CPU signature is "AuthenticAMD".
38
39 @retval TRUE The CPU signature matches.
40 @retval FALSE The CPU signature does not match.
41
42 **/
43 BOOLEAN
44 StandardSignatureIsAuthenticAMD (
45 VOID
46 )
47 {
48 UINT32 RegEbx;
49 UINT32 RegEcx;
50 UINT32 RegEdx;
51
52 AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);
53 return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&
54 RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&
55 RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);
56 }
57
58 /**
59 Determine if the CPU supports the Local APIC Base Address MSR.
60
61 @retval TRUE The CPU supports the Local APIC Base Address MSR.
62 @retval FALSE The CPU does not support the Local APIC Base Address MSR.
63
64 **/
65 BOOLEAN
66 LocalApicBaseAddressMsrSupported (
67 VOID
68 )
69 {
70 UINT32 RegEax;
71 UINTN FamilyId;
72
73 AsmCpuid (1, &RegEax, NULL, NULL, NULL);
74 FamilyId = BitFieldRead32 (RegEax, 8, 11);
75 if (FamilyId == 0x04 || FamilyId == 0x05) {
76 //
77 // CPUs with a FamilyId of 0x04 or 0x05 do not support the
78 // Local APIC Base Address MSR
79 //
80 return FALSE;
81 }
82 return TRUE;
83 }
84
85 /**
86 Retrieve the base address of local APIC.
87
88 @return The base address of local APIC.
89
90 **/
91 UINTN
92 EFIAPI
93 GetLocalApicBaseAddress (
94 VOID
95 )
96 {
97 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
98
99 if (!LocalApicBaseAddressMsrSupported ()) {
100 //
101 // If CPU does not support Local APIC Base Address MSR, then retrieve
102 // Local APIC Base Address from PCD
103 //
104 return PcdGet32 (PcdCpuLocalApicBaseAddress);
105 }
106
107 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
108
109 return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +
110 (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
111 }
112
113 /**
114 Set the base address of local APIC.
115
116 If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
117
118 @param[in] BaseAddress Local APIC base address to be set.
119
120 **/
121 VOID
122 EFIAPI
123 SetLocalApicBaseAddress (
124 IN UINTN BaseAddress
125 )
126 {
127 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
128
129 ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
130
131 if (!LocalApicBaseAddressMsrSupported ()) {
132 //
133 // Ignore set request of the CPU does not support APIC Base Address MSR
134 //
135 return;
136 }
137
138 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
139
140 ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12);
141 ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
142
143 AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
144 }
145
146 /**
147 Read from a local APIC register.
148
149 This function reads from a local APIC register either in xAPIC or x2APIC mode.
150 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
151 accessed using multiple 32-bit loads or stores, so this function only performs
152 32-bit read.
153
154 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
155 It must be 16-byte aligned.
156
157 @return 32-bit Value read from the register.
158 **/
159 UINT32
160 EFIAPI
161 ReadLocalApicReg (
162 IN UINTN MmioOffset
163 )
164 {
165 UINT32 MsrIndex;
166
167 ASSERT ((MmioOffset & 0xf) == 0);
168
169 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
170 return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);
171 } else {
172 //
173 // DFR is not supported in x2APIC mode.
174 //
175 ASSERT (MmioOffset != XAPIC_ICR_DFR_OFFSET);
176 //
177 // Note that in x2APIC mode, ICR is a 64-bit MSR that needs special treatment. It
178 // is not supported in this function for simplicity.
179 //
180 ASSERT (MmioOffset != XAPIC_ICR_HIGH_OFFSET);
181
182 MsrIndex = (UINT32)(MmioOffset >> 4) + X2APIC_MSR_BASE_ADDRESS;
183 return AsmReadMsr32 (MsrIndex);
184 }
185 }
186
187 /**
188 Write to a local APIC register.
189
190 This function writes to a local APIC register either in xAPIC or x2APIC mode.
191 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
192 accessed using multiple 32-bit loads or stores, so this function only performs
193 32-bit write.
194
195 if the register index is invalid or unsupported in current APIC mode, then ASSERT.
196
197 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
198 It must be 16-byte aligned.
199 @param Value Value to be written to the register.
200 **/
201 VOID
202 EFIAPI
203 WriteLocalApicReg (
204 IN UINTN MmioOffset,
205 IN UINT32 Value
206 )
207 {
208 UINT32 MsrIndex;
209
210 ASSERT ((MmioOffset & 0xf) == 0);
211
212 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
213 MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);
214 } else {
215 //
216 // DFR is not supported in x2APIC mode.
217 //
218 ASSERT (MmioOffset != XAPIC_ICR_DFR_OFFSET);
219 //
220 // Note that in x2APIC mode, ICR is a 64-bit MSR that needs special treatment. It
221 // is not supported in this function for simplicity.
222 //
223 ASSERT (MmioOffset != XAPIC_ICR_HIGH_OFFSET);
224 ASSERT (MmioOffset != XAPIC_ICR_LOW_OFFSET);
225
226 MsrIndex = (UINT32)(MmioOffset >> 4) + X2APIC_MSR_BASE_ADDRESS;
227 //
228 // The serializing semantics of WRMSR are relaxed when writing to the APIC registers.
229 // Use memory fence here to force the serializing semantics to be consisent with xAPIC mode.
230 //
231 MemoryFence ();
232 AsmWriteMsr32 (MsrIndex, Value);
233 }
234 }
235
236 /**
237 Send an IPI by writing to ICR.
238
239 This function returns after the IPI has been accepted by the target processor.
240
241 @param IcrLow 32-bit value to be written to the low half of ICR.
242 @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
243 **/
244 VOID
245 SendIpi (
246 IN UINT32 IcrLow,
247 IN UINT32 ApicId
248 )
249 {
250 UINT64 MsrValue;
251 LOCAL_APIC_ICR_LOW IcrLowReg;
252 UINTN LocalApciBaseAddress;
253 UINT32 IcrHigh;
254 BOOLEAN InterruptState;
255
256 //
257 // Legacy APIC or X2APIC?
258 //
259 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
260 ASSERT (ApicId <= 0xff);
261
262 InterruptState = SaveAndDisableInterrupts ();
263
264 //
265 // Get base address of this LAPIC
266 //
267 LocalApciBaseAddress = GetLocalApicBaseAddress();
268
269 //
270 // Save existing contents of ICR high 32 bits
271 //
272 IcrHigh = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET);
273
274 //
275 // Wait for DeliveryStatus clear in case a previous IPI
276 // is still being sent
277 //
278 do {
279 IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);
280 } while (IcrLowReg.Bits.DeliveryStatus != 0);
281
282 //
283 // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
284 //
285 MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, ApicId << 24);
286 MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET, IcrLow);
287
288 //
289 // Wait for DeliveryStatus clear again
290 //
291 do {
292 IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);
293 } while (IcrLowReg.Bits.DeliveryStatus != 0);
294
295 //
296 // And restore old contents of ICR high
297 //
298 MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, IcrHigh);
299
300 SetInterruptState (InterruptState);
301
302 } else {
303 //
304 // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an
305 // interrupt in x2APIC mode.
306 //
307 MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow;
308 AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue);
309 }
310 }
311
312 //
313 // Library API implementation functions
314 //
315
316 /**
317 Get the current local APIC mode.
318
319 If local APIC is disabled, then ASSERT.
320
321 @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.
322 @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
323 **/
324 UINTN
325 EFIAPI
326 GetApicMode (
327 VOID
328 )
329 {
330 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
331
332 if (!LocalApicBaseAddressMsrSupported ()) {
333 //
334 // If CPU does not support APIC Base Address MSR, then return XAPIC mode
335 //
336 return LOCAL_APIC_MODE_XAPIC;
337 }
338
339 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
340 //
341 // Local APIC should have been enabled
342 //
343 ASSERT (ApicBaseMsr.Bits.EN != 0);
344 if (ApicBaseMsr.Bits.EXTD != 0) {
345 return LOCAL_APIC_MODE_X2APIC;
346 } else {
347 return LOCAL_APIC_MODE_XAPIC;
348 }
349 }
350
351 /**
352 Set the current local APIC mode.
353
354 If the specified local APIC mode is not valid, then ASSERT.
355 If the specified local APIC mode can't be set as current, then ASSERT.
356
357 @param ApicMode APIC mode to be set.
358
359 @note This API must not be called from an interrupt handler or SMI handler.
360 It may result in unpredictable behavior.
361 **/
362 VOID
363 EFIAPI
364 SetApicMode (
365 IN UINTN ApicMode
366 )
367 {
368 UINTN CurrentMode;
369 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
370
371 if (!LocalApicBaseAddressMsrSupported ()) {
372 //
373 // Ignore set request if the CPU does not support APIC Base Address MSR
374 //
375 return;
376 }
377
378 CurrentMode = GetApicMode ();
379 if (CurrentMode == LOCAL_APIC_MODE_XAPIC) {
380 switch (ApicMode) {
381 case LOCAL_APIC_MODE_XAPIC:
382 break;
383 case LOCAL_APIC_MODE_X2APIC:
384 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
385 ApicBaseMsr.Bits.EXTD = 1;
386 AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
387 break;
388 default:
389 ASSERT (FALSE);
390 }
391 } else {
392 switch (ApicMode) {
393 case LOCAL_APIC_MODE_XAPIC:
394 //
395 // Transition from x2APIC mode to xAPIC mode is a two-step process:
396 // x2APIC -> Local APIC disabled -> xAPIC
397 //
398 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
399 ApicBaseMsr.Bits.EXTD = 0;
400 ApicBaseMsr.Bits.EN = 0;
401 AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
402 ApicBaseMsr.Bits.EN = 1;
403 AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
404 break;
405 case LOCAL_APIC_MODE_X2APIC:
406 break;
407 default:
408 ASSERT (FALSE);
409 }
410 }
411 }
412
413 /**
414 Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
415
416 In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
417 In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
418 the 32-bit local APIC ID is returned as initial APIC ID.
419
420 @return 32-bit initial local APIC ID of the executing processor.
421 **/
422 UINT32
423 EFIAPI
424 GetInitialApicId (
425 VOID
426 )
427 {
428 UINT32 ApicId;
429 UINT32 MaxCpuIdIndex;
430 UINT32 RegEbx;
431
432 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
433 //
434 // Get the max index of basic CPUID
435 //
436 AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
437 //
438 // If CPUID Leaf B is supported,
439 // And CPUID.0BH:EBX[15:0] reports a non-zero value,
440 // Then the initial 32-bit APIC ID = CPUID.0BH:EDX
441 // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]
442 //
443 if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
444 AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, &RegEbx, NULL, &ApicId);
445 if ((RegEbx & (BIT16 - 1)) != 0) {
446 return ApicId;
447 }
448 }
449 AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
450 return RegEbx >> 24;
451 } else {
452 return GetApicId ();
453 }
454 }
455
456 /**
457 Get the local APIC ID of the executing processor.
458
459 @return 32-bit local APIC ID of the executing processor.
460 **/
461 UINT32
462 EFIAPI
463 GetApicId (
464 VOID
465 )
466 {
467 UINT32 ApicId;
468 UINT32 InitApicId;
469
470 ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
471 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
472 ApicId = ((InitApicId = GetInitialApicId ()) < 0x100) ? (ApicId >> 24) : InitApicId;
473 }
474
475 return ApicId;
476 }
477
478 /**
479 Get the value of the local APIC version register.
480
481 @return the value of the local APIC version register.
482 **/
483 UINT32
484 EFIAPI
485 GetApicVersion (
486 VOID
487 )
488 {
489 return ReadLocalApicReg (XAPIC_VERSION_OFFSET);
490 }
491
492 /**
493 Send a Fixed IPI to a specified target processor.
494
495 This function returns after the IPI has been accepted by the target processor.
496
497 @param ApicId The local APIC ID of the target processor.
498 @param Vector The vector number of the interrupt being sent.
499 **/
500 VOID
501 EFIAPI
502 SendFixedIpi (
503 IN UINT32 ApicId,
504 IN UINT8 Vector
505 )
506 {
507 LOCAL_APIC_ICR_LOW IcrLow;
508
509 IcrLow.Uint32 = 0;
510 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
511 IcrLow.Bits.Level = 1;
512 IcrLow.Bits.Vector = Vector;
513 SendIpi (IcrLow.Uint32, ApicId);
514 }
515
516 /**
517 Send a Fixed IPI to all processors excluding self.
518
519 This function returns after the IPI has been accepted by the target processors.
520
521 @param Vector The vector number of the interrupt being sent.
522 **/
523 VOID
524 EFIAPI
525 SendFixedIpiAllExcludingSelf (
526 IN UINT8 Vector
527 )
528 {
529 LOCAL_APIC_ICR_LOW IcrLow;
530
531 IcrLow.Uint32 = 0;
532 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
533 IcrLow.Bits.Level = 1;
534 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
535 IcrLow.Bits.Vector = Vector;
536 SendIpi (IcrLow.Uint32, 0);
537 }
538
539 /**
540 Send a SMI IPI to a specified target processor.
541
542 This function returns after the IPI has been accepted by the target processor.
543
544 @param ApicId Specify the local APIC ID of the target processor.
545 **/
546 VOID
547 EFIAPI
548 SendSmiIpi (
549 IN UINT32 ApicId
550 )
551 {
552 LOCAL_APIC_ICR_LOW IcrLow;
553
554 IcrLow.Uint32 = 0;
555 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
556 IcrLow.Bits.Level = 1;
557 SendIpi (IcrLow.Uint32, ApicId);
558 }
559
560 /**
561 Send a SMI IPI to all processors excluding self.
562
563 This function returns after the IPI has been accepted by the target processors.
564 **/
565 VOID
566 EFIAPI
567 SendSmiIpiAllExcludingSelf (
568 VOID
569 )
570 {
571 LOCAL_APIC_ICR_LOW IcrLow;
572
573 IcrLow.Uint32 = 0;
574 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
575 IcrLow.Bits.Level = 1;
576 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
577 SendIpi (IcrLow.Uint32, 0);
578 }
579
580 /**
581 Send an INIT IPI to a specified target processor.
582
583 This function returns after the IPI has been accepted by the target processor.
584
585 @param ApicId Specify the local APIC ID of the target processor.
586 **/
587 VOID
588 EFIAPI
589 SendInitIpi (
590 IN UINT32 ApicId
591 )
592 {
593 LOCAL_APIC_ICR_LOW IcrLow;
594
595 IcrLow.Uint32 = 0;
596 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
597 IcrLow.Bits.Level = 1;
598 SendIpi (IcrLow.Uint32, ApicId);
599 }
600
601 /**
602 Send an INIT IPI to all processors excluding self.
603
604 This function returns after the IPI has been accepted by the target processors.
605 **/
606 VOID
607 EFIAPI
608 SendInitIpiAllExcludingSelf (
609 VOID
610 )
611 {
612 LOCAL_APIC_ICR_LOW IcrLow;
613
614 IcrLow.Uint32 = 0;
615 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
616 IcrLow.Bits.Level = 1;
617 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
618 SendIpi (IcrLow.Uint32, 0);
619 }
620
621 /**
622 Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
623
624 This function returns after the IPI has been accepted by the target processor.
625
626 if StartupRoutine >= 1M, then ASSERT.
627 if StartupRoutine is not multiple of 4K, then ASSERT.
628
629 @param ApicId Specify the local APIC ID of the target processor.
630 @param StartupRoutine Points to a start-up routine which is below 1M physical
631 address and 4K aligned.
632 **/
633 VOID
634 EFIAPI
635 SendInitSipiSipi (
636 IN UINT32 ApicId,
637 IN UINT32 StartupRoutine
638 )
639 {
640 LOCAL_APIC_ICR_LOW IcrLow;
641
642 ASSERT (StartupRoutine < 0x100000);
643 ASSERT ((StartupRoutine & 0xfff) == 0);
644
645 SendInitIpi (ApicId);
646 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
647 IcrLow.Uint32 = 0;
648 IcrLow.Bits.Vector = (StartupRoutine >> 12);
649 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
650 IcrLow.Bits.Level = 1;
651 SendIpi (IcrLow.Uint32, ApicId);
652 if (!StandardSignatureIsAuthenticAMD ()) {
653 MicroSecondDelay (200);
654 SendIpi (IcrLow.Uint32, ApicId);
655 }
656 }
657
658 /**
659 Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
660
661 This function returns after the IPI has been accepted by the target processors.
662
663 if StartupRoutine >= 1M, then ASSERT.
664 if StartupRoutine is not multiple of 4K, then ASSERT.
665
666 @param StartupRoutine Points to a start-up routine which is below 1M physical
667 address and 4K aligned.
668 **/
669 VOID
670 EFIAPI
671 SendInitSipiSipiAllExcludingSelf (
672 IN UINT32 StartupRoutine
673 )
674 {
675 LOCAL_APIC_ICR_LOW IcrLow;
676
677 ASSERT (StartupRoutine < 0x100000);
678 ASSERT ((StartupRoutine & 0xfff) == 0);
679
680 SendInitIpiAllExcludingSelf ();
681 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
682 IcrLow.Uint32 = 0;
683 IcrLow.Bits.Vector = (StartupRoutine >> 12);
684 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
685 IcrLow.Bits.Level = 1;
686 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
687 SendIpi (IcrLow.Uint32, 0);
688 if (!StandardSignatureIsAuthenticAMD ()) {
689 MicroSecondDelay (200);
690 SendIpi (IcrLow.Uint32, 0);
691 }
692 }
693
694 /**
695 Initialize the state of the SoftwareEnable bit in the Local APIC
696 Spurious Interrupt Vector register.
697
698 @param Enable If TRUE, then set SoftwareEnable to 1
699 If FALSE, then set SoftwareEnable to 0.
700
701 **/
702 VOID
703 EFIAPI
704 InitializeLocalApicSoftwareEnable (
705 IN BOOLEAN Enable
706 )
707 {
708 LOCAL_APIC_SVR Svr;
709
710 //
711 // Set local APIC software-enabled bit.
712 //
713 Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
714 if (Enable) {
715 if (Svr.Bits.SoftwareEnable == 0) {
716 Svr.Bits.SoftwareEnable = 1;
717 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
718 }
719 } else {
720 if (Svr.Bits.SoftwareEnable == 1) {
721 Svr.Bits.SoftwareEnable = 0;
722 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
723 }
724 }
725 }
726
727 /**
728 Programming Virtual Wire Mode.
729
730 This function programs the local APIC for virtual wire mode following
731 the example described in chapter A.3 of the MP 1.4 spec.
732
733 IOxAPIC is not involved in this type of virtual wire mode.
734 **/
735 VOID
736 EFIAPI
737 ProgramVirtualWireMode (
738 VOID
739 )
740 {
741 LOCAL_APIC_SVR Svr;
742 LOCAL_APIC_LVT_LINT Lint;
743
744 //
745 // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
746 //
747 Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
748 Svr.Bits.SpuriousVector = 0xf;
749 Svr.Bits.SoftwareEnable = 1;
750 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
751
752 //
753 // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
754 //
755 Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
756 Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
757 Lint.Bits.InputPinPolarity = 0;
758 Lint.Bits.TriggerMode = 0;
759 Lint.Bits.Mask = 0;
760 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);
761
762 //
763 // Program the LINT0 vector entry as NMI. Not masked, edge, active high.
764 //
765 Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
766 Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
767 Lint.Bits.InputPinPolarity = 0;
768 Lint.Bits.TriggerMode = 0;
769 Lint.Bits.Mask = 0;
770 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);
771 }
772
773 /**
774 Disable LINT0 & LINT1 interrupts.
775
776 This function sets the mask flag in the LVT LINT0 & LINT1 registers.
777 **/
778 VOID
779 EFIAPI
780 DisableLvtInterrupts (
781 VOID
782 )
783 {
784 LOCAL_APIC_LVT_LINT LvtLint;
785
786 LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
787 LvtLint.Bits.Mask = 1;
788 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);
789
790 LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
791 LvtLint.Bits.Mask = 1;
792 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);
793 }
794
795 /**
796 Read the initial count value from the init-count register.
797
798 @return The initial count value read from the init-count register.
799 **/
800 UINT32
801 EFIAPI
802 GetApicTimerInitCount (
803 VOID
804 )
805 {
806 return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);
807 }
808
809 /**
810 Read the current count value from the current-count register.
811
812 @return The current count value read from the current-count register.
813 **/
814 UINT32
815 EFIAPI
816 GetApicTimerCurrentCount (
817 VOID
818 )
819 {
820 return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);
821 }
822
823 /**
824 Initialize the local APIC timer.
825
826 The local APIC timer is initialized and enabled.
827
828 @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
829 If it is 0, then use the current divide value in the DCR.
830 @param InitCount The initial count value.
831 @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
832 @param Vector The timer interrupt vector number.
833 **/
834 VOID
835 EFIAPI
836 InitializeApicTimer (
837 IN UINTN DivideValue,
838 IN UINT32 InitCount,
839 IN BOOLEAN PeriodicMode,
840 IN UINT8 Vector
841 )
842 {
843 LOCAL_APIC_DCR Dcr;
844 LOCAL_APIC_LVT_TIMER LvtTimer;
845 UINT32 Divisor;
846
847 //
848 // Ensure local APIC is in software-enabled state.
849 //
850 InitializeLocalApicSoftwareEnable (TRUE);
851
852 //
853 // Program init-count register.
854 //
855 WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);
856
857 if (DivideValue != 0) {
858 ASSERT (DivideValue <= 128);
859 ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));
860 Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);
861
862 Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
863 Dcr.Bits.DivideValue1 = (Divisor & 0x3);
864 Dcr.Bits.DivideValue2 = (Divisor >> 2);
865 WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
866 }
867
868 //
869 // Enable APIC timer interrupt with specified timer mode.
870 //
871 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
872 if (PeriodicMode) {
873 LvtTimer.Bits.TimerMode = 1;
874 } else {
875 LvtTimer.Bits.TimerMode = 0;
876 }
877 LvtTimer.Bits.Mask = 0;
878 LvtTimer.Bits.Vector = Vector;
879 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
880 }
881
882 /**
883 Get the state of the local APIC timer.
884
885 This function will ASSERT if the local APIC is not software enabled.
886
887 @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
888 @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
889 @param Vector Return the timer interrupt vector number.
890 **/
891 VOID
892 EFIAPI
893 GetApicTimerState (
894 OUT UINTN *DivideValue OPTIONAL,
895 OUT BOOLEAN *PeriodicMode OPTIONAL,
896 OUT UINT8 *Vector OPTIONAL
897 )
898 {
899 UINT32 Divisor;
900 LOCAL_APIC_DCR Dcr;
901 LOCAL_APIC_LVT_TIMER LvtTimer;
902
903 //
904 // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt
905 // Vector Register.
906 // This bit will be 1, if local APIC is software enabled.
907 //
908 ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);
909
910 if (DivideValue != NULL) {
911 Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
912 Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
913 Divisor = (Divisor + 1) & 0x7;
914 *DivideValue = ((UINTN)1) << Divisor;
915 }
916
917 if (PeriodicMode != NULL || Vector != NULL) {
918 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
919 if (PeriodicMode != NULL) {
920 if (LvtTimer.Bits.TimerMode == 1) {
921 *PeriodicMode = TRUE;
922 } else {
923 *PeriodicMode = FALSE;
924 }
925 }
926 if (Vector != NULL) {
927 *Vector = (UINT8) LvtTimer.Bits.Vector;
928 }
929 }
930 }
931
932 /**
933 Enable the local APIC timer interrupt.
934 **/
935 VOID
936 EFIAPI
937 EnableApicTimerInterrupt (
938 VOID
939 )
940 {
941 LOCAL_APIC_LVT_TIMER LvtTimer;
942
943 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
944 LvtTimer.Bits.Mask = 0;
945 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
946 }
947
948 /**
949 Disable the local APIC timer interrupt.
950 **/
951 VOID
952 EFIAPI
953 DisableApicTimerInterrupt (
954 VOID
955 )
956 {
957 LOCAL_APIC_LVT_TIMER LvtTimer;
958
959 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
960 LvtTimer.Bits.Mask = 1;
961 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
962 }
963
964 /**
965 Get the local APIC timer interrupt state.
966
967 @retval TRUE The local APIC timer interrupt is enabled.
968 @retval FALSE The local APIC timer interrupt is disabled.
969 **/
970 BOOLEAN
971 EFIAPI
972 GetApicTimerInterruptState (
973 VOID
974 )
975 {
976 LOCAL_APIC_LVT_TIMER LvtTimer;
977
978 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
979 return (BOOLEAN)(LvtTimer.Bits.Mask == 0);
980 }
981
982 /**
983 Send EOI to the local APIC.
984 **/
985 VOID
986 EFIAPI
987 SendApicEoi (
988 VOID
989 )
990 {
991 WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);
992 }
993
994 /**
995 Get the 32-bit address that a device should use to send a Message Signaled
996 Interrupt (MSI) to the Local APIC of the currently executing processor.
997
998 @return 32-bit address used to send an MSI to the Local APIC.
999 **/
1000 UINT32
1001 EFIAPI
1002 GetApicMsiAddress (
1003 VOID
1004 )
1005 {
1006 LOCAL_APIC_MSI_ADDRESS MsiAddress;
1007
1008 //
1009 // Return address for an MSI interrupt to be delivered only to the APIC ID
1010 // of the currently executing processor.
1011 //
1012 MsiAddress.Uint32 = 0;
1013 MsiAddress.Bits.BaseAddress = 0xFEE;
1014 MsiAddress.Bits.DestinationId = GetApicId ();
1015 return MsiAddress.Uint32;
1016 }
1017
1018 /**
1019 Get the 64-bit data value that a device should use to send a Message Signaled
1020 Interrupt (MSI) to the Local APIC of the currently executing processor.
1021
1022 If Vector is not in range 0x10..0xFE, then ASSERT().
1023 If DeliveryMode is not supported, then ASSERT().
1024
1025 @param Vector The 8-bit interrupt vector associated with the MSI.
1026 Must be in the range 0x10..0xFE
1027 @param DeliveryMode A 3-bit value that specifies how the recept of the MSI
1028 is handled. The only supported values are:
1029 0: LOCAL_APIC_DELIVERY_MODE_FIXED
1030 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
1031 2: LOCAL_APIC_DELIVERY_MODE_SMI
1032 4: LOCAL_APIC_DELIVERY_MODE_NMI
1033 5: LOCAL_APIC_DELIVERY_MODE_INIT
1034 7: LOCAL_APIC_DELIVERY_MODE_EXTINT
1035
1036 @param LevelTriggered TRUE specifies a level triggered interrupt.
1037 FALSE specifies an edge triggered interrupt.
1038 @param AssertionLevel Ignored if LevelTriggered is FALSE.
1039 TRUE specifies a level triggered interrupt that active
1040 when the interrupt line is asserted.
1041 FALSE specifies a level triggered interrupt that active
1042 when the interrupt line is deasserted.
1043
1044 @return 64-bit data value used to send an MSI to the Local APIC.
1045 **/
1046 UINT64
1047 EFIAPI
1048 GetApicMsiValue (
1049 IN UINT8 Vector,
1050 IN UINTN DeliveryMode,
1051 IN BOOLEAN LevelTriggered,
1052 IN BOOLEAN AssertionLevel
1053 )
1054 {
1055 LOCAL_APIC_MSI_DATA MsiData;
1056
1057 ASSERT (Vector >= 0x10 && Vector <= 0xFE);
1058 ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);
1059
1060 MsiData.Uint64 = 0;
1061 MsiData.Bits.Vector = Vector;
1062 MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;
1063 if (LevelTriggered) {
1064 MsiData.Bits.TriggerMode = 1;
1065 if (AssertionLevel) {
1066 MsiData.Bits.Level = 1;
1067 }
1068 }
1069 return MsiData.Uint64;
1070 }
1071
1072 /**
1073 Get Package ID/Core ID/Thread ID of a processor.
1074
1075 The algorithm assumes the target system has symmetry across physical
1076 package boundaries with respect to the number of logical processors
1077 per package, number of cores per package.
1078
1079 @param[in] InitialApicId Initial APIC ID of the target logical processor.
1080 @param[out] Package Returns the processor package ID.
1081 @param[out] Core Returns the processor core ID.
1082 @param[out] Thread Returns the processor thread ID.
1083 **/
1084 VOID
1085 EFIAPI
1086 GetProcessorLocationByApicId (
1087 IN UINT32 InitialApicId,
1088 OUT UINT32 *Package OPTIONAL,
1089 OUT UINT32 *Core OPTIONAL,
1090 OUT UINT32 *Thread OPTIONAL
1091 )
1092 {
1093 BOOLEAN TopologyLeafSupported;
1094 CPUID_VERSION_INFO_EBX VersionInfoEbx;
1095 CPUID_VERSION_INFO_EDX VersionInfoEdx;
1096 CPUID_CACHE_PARAMS_EAX CacheParamsEax;
1097 CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
1098 CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
1099 CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
1100 CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
1101 CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
1102 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
1103 UINT32 MaxStandardCpuIdIndex;
1104 UINT32 MaxExtendedCpuIdIndex;
1105 UINT32 SubIndex;
1106 UINTN LevelType;
1107 UINT32 MaxLogicProcessorsPerPackage;
1108 UINT32 MaxCoresPerPackage;
1109 UINTN ThreadBits;
1110 UINTN CoreBits;
1111
1112 //
1113 // Check if the processor is capable of supporting more than one logical processor.
1114 //
1115 AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
1116 if (VersionInfoEdx.Bits.HTT == 0) {
1117 if (Thread != NULL) {
1118 *Thread = 0;
1119 }
1120 if (Core != NULL) {
1121 *Core = 0;
1122 }
1123 if (Package != NULL) {
1124 *Package = 0;
1125 }
1126 return;
1127 }
1128
1129 //
1130 // Assume three-level mapping of APIC ID: Package|Core|Thread.
1131 //
1132 ThreadBits = 0;
1133 CoreBits = 0;
1134
1135 //
1136 // Get max index of CPUID
1137 //
1138 AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
1139 AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);
1140
1141 //
1142 // If the extended topology enumeration leaf is available, it
1143 // is the preferred mechanism for enumerating topology.
1144 //
1145 TopologyLeafSupported = FALSE;
1146 if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
1147 AsmCpuidEx(
1148 CPUID_EXTENDED_TOPOLOGY,
1149 0,
1150 &ExtendedTopologyEax.Uint32,
1151 &ExtendedTopologyEbx.Uint32,
1152 &ExtendedTopologyEcx.Uint32,
1153 NULL
1154 );
1155 //
1156 // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
1157 // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
1158 // supported on that processor.
1159 //
1160 if (ExtendedTopologyEbx.Uint32 != 0) {
1161 TopologyLeafSupported = TRUE;
1162
1163 //
1164 // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
1165 // the SMT sub-field of x2APIC ID.
1166 //
1167 LevelType = ExtendedTopologyEcx.Bits.LevelType;
1168 ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
1169 ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
1170
1171 //
1172 // Software must not assume any "level type" encoding
1173 // value to be related to any sub-leaf index, except sub-leaf 0.
1174 //
1175 SubIndex = 1;
1176 do {
1177 AsmCpuidEx (
1178 CPUID_EXTENDED_TOPOLOGY,
1179 SubIndex,
1180 &ExtendedTopologyEax.Uint32,
1181 NULL,
1182 &ExtendedTopologyEcx.Uint32,
1183 NULL
1184 );
1185 LevelType = ExtendedTopologyEcx.Bits.LevelType;
1186 if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
1187 CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
1188 break;
1189 }
1190 SubIndex++;
1191 } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
1192 }
1193 }
1194
1195 if (!TopologyLeafSupported) {
1196 //
1197 // Get logical processor count
1198 //
1199 AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
1200 MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
1201
1202 //
1203 // Assume single-core processor
1204 //
1205 MaxCoresPerPackage = 1;
1206
1207 //
1208 // Check for topology extensions on AMD processor
1209 //
1210 if (StandardSignatureIsAuthenticAMD()) {
1211 if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
1212 AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
1213 if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
1214 //
1215 // Account for max possible thread count to decode ApicId
1216 //
1217 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);
1218 MaxLogicProcessorsPerPackage = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
1219
1220 //
1221 // Get cores per processor package
1222 //
1223 AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, NULL, NULL);
1224 MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
1225 }
1226 }
1227 }
1228 else {
1229 //
1230 // Extract core count based on CACHE information
1231 //
1232 if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
1233 AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
1234 if (CacheParamsEax.Uint32 != 0) {
1235 MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
1236 }
1237 }
1238 }
1239
1240 ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
1241 CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
1242 }
1243
1244 if (Thread != NULL) {
1245 *Thread = InitialApicId & ((1 << ThreadBits) - 1);
1246 }
1247 if (Core != NULL) {
1248 *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
1249 }
1250 if (Package != NULL) {
1251 *Package = (InitialApicId >> (ThreadBits + CoreBits));
1252 }
1253 }
1254
1255 /**
1256 Get Package ID/Die ID/Tile ID/Module ID/Core ID/Thread ID of a processor.
1257
1258 The algorithm assumes the target system has symmetry across physical
1259 package boundaries with respect to the number of threads per core, number of
1260 cores per module, number of modules per tile, number of tiles per die, number
1261 of dies per package.
1262
1263 @param[in] InitialApicId Initial APIC ID of the target logical processor.
1264 @param[out] Package Returns the processor package ID.
1265 @param[out] Die Returns the processor die ID.
1266 @param[out] Tile Returns the processor tile ID.
1267 @param[out] Module Returns the processor module ID.
1268 @param[out] Core Returns the processor core ID.
1269 @param[out] Thread Returns the processor thread ID.
1270 **/
1271 VOID
1272 EFIAPI
1273 GetProcessorLocation2ByApicId (
1274 IN UINT32 InitialApicId,
1275 OUT UINT32 *Package OPTIONAL,
1276 OUT UINT32 *Die OPTIONAL,
1277 OUT UINT32 *Tile OPTIONAL,
1278 OUT UINT32 *Module OPTIONAL,
1279 OUT UINT32 *Core OPTIONAL,
1280 OUT UINT32 *Thread OPTIONAL
1281 )
1282 {
1283 CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
1284 CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
1285 UINT32 MaxStandardCpuIdIndex;
1286 UINT32 Index;
1287 UINTN LevelType;
1288 UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
1289 UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
1290
1291 for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) {
1292 Bits[LevelType] = 0;
1293 }
1294
1295 //
1296 // Get max index of CPUID
1297 //
1298 AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
1299 if (MaxStandardCpuIdIndex < CPUID_V2_EXTENDED_TOPOLOGY) {
1300 if (Die != NULL) {
1301 *Die = 0;
1302 }
1303 if (Tile != NULL) {
1304 *Tile = 0;
1305 }
1306 if (Module != NULL) {
1307 *Module = 0;
1308 }
1309 GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);
1310 return;
1311 }
1312
1313 //
1314 // If the V2 extended topology enumeration leaf is available, it
1315 // is the preferred mechanism for enumerating topology.
1316 //
1317 for (Index = 0; ; Index++) {
1318 AsmCpuidEx(
1319 CPUID_V2_EXTENDED_TOPOLOGY,
1320 Index,
1321 &ExtendedTopologyEax.Uint32,
1322 NULL,
1323 &ExtendedTopologyEcx.Uint32,
1324 NULL
1325 );
1326
1327 LevelType = ExtendedTopologyEcx.Bits.LevelType;
1328
1329 //
1330 // first level reported should be SMT.
1331 //
1332 ASSERT ((Index != 0) || (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT));
1333 if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {
1334 break;
1335 }
1336 ASSERT (LevelType < ARRAY_SIZE (Bits));
1337 Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift;
1338 }
1339
1340 for (LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE; LevelType < ARRAY_SIZE (Bits); LevelType++) {
1341 //
1342 // If there are more levels between level-1 (low-level) and level-2 (high-level), the unknown levels will be ignored
1343 // and treated as an extension of the last known level (i.e., level-1 in this case).
1344 //
1345 if (Bits[LevelType] == 0) {
1346 Bits[LevelType] = Bits[LevelType - 1];
1347 }
1348 }
1349
1350 Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package;
1351 Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE ] = Die;
1352 Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE ] = Tile;
1353 Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE ] = Module;
1354 Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE ] = Core;
1355 Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT ] = Thread;
1356
1357 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32;
1358
1359 for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT
1360 ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1
1361 ; LevelType ++
1362 ) {
1363 if (Location[LevelType] != NULL) {
1364 //
1365 // Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique
1366 // topology ID of the next level type.
1367 //
1368 *Location[LevelType] = InitialApicId >> Bits[LevelType - 1];
1369
1370 //
1371 // Bits[i] - Bits[i-1] holds the number of bits for the next ONE level type.
1372 //
1373 *Location[LevelType] &= (1 << (Bits[LevelType] - Bits[LevelType - 1])) - 1;
1374 }
1375 }
1376 }
EFI Development Kit II mirror for PVE