UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c

   1 /** @file
   2   Protected Processor Inventory Number(PPIN) feature.
   3
   4   Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9 #include "CpuCommonFeatures.h"
  10
  11 /**
  12   Prepares for the data used by CPU feature detection and initialization.
  13
  14   @param[in]  NumberOfProcessors  The number of CPUs in the platform.
  15
  16   @return  Pointer to a buffer of CPU related configuration data.
  17
  18   @note This service could be called by BSP only.
  19 **/
  20 VOID *
  21 EFIAPI
  22 PpinGetConfigData (
  23   IN UINTN  NumberOfProcessors
  24   )
  25 {
  26   VOID  *ConfigData;
  27
  28   ConfigData = AllocateZeroPool (sizeof (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER) * NumberOfProcessors);
  29   ASSERT (ConfigData != NULL);
  30   return ConfigData;
  31 }
  32
  33 /**
  34   Detects if Protected Processor Inventory Number feature supported on current
  35   processor.
  36
  37   @param[in]  ProcessorNumber  The index of the CPU executing this function.
  38   @param[in]  CpuInfo          A pointer to the REGISTER_CPU_FEATURE_INFORMATION
  39                                structure for the CPU executing this function.
  40   @param[in]  ConfigData       A pointer to the configuration buffer returned
  41                                by CPU_FEATURE_GET_CONFIG_DATA.  NULL if
  42                                CPU_FEATURE_GET_CONFIG_DATA was not provided in
  43                                RegisterCpuFeature().
  44
  45   @retval TRUE     Protected Processor Inventory Number feature is supported.
  46   @retval FALSE    Protected Processor Inventory Number feature is not supported.
  47
  48   @note This service could be called by BSP/APs.
  49 **/
  50 BOOLEAN
  51 EFIAPI
  52 PpinSupport (
  53   IN UINTN                             ProcessorNumber,
  54   IN REGISTER_CPU_FEATURE_INFORMATION  *CpuInfo,
  55   IN VOID                              *ConfigData  OPTIONAL
  56   )
  57 {
  58   MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER  PlatformInfo;
  59   MSR_IVY_BRIDGE_PPIN_CTL_REGISTER         *MsrPpinCtrl;
  60
  61   if ((CpuInfo->DisplayFamily == 0x06) &&
  62       ((CpuInfo->DisplayModel == 0x3E) ||      // Xeon E5 V2
  63        (CpuInfo->DisplayModel == 0x56) ||      // Xeon Processor D Product
  64        (CpuInfo->DisplayModel == 0x4F) ||      // Xeon E5 v4, E7 v4
  65        (CpuInfo->DisplayModel == 0x55) ||      // Xeon Processor Scalable
  66        (CpuInfo->DisplayModel == 0x57) ||      // Xeon Phi processor 3200, 5200, 7200 series.
  67        (CpuInfo->DisplayModel == 0x85)         // Future Xeon phi processor
  68       ))
  69   {
  70     //
  71     // Check whether platform support this feature.
  72     //
  73     PlatformInfo.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);
  74     if (PlatformInfo.Bits.PPIN_CAP != 0) {
  75       MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;
  76       ASSERT (MsrPpinCtrl != NULL);
  77       MsrPpinCtrl[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);
  78       return TRUE;
  79     }
  80   }
  81
  82   return FALSE;
  83 }
  84
  85 /**
  86   Initializes Protected Processor Inventory Number feature to specific state.
  87
  88   @param[in]  ProcessorNumber  The index of the CPU executing this function.
  89   @param[in]  CpuInfo          A pointer to the REGISTER_CPU_FEATURE_INFORMATION
  90                                structure for the CPU executing this function.
  91   @param[in]  ConfigData       A pointer to the configuration buffer returned
  92                                by CPU_FEATURE_GET_CONFIG_DATA.  NULL if
  93                                CPU_FEATURE_GET_CONFIG_DATA was not provided in
  94                                RegisterCpuFeature().
  95   @param[in]  State            If TRUE, then the Protected Processor Inventory
  96                                Number feature must be enabled.
  97                                If FALSE, then the Protected Processor Inventory
  98                                Number feature must be disabled.
  99
 100   @retval RETURN_SUCCESS       Protected Processor Inventory Number feature is
 101                                initialized.
 102   @retval RETURN_DEVICE_ERROR  Device can't change state because it has been
 103                                locked.
 104
 105   @note This service could be called by BSP only.
 106 **/
 107 RETURN_STATUS
 108 EFIAPI
 109 PpinInitialize (
 110   IN UINTN                             ProcessorNumber,
 111   IN REGISTER_CPU_FEATURE_INFORMATION  *CpuInfo,
 112   IN VOID                              *ConfigData   OPTIONAL,
 113   IN BOOLEAN                           State
 114   )
 115 {
 116   MSR_IVY_BRIDGE_PPIN_CTL_REGISTER  *MsrPpinCtrl;
 117
 118   MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;
 119   ASSERT (MsrPpinCtrl != NULL);
 120
 121   //
 122   // Check whether processor already lock this register.
 123   // If already locked, just based on the request state and
 124   // the current state to return the status.
 125   //
 126   if (MsrPpinCtrl[ProcessorNumber].Bits.LockOut != 0) {
 127     return MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN == State ? RETURN_SUCCESS : RETURN_DEVICE_ERROR;
 128   }
 129
 130   //
 131   // Support function already check the processor which support PPIN feature, so this function not need
 132   // to check the processor again.
 133   //
 134   // The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only program MSR_IVY_BRIDGE_PPIN_CTL
 135   // once for each package.
 136   //
 137   if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) {
 138     return RETURN_SUCCESS;
 139   }
 140
 141   if (State) {
 142     //
 143     // Enable and Unlock.
 144     // According to SDM, once Enable_PPIN is set, attempt to write 1 to LockOut will cause #GP.
 145     //
 146     MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 1;
 147     MsrPpinCtrl[ProcessorNumber].Bits.LockOut     = 0;
 148   } else {
 149     //
 150     // Disable and Lock.
 151     // According to SDM, writing 1 to LockOut is permitted only if Enable_PPIN is clear.
 152     //
 153     MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 0;
 154     MsrPpinCtrl[ProcessorNumber].Bits.LockOut     = 1;
 155   }
 156
 157   CPU_REGISTER_TABLE_WRITE64 (
 158     ProcessorNumber,
 159     Msr,
 160     MSR_IVY_BRIDGE_PPIN_CTL,
 161     MsrPpinCtrl[ProcessorNumber].Uint64
 162     );
 163
 164   return RETURN_SUCCESS;
 165 }