UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h

   1 /** @file
   2   Internal header for CpuPageTableLib.
   3
   4   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9 #ifndef CPU_PAGE_TABLE_H_
  10 #define CPU_PAGE_TABLE_H_
  11
  12 #include <Base.h>
  13 #include <Library/BaseLib.h>
  14 #include <Library/BaseMemoryLib.h>
  15 #include <Library/DebugLib.h>
  16 #include <Library/CpuPageTableLib.h>
  17
  18 #define IA32_PE_BASE_ADDRESS_MASK_40  0xFFFFFFFFFF000ull
  19 #define IA32_PE_BASE_ADDRESS_MASK_39  0xFFFFFFFFFE000ull
  20
  21 #define REGION_LENGTH(l)  LShiftU64 (1, (l) * 9 + 3)
  22
  23 typedef struct {
  24   UINT64    Present        : 1;       // 0 = Not present in memory, 1 = Present in memory
  25   UINT64    ReadWrite      : 1;       // 0 = Read-Only, 1= Read/Write
  26   UINT64    UserSupervisor : 1;       // 0 = Supervisor, 1=User
  27   UINT64    Reserved       : 58;
  28   UINT64    Nx             : 1;        // No Execute bit
  29 } IA32_PAGE_COMMON_ENTRY;
  30
  31 ///
  32 /// Format of a non-leaf entry that references a page table entry
  33 ///
  34 typedef union {
  35   struct {
  36     UINT64    Present              : 1; // 0 = Not present in memory, 1 = Present in memory
  37     UINT64    ReadWrite            : 1; // 0 = Read-Only, 1= Read/Write
  38     UINT64    UserSupervisor       : 1; // 0 = Supervisor, 1=User
  39     UINT64    WriteThrough         : 1; // 0 = Write-Back caching, 1=Write-Through caching
  40     UINT64    CacheDisabled        : 1; // 0 = Cached, 1=Non-Cached
  41     UINT64    Accessed             : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
  42     UINT64    Available0           : 1; // Ignored
  43     UINT64    MustBeZero           : 1; // Must Be Zero
  44
  45     UINT64    Available2           : 4; // Ignored
  46
  47     UINT64    PageTableBaseAddress : 40; // Page Table Base Address
  48     UINT64    Available3           : 11; // Ignored
  49     UINT64    Nx                   : 1;  // No Execute bit
  50   } Bits;
  51   UINT64    Uint64;
  52 } IA32_PAGE_NON_LEAF_ENTRY;
  53
  54 #define IA32_PNLE_PAGE_TABLE_BASE_ADDRESS(pa)  ((pa)->Uint64 & IA32_PE_BASE_ADDRESS_MASK_40)
  55
  56 ///
  57 /// Format of a PML5 Entry (PML5E) that References a PML4 Table
  58 ///
  59 typedef IA32_PAGE_NON_LEAF_ENTRY IA32_PML5E;
  60
  61 ///
  62 /// Format of a PML4 Entry (PML4E) that References a Page-Directory-Pointer Table
  63 ///
  64 typedef IA32_PAGE_NON_LEAF_ENTRY IA32_PML4E;
  65
  66 ///
  67 /// Format of a Page-Directory-Pointer-Table Entry (PDPTE) that References a Page Directory
  68 ///
  69 typedef IA32_PAGE_NON_LEAF_ENTRY IA32_PDPTE;
  70
  71 ///
  72 /// Format of a Page-Directory Entry that References a Page Table
  73 ///
  74 typedef IA32_PAGE_NON_LEAF_ENTRY IA32_PDE;
  75
  76 ///
  77 /// Format of a leaf entry that Maps a 1-Gbyte or 2-MByte Page
  78 ///
  79 typedef union {
  80   struct {
  81     UINT64    Present              : 1; // 0 = Not present in memory, 1 = Present in memory
  82     UINT64    ReadWrite            : 1; // 0 = Read-Only, 1= Read/Write
  83     UINT64    UserSupervisor       : 1; // 0 = Supervisor, 1=User
  84     UINT64    WriteThrough         : 1; // 0 = Write-Back caching, 1=Write-Through caching
  85     UINT64    CacheDisabled        : 1; // 0 = Cached, 1=Non-Cached
  86     UINT64    Accessed             : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
  87     UINT64    Dirty                : 1; // 0 = Not dirty, 1 = Dirty (set by CPU)
  88     UINT64    MustBeOne            : 1; // Page Size. Must Be One
  89
  90     UINT64    Global               : 1; // 0 = Not global, 1 = Global (if CR4.PGE = 1)
  91     UINT64    Available1           : 3; // Ignored
  92     UINT64    Pat                  : 1; // PAT
  93
  94     UINT64    PageTableBaseAddress : 39; // Page Table Base Address
  95     UINT64    Available3           : 7;  // Ignored
  96     UINT64    ProtectionKey        : 4;  // Protection key
  97     UINT64    Nx                   : 1;  // No Execute bit
  98   } Bits;
  99   UINT64    Uint64;
 100 } IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE;
 101 #define IA32_PLEB_PAGE_TABLE_BASE_ADDRESS(pa)  ((pa)->Uint64 & IA32_PE_BASE_ADDRESS_MASK_39)
 102
 103 ///
 104 /// Format of a Page-Directory Entry that Maps a 2-MByte Page
 105 ///
 106 typedef IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE IA32_PDE_2M;
 107
 108 ///
 109 /// Format of a Page-Directory-Pointer-Table Entry (PDPTE) that Maps a 1-GByte Page
 110 ///
 111 typedef IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE IA32_PDPTE_1G;
 112
 113 ///
 114 /// Format of a Page-Table Entry that Maps a 4-KByte Page
 115 ///
 116 typedef union {
 117   struct {
 118     UINT64    Present              : 1; // 0 = Not present in memory, 1 = Present in memory
 119     UINT64    ReadWrite            : 1; // 0 = Read-Only, 1= Read/Write
 120     UINT64    UserSupervisor       : 1; // 0 = Supervisor, 1=User
 121     UINT64    WriteThrough         : 1; // 0 = Write-Back caching, 1=Write-Through caching
 122     UINT64    CacheDisabled        : 1; // 0 = Cached, 1=Non-Cached
 123     UINT64    Accessed             : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
 124     UINT64    Dirty                : 1; // 0 = Not dirty, 1 = Dirty (set by CPU)
 125     UINT64    Pat                  : 1; // PAT
 126
 127     UINT64    Global               : 1; // 0 = Not global, 1 = Global (if CR4.PGE = 1)
 128     UINT64    Available1           : 3; // Ignored
 129
 130     UINT64    PageTableBaseAddress : 40; // Page Table Base Address
 131     UINT64    Available3           : 7;  // Ignored
 132     UINT64    ProtectionKey        : 4;  // Protection key
 133     UINT64    Nx                   : 1;  // No Execute bit
 134   } Bits;
 135   UINT64    Uint64;
 136 } IA32_PTE_4K;
 137 #define IA32_PTE4K_PAGE_TABLE_BASE_ADDRESS(pa)  ((pa)->Uint64 & IA32_PE_BASE_ADDRESS_MASK_40)
 138
 139 ///
 140 /// Format of a Page-Directory-Pointer-Table Entry (PDPTE) that References a Page Directory (32bit PAE specific)
 141 ///
 142 typedef union {
 143   struct {
 144     UINT64    Present              : 1; // 0 = Not present in memory, 1 = Present in memory
 145     UINT64    MustBeZero           : 2; // Must Be Zero
 146     UINT64    WriteThrough         : 1; // 0 = Write-Back caching, 1=Write-Through caching
 147     UINT64    CacheDisabled        : 1; // 0 = Cached, 1=Non-Cached
 148     UINT64    MustBeZero2          : 4; // Must Be Zero
 149
 150     UINT64    Available            : 3; // Ignored
 151
 152     UINT64    PageTableBaseAddress : 40; // Page Table Base Address
 153     UINT64    MustBeZero3          : 12; // Must Be Zero
 154   } Bits;
 155   UINT64    Uint64;
 156 } IA32_PDPTE_PAE;
 157
 158 typedef union {
 159   IA32_PAGE_NON_LEAF_ENTRY             Pnle; // To access Pml5, Pml4, Pdpte and Pde.
 160   IA32_PML5E                           Pml5;
 161   IA32_PML4E                           Pml4;
 162   IA32_PDPTE                           Pdpte;
 163   IA32_PDE                             Pde;
 164
 165   IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE    PleB; // to access Pdpte1G and Pde2M.
 166   IA32_PDPTE_1G                        Pdpte1G;
 167   IA32_PDE_2M                          Pde2M;
 168
 169   IA32_PTE_4K                          Pte4K;
 170
 171   IA32_PDPTE_PAE                       PdptePae;
 172   IA32_PAGE_COMMON_ENTRY               Pce; // To access all common bits in above entries.
 173
 174   UINT64                               Uint64;
 175   UINTN                                Uintn;
 176 } IA32_PAGING_ENTRY;
 177
 178 /**
 179   Return TRUE when the page table entry is a leaf entry that points to the physical address memory.
 180   Return FALSE when the page table entry is a non-leaf entry that points to the page table entries.
 181
 182   @param[in] PagingEntry Pointer to the page table entry.
 183   @param[in] Level       Page level where the page table entry resides in.
 184
 185   @retval TRUE  It's a leaf entry.
 186   @retval FALSE It's a non-leaf entry.
 187 **/
 188 BOOLEAN
 189 IsPle (
 190   IN     IA32_PAGING_ENTRY  *PagingEntry,
 191   IN     UINTN              Level
 192   );
 193
 194 /**
 195   Return the attribute of a 2M/1G page table entry.
 196
 197   @param[in] PleB               Pointer to a 2M/1G page table entry.
 198   @param[in] ParentMapAttribute Pointer to the parent attribute.
 199
 200   @return Attribute of the 2M/1G page table entry.
 201 **/
 202 UINT64
 203 PageTableLibGetPleBMapAttribute (
 204   IN IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE  *PleB,
 205   IN IA32_MAP_ATTRIBUTE                 *ParentMapAttribute
 206   );
 207
 208 /**
 209   Return the attribute of a non-leaf page table entry.
 210
 211   @param[in] Pnle               Pointer to a non-leaf page table entry.
 212   @param[in] ParentMapAttribute Pointer to the parent attribute.
 213
 214   @return Attribute of the non-leaf page table entry.
 215 **/
 216 UINT64
 217 PageTableLibGetPnleMapAttribute (
 218   IN IA32_PAGE_NON_LEAF_ENTRY  *Pnle,
 219   IN IA32_MAP_ATTRIBUTE        *ParentMapAttribute
 220   );
 221
 222 #endif