1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR>
3 ; SPDX-License-Identifier: BSD-2-Clause-Patent
11 ; This is the equates file for Multiple Processor support
13 ;-------------------------------------------------------------------------------
16 CPU_SWITCH_STATE_IDLE equ 0
17 CPU_SWITCH_STATE_STORED equ 1
18 CPU_SWITCH_STATE_LOADED equ 2
21 ; Equivalent NASM structure of MP_ASSEMBLY_ADDRESS_MAP
23 struc MP_ASSEMBLY_ADDRESS_MAP
24 .RendezvousFunnelAddress CTYPE_UINTN 1
25 .ModeEntryOffset CTYPE_UINTN 1
26 .RendezvousFunnelSize CTYPE_UINTN 1
27 .RelocateApLoopFuncAddress CTYPE_UINTN 1
28 .RelocateApLoopFuncSize CTYPE_UINTN 1
29 .RelocateApLoopFuncAddressAmd CTYPE_UINTN 1
30 .RelocateApLoopFuncSizeAmd CTYPE_UINTN 1
31 .ModeTransitionOffset CTYPE_UINTN 1
32 .SwitchToRealNoNxOffset CTYPE_UINTN 1
33 .SwitchToRealPM16ModeOffset CTYPE_UINTN 1
34 .SwitchToRealPM16ModeSize CTYPE_UINTN 1
38 ; Equivalent NASM structure of IA32_DESCRIPTOR
46 ; Equivalent NASM structure of CPU_EXCHANGE_ROLE_INFO
48 struc CPU_EXCHANGE_ROLE_INFO
49 ; State is defined as UINT8 in C header file
50 ; Define it as UINTN here to guarantee the fields that follow State
51 ; is naturally aligned. The structure layout doesn't change.
53 .StackPointer CTYPE_UINTN 1
54 .Gdtr CTYPE_UINT8 IA32_DESCRIPTOR_size
55 .Idtr CTYPE_UINT8 IA32_DESCRIPTOR_size
59 ; Equivalent NASM structure of CPU_INFO_IN_HOB
62 .InitialApicId CTYPE_UINT32 1
63 .ApicId CTYPE_UINT32 1
64 .Health CTYPE_UINT32 1
65 .ApTopOfStack CTYPE_UINT64 1
69 ; Equivalent NASM structure of MP_CPU_EXCHANGE_INFO
71 struc MP_CPU_EXCHANGE_INFO
72 .StackStart: CTYPE_UINTN 1
73 .StackSize: CTYPE_UINTN 1
74 .CFunction: CTYPE_UINTN 1
75 .GdtrProfile: CTYPE_UINT8 IA32_DESCRIPTOR_size
76 .IdtrProfile: CTYPE_UINT8 IA32_DESCRIPTOR_size
77 .BufferStart: CTYPE_UINTN 1
78 .ModeOffset: CTYPE_UINTN 1
79 .ApIndex: CTYPE_UINTN 1
80 .CodeSegment: CTYPE_UINTN 1
81 .DataSegment: CTYPE_UINTN 1
82 .EnableExecuteDisable: CTYPE_UINTN 1
84 .InitFlag: CTYPE_UINTN 1
85 .CpuInfo: CTYPE_UINTN 1
86 .NumApsExecuting: CTYPE_UINTN 1
87 .CpuMpData: CTYPE_UINTN 1
88 .InitializeFloatingPointUnits: CTYPE_UINTN 1
89 .ModeTransitionMemory: CTYPE_UINT32 1
90 .ModeTransitionSegment: CTYPE_UINT16 1
91 .ModeHighMemory: CTYPE_UINT32 1
92 .ModeHighSegment: CTYPE_UINT16 1
93 .Enable5LevelPaging: CTYPE_BOOLEAN 1
94 .SevEsIsEnabled: CTYPE_BOOLEAN 1
95 .SevSnpIsEnabled CTYPE_BOOLEAN 1
96 .GhcbBase: CTYPE_UINTN 1
97 .ExtTopoAvail: CTYPE_BOOLEAN 1
100 MP_CPU_EXCHANGE_INFO_OFFSET equ (Flat32Start - RendezvousFunnelProcStart)
101 %define MP_CPU_EXCHANGE_INFO_FIELD(Field) (MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO. %+ Field)