1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
3 ; This program and the accompanying materials
4 ; are licensed and made available under the terms and conditions of the BSD License
5 ; which accompanies this distribution. The full text of the license may be found at
6 ; http://opensource.org/licenses/bsd-license.php.
8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 ; This is the assembly code for MP support
19 ;-------------------------------------------------------------------------------
22 extern ASM_PFX(InitializeFloatingPointUnits)
28 ;-------------------------------------------------------------------------------------
29 ;RendezvousFunnelProc procedure follows. All APs execute their procedure. This
30 ;procedure serializes all the AP processors through an Init sequence. It must be
31 ;noted that APs arrive here very raw...ie: real mode, no stack.
32 ;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC
34 ;-------------------------------------------------------------------------------------
35 global ASM_PFX(RendezvousFunnelProc)
36 ASM_PFX(RendezvousFunnelProc):
37 RendezvousFunnelProcStart:
38 ; At this point CS = 0x(vv00) and ip= 0x0.
39 ; Save BIST information to ebp firstly
42 mov ebp, eax ; Save BIST information
52 mov si, BufferStartLocation
55 mov di, ModeOffsetLocation
57 mov di, CodeSegmentLocation
61 mov [di],dx ; Patch long mode CS
64 mov [di],eax ; Patch address
72 mov si, EnableExecuteDisableLocation
74 jz SkipEnableExecuteDisableBit
77 ; Enable execute disable bit
79 mov ecx, 0c0000080h ; EFER MSR number
81 bts eax, 11 ; Enable Execute Disable Bit
84 SkipEnableExecuteDisableBit:
86 mov di, DataSegmentLocation
87 mov edi, [di] ; Save long mode DS in edi
89 mov si, Cr3Location ; Save CR3 in ecx
93 mov ds, ax ; Clear data segment
95 mov eax, cr0 ; Get control register 0
96 or eax, 000000003h ; Set PE bit (bit #0) & MP
103 mov cr3, ecx ; Load CR3
105 mov ecx, 0c0000080h ; EFER MSR number
107 bts eax, 8 ; Set LME=1
110 mov eax, cr0 ; Read CR0
111 bts eax, 31 ; Set PG=1
112 mov cr0, eax ; Write CR0
114 jmp 0:strict dword 0 ; far jump to long mode
123 lea edi, [esi + InitFlagLocation]
124 cmp qword [edi], 1 ; ApInitConfig
129 add edi, LockLocation
130 mov rax, NotVacantFlag
133 xchg qword [edi], rax
134 cmp rax, NotVacantFlag
137 lea ecx, [esi + NumApsExecutingLocation]
143 xchg qword [edi], rax
146 add edi, StackSizeLocation
150 mul ecx ; EAX = StackSize * (CpuNumber + 1)
152 add edi, StackStartAddressLocation
161 jb NoX2Apic ; CPUID level below CPUID_EXTENDED_TOPOLOGY
167 jz NoX2Apic ; CPUID.0BH:EBX[15:0] is zero
169 ; Processor is x2APIC capable; 32-bit x2APIC ID is already in EDX
170 jmp GetProcessorNumber
173 ; Processor is not x2APIC capable, so get 8-bit APIC ID
181 ; Get processor number for this AP
182 ; Note that BSP may become an AP due to SwitchBsp()
185 lea eax, [esi + CpuInfoLocation]
189 cmp dword [edi], edx ; APIC ID match?
193 jmp GetNextProcNumber
196 mov rsp, qword [edi + 12]
199 push rbp ; Push BIST data at top of AP stack
200 xor rbp, rbp ; Clear ebp for call stack trace
204 mov rax, ASM_PFX(InitializeFloatingPointUnits)
206 call rax ; Call assembly function to initialize FPU per UEFI spec
209 mov edx, ebx ; edx is NumApsExecuting
211 add ecx, LockLocation ; rcx is address of exchange info data buffer
214 add edi, ApProcedureLocation
218 call rax ; Invoke C function
220 jmp $ ; Should never reach here
222 RendezvousFunnelProcEnd:
224 ;-------------------------------------------------------------------------------------
225 ; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfApStack, CountTofinish);
226 ;-------------------------------------------------------------------------------------
227 global ASM_PFX(AsmRelocateApLoop)
228 ASM_PFX(AsmRelocateApLoop):
229 AsmRelocateApLoopStart:
230 mov rax, [rsp + 40] ; CountTofinish
231 lock dec dword [rax] ; (*CountTofinish)--
236 lea rsi, [PmEntry] ; rsi <- The start address of transition code
245 btr eax, 31 ; Clear CR0.PG
246 mov cr0, eax ; Disable paging and caches
248 mov ebx, edx ; Save EntryPoint to rbx, for rdmsr will overwrite rdx
251 and ah, ~ 1 ; Clear LME
254 and al, ~ (1 << 5) ; Clear PAE
261 cmp cl, 1 ; Check mwait-monitor support
263 mov ebx, edx ; Save C-State to ebx
265 mov eax, esp ; Set Monitor Address
266 xor ecx, ecx ; ecx = 0
267 xor edx, edx ; edx = 0
270 mov eax, ebx ; Mwait Cx, Target C-State per eax[7:4]
279 AsmRelocateApLoopEnd:
281 ;-------------------------------------------------------------------------------------
282 ; AsmGetAddressMap (&AddressMap);
283 ;-------------------------------------------------------------------------------------
284 global ASM_PFX(AsmGetAddressMap)
285 ASM_PFX(AsmGetAddressMap):
286 mov rax, ASM_PFX(RendezvousFunnelProc)
288 mov qword [rcx + 8h], LongModeStart - RendezvousFunnelProcStart
289 mov qword [rcx + 10h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart
290 mov rax, ASM_PFX(AsmRelocateApLoop)
291 mov qword [rcx + 18h], rax
292 mov qword [rcx + 20h], AsmRelocateApLoopEnd - AsmRelocateApLoopStart
295 ;-------------------------------------------------------------------------------------
296 ;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is
297 ;about to become an AP. It switches its stack with the current AP.
298 ;AsmExchangeRole (IN CPU_EXCHANGE_INFO *MyInfo, IN CPU_EXCHANGE_INFO *OthersInfo);
299 ;-------------------------------------------------------------------------------------
300 global ASM_PFX(AsmExchangeRole)
301 ASM_PFX(AsmExchangeRole):
302 ; DO NOT call other functions in this function, since 2 CPU may use 1 stack
303 ; at the same time. If 1 CPU try to call a function, stack will be corrupted.
327 ; rsi contains MyInfo pointer
330 ; rdi contains OthersInfo pointer
333 ;Store EFLAGS, GDTR and IDTR regiter to stack
338 ; Store the its StackPointer
341 ; update its switch state to STORED
342 mov byte [rsi], CPU_SWITCH_STATE_STORED
345 ; wait until the other CPU finish storing its state
346 cmp byte [rdi], CPU_SWITCH_STATE_STORED
349 jmp WaitForOtherStored
352 ; Since another CPU already stored its state, load them
359 ; load its future StackPointer
362 ; update the other CPU's switch state to LOADED
363 mov byte [rdi], CPU_SWITCH_STATE_LOADED
366 ; wait until the other CPU finish loading new state,
367 ; otherwise the data in stack may corrupt
368 cmp byte [rsi], CPU_SWITCH_STATE_LOADED
371 jmp WaitForOtherLoaded
374 ; since the other CPU already get the data it want, leave this procedure