UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm

   1 ;------------------------------------------------------------------------------ ;
   2 ; Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
   3 ; This program and the accompanying materials
   4 ; are licensed and made available under the terms and conditions of the BSD License
   5 ; which accompanies this distribution.  The full text of the license may be found at
   6 ; http://opensource.org/licenses/bsd-license.php.
   7 ;
   8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
   9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  10 ;
  11 ; Module Name:
  12 ;
  13 ;   SmiException.nasm
  14 ;
  15 ; Abstract:
  16 ;
  17 ;   Exception handlers used in SM mode
  18 ;
  19 ;-------------------------------------------------------------------------------
  20
  21 %include "StuffRsb.inc"
  22
  23 global  ASM_PFX(gcStmPsd)
  24
  25 extern  ASM_PFX(SmmStmExceptionHandler)
  26 extern  ASM_PFX(SmmStmSetup)
  27 extern  ASM_PFX(SmmStmTeardown)
  28 extern  ASM_PFX(gStmXdSupported)
  29 extern  ASM_PFX(gStmSmiHandlerIdtr)
  30
  31 %define MSR_IA32_MISC_ENABLE 0x1A0
  32 %define MSR_EFER      0xc0000080
  33 %define MSR_EFER_XD   0x800
  34
  35 CODE_SEL          equ 0x08
  36 DATA_SEL          equ 0x20
  37 TSS_SEL           equ 0x40
  38
  39     SECTION .data
  40
  41 ASM_PFX(gcStmPsd):
  42             DB      'TXTPSSIG'
  43             DW      PSD_SIZE
  44             DW      1              ; Version
  45             DD      0              ; LocalApicId
  46             DB      0x05           ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr
  47             DB      0              ; BIOS to STM
  48             DB      0              ; STM to BIOS
  49             DB      0
  50             DW      CODE_SEL
  51             DW      DATA_SEL
  52             DW      DATA_SEL
  53             DW      DATA_SEL
  54             DW      TSS_SEL
  55             DW      0
  56             DQ      0              ; SmmCr3
  57             DD      ASM_PFX(OnStmSetup)
  58             DD      0
  59             DD      ASM_PFX(OnStmTeardown)
  60             DD      0
  61             DQ      0              ; SmmSmiHandlerRip - SMM guest entrypoint
  62             DQ      0              ; SmmSmiHandlerRsp
  63             DQ      0
  64             DD      0
  65             DD      0x80010100     ; RequiredStmSmmRevId
  66             DD      ASM_PFX(OnException)
  67             DD      0
  68             DQ      0              ; ExceptionStack
  69             DW      DATA_SEL
  70             DW      0x01F          ; ExceptionFilter
  71             DD      0
  72             DD      0
  73             DD      0
  74             DQ      0              ; BiosHwResourceRequirementsPtr
  75             DQ      0              ; AcpiRsdp
  76             DB      0              ; PhysicalAddressBits
  77 PSD_SIZE  equ $ - ASM_PFX(gcStmPsd)
  78
  79     SECTION .text
  80 ;------------------------------------------------------------------------------
  81 ; SMM Exception handlers
  82 ;------------------------------------------------------------------------------
  83 global ASM_PFX(OnException)
  84 ASM_PFX(OnException):
  85     mov  ecx, esp
  86     push ecx
  87     call ASM_PFX(SmmStmExceptionHandler)
  88     add  esp, 4
  89
  90     mov  ebx, eax
  91     mov  eax, 4
  92     vmcall
  93     jmp $
  94
  95 global ASM_PFX(OnStmSetup)
  96 ASM_PFX(OnStmSetup):
  97 ;
  98 ; Check XD disable bit
  99 ;
 100     xor     esi, esi
 101     mov     eax, ASM_PFX(gStmXdSupported)
 102     mov     al, [eax]
 103     cmp     al, 0
 104     jz      @StmXdDone1
 105     mov     ecx, MSR_IA32_MISC_ENABLE
 106     rdmsr
 107     mov     esi, edx                   ; save MSR_IA32_MISC_ENABLE[63-32]
 108     test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]
 109     jz      .51
 110     and     dx, 0xFFFB                 ; clear XD Disable bit if it is set
 111     wrmsr
 112 .51:
 113     mov     ecx, MSR_EFER
 114     rdmsr
 115     or      ax, MSR_EFER_XD             ; enable NXE
 116     wrmsr
 117 @StmXdDone1:
 118     push    esi
 119
 120   call ASM_PFX(SmmStmSetup)
 121
 122     mov     eax, ASM_PFX(gStmXdSupported)
 123     mov     al, [eax]
 124     cmp     al, 0
 125     jz      .71
 126     pop     edx                       ; get saved MSR_IA32_MISC_ENABLE[63-32]
 127     test    edx, BIT2
 128     jz      .71
 129     mov     ecx, MSR_IA32_MISC_ENABLE
 130     rdmsr
 131     or      dx, BIT2                  ; set XD Disable bit if it was set before entering into SMM
 132     wrmsr
 133
 134 .71:
 135     StuffRsb32
 136     rsm
 137
 138 global  ASM_PFX(OnStmTeardown)
 139 ASM_PFX(OnStmTeardown):
 140 ;
 141 ; Check XD disable bit
 142 ;
 143     xor     esi, esi
 144     mov     eax, ASM_PFX(gStmXdSupported)
 145     mov     al, [eax]
 146     cmp     al, 0
 147     jz      @StmXdDone2
 148     mov     ecx, MSR_IA32_MISC_ENABLE
 149     rdmsr
 150     mov     esi, edx                   ; save MSR_IA32_MISC_ENABLE[63-32]
 151     test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]
 152     jz      .52
 153     and     dx, 0xFFFB                 ; clear XD Disable bit if it is set
 154     wrmsr
 155 .52:
 156     mov     ecx, MSR_EFER
 157     rdmsr
 158     or      ax, MSR_EFER_XD             ; enable NXE
 159     wrmsr
 160 @StmXdDone2:
 161     push    esi
 162
 163   call ASM_PFX(SmmStmTeardown)
 164
 165     mov     eax, ASM_PFX(gStmXdSupported)
 166     mov     al, [eax]
 167     cmp     al, 0
 168     jz      .72
 169     pop     edx                       ; get saved MSR_IA32_MISC_ENABLE[63-32]
 170     test    edx, BIT2
 171     jz      .72
 172     mov     ecx, MSR_IA32_MISC_ENABLE
 173     rdmsr
 174     or      dx, BIT2                  ; set XD Disable bit if it was set before entering into SMM
 175     wrmsr
 176
 177 .72:
 178     StuffRsb32
 179     rsm