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1 /** @file
2 SMM STM support functions
3
4 Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
6
7 **/
8
9 #include <PiMm.h>
10 #include <Library/DebugLib.h>
11
12 #include "SmmStm.h"
13
14 ///
15 /// Page Table Entry
16 ///
17 #define IA32_PG_P BIT0
18 #define IA32_PG_RW BIT1
19 #define IA32_PG_PS BIT7
20
21 /**
22
23 Create 4G page table for STM.
24 4M Non-PAE page table in IA32 version.
25
26 @param PageTableBase The page table base in MSEG
27
28 **/
29 VOID
30 StmGen4GPageTable (
31 IN UINTN PageTableBase
32 )
33 {
34 UINTN Index;
35 UINT32 *Pte;
36 UINT32 Address;
37
38 Pte = (UINT32 *)(UINTN)PageTableBase;
39
40 Address = 0;
41 for (Index = 0; Index < SIZE_4KB / sizeof (*Pte); Index++) {
42 *Pte = Address | IA32_PG_PS | IA32_PG_RW | IA32_PG_P;
43 Pte++;
44 Address += SIZE_4MB;
45 }
46 }
47
48 /**
49 This is SMM exception handle.
50 Consumed by STM when exception happen.
51
52 @param Context STM protection exception stack frame
53
54 @return the EBX value for STM reference.
55 EBX = 0: resume SMM guest using register state found on exception stack.
56 EBX = 1 to 0x0F: EBX contains a BIOS error code which the STM must record in the
57 TXT.ERRORCODE register and subsequently reset the system via
58 TXT.CMD.SYS_RESET. The value of the TXT.ERRORCODE register is calculated as
59 follows: TXT.ERRORCODE = (EBX & 0x0F) | STM_CRASH_BIOS_PANIC
60 EBX = 0x10 to 0xFFFFFFFF - reserved, do not use.
61
62 **/
63 UINT32
64 EFIAPI
65 SmmStmExceptionHandler (
66 IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context
67 )
68 {
69 // TBD - SmmStmExceptionHandler, record information
70 DEBUG ((DEBUG_ERROR, "SmmStmExceptionHandler ...\n"));
71 //
72 // Skip this instruction and continue;
73 //
74 Context.Ia32StackFrame->Rip += Context.Ia32StackFrame->VmcsExitInstructionLength;
75
76 return 0;
77 }