UefiCpuPkg/SmmCpuFeatureLib: Add more CPU ID for SmmFeatureControl.
[mirror_edk2.git] / UefiCpuPkg / Library / SmmCpuFeaturesLib / SmmCpuFeaturesLib.c
1 /** @file
2 The CPU specific programming for PiSmmCpuDxeSmm module.
3
4 Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include <PiSmm.h>
16 #include <Library/SmmCpuFeaturesLib.h>
17 #include <Library/BaseLib.h>
18 #include <Library/MtrrLib.h>
19 #include <Library/PcdLib.h>
20 #include <Library/MemoryAllocationLib.h>
21 #include <Library/DebugLib.h>
22 #include <Register/Cpuid.h>
23 #include <Register/SmramSaveStateMap.h>
24
25 //
26 // Machine Specific Registers (MSRs)
27 //
28 #define SMM_FEATURES_LIB_IA32_MTRR_CAP 0x0FE
29 #define SMM_FEATURES_LIB_IA32_FEATURE_CONTROL 0x03A
30 #define SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE 0x1F2
31 #define SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK 0x1F3
32 #define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE 0x0A0
33 #define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK 0x0A1
34 #define EFI_MSR_SMRR_MASK 0xFFFFF000
35 #define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11
36 #define SMM_FEATURES_LIB_SMM_FEATURE_CONTROL 0x4E0
37
38 //
39 // MSRs required for configuration of SMM Code Access Check
40 //
41 #define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D
42 #define SMM_CODE_ACCESS_CHK_BIT BIT58
43
44 /**
45 Internal worker function that is called to complete CPU initialization at the
46 end of SmmCpuFeaturesInitializeProcessor().
47
48 **/
49 VOID
50 FinishSmmCpuFeaturesInitializeProcessor (
51 VOID
52 );
53
54 //
55 // Set default value to assume SMRR is not supported
56 //
57 BOOLEAN mSmrrSupported = FALSE;
58
59 //
60 // Set default value to assume MSR_SMM_FEATURE_CONTROL is not supported
61 //
62 BOOLEAN mSmmFeatureControlSupported = FALSE;
63
64 //
65 // Set default value to assume IA-32 Architectural MSRs are used
66 //
67 UINT32 mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE;
68 UINT32 mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK;
69
70 //
71 // Set default value to assume MTRRs need to be configured on each SMI
72 //
73 BOOLEAN mNeedConfigureMtrrs = TRUE;
74
75 //
76 // Array for state of SMRR enable on all CPUs
77 //
78 BOOLEAN *mSmrrEnabled;
79
80 /**
81 The constructor function
82
83 @param[in] ImageHandle The firmware allocated handle for the EFI image.
84 @param[in] SystemTable A pointer to the EFI System Table.
85
86 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
87
88 **/
89 EFI_STATUS
90 EFIAPI
91 SmmCpuFeaturesLibConstructor (
92 IN EFI_HANDLE ImageHandle,
93 IN EFI_SYSTEM_TABLE *SystemTable
94 )
95 {
96 UINT32 RegEax;
97 UINT32 RegEdx;
98 UINTN FamilyId;
99 UINTN ModelId;
100
101 //
102 // Retrieve CPU Family and Model
103 //
104 AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);
105 FamilyId = (RegEax >> 8) & 0xf;
106 ModelId = (RegEax >> 4) & 0xf;
107 if (FamilyId == 0x06 || FamilyId == 0x0f) {
108 ModelId = ModelId | ((RegEax >> 12) & 0xf0);
109 }
110
111 //
112 // Check CPUID(CPUID_VERSION_INFO).EDX[12] for MTRR capability
113 //
114 if ((RegEdx & BIT12) != 0) {
115 //
116 // Check MTRR_CAP MSR bit 11 for SMRR support
117 //
118 if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MTRR_CAP) & BIT11) != 0) {
119 mSmrrSupported = TRUE;
120 }
121 }
122
123 //
124 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
125 // Volume 3C, Section 35.3 MSRs in the Intel(R) Atom(TM) Processor Family
126 //
127 // If CPU Family/Model is 06_1CH, 06_26H, 06_27H, 06_35H or 06_36H, then
128 // SMRR Physical Base and SMM Physical Mask MSRs are not available.
129 //
130 if (FamilyId == 0x06) {
131 if (ModelId == 0x1C || ModelId == 0x26 || ModelId == 0x27 || ModelId == 0x35 || ModelId == 0x36) {
132 mSmrrSupported = FALSE;
133 }
134 }
135
136 //
137 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
138 // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family
139 //
140 // If CPU Family/Model is 06_0F or 06_17, then use Intel(R) Core(TM) 2
141 // Processor Family MSRs
142 //
143 if (FamilyId == 0x06) {
144 if (ModelId == 0x17 || ModelId == 0x0f) {
145 mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE;
146 mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK;
147 }
148 }
149
150 //
151 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
152 // Volume 3C, Section 34.4.2 SMRAM Caching
153 // An IA-32 processor does not automatically write back and invalidate its
154 // caches before entering SMM or before exiting SMM. Because of this behavior,
155 // care must be taken in the placement of the SMRAM in system memory and in
156 // the caching of the SMRAM to prevent cache incoherence when switching back
157 // and forth between SMM and protected mode operation.
158 //
159 // An IA-32 processor is a processor that does not support the Intel 64
160 // Architecture. Support for the Intel 64 Architecture can be detected from
161 // CPUID(CPUID_EXTENDED_CPU_SIG).EDX[29]
162 //
163 // If an IA-32 processor is detected, then set mNeedConfigureMtrrs to TRUE,
164 // so caches are flushed on SMI entry and SMI exit, the interrupted code
165 // MTRRs are saved/restored, and MTRRs for SMM are loaded.
166 //
167 AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
168 if (RegEax >= CPUID_EXTENDED_CPU_SIG) {
169 AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);
170 if ((RegEdx & BIT29) != 0) {
171 mNeedConfigureMtrrs = FALSE;
172 }
173 }
174
175 //
176 // Allocate array for state of SMRR enable on all CPUs
177 //
178 mSmrrEnabled = (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) * PcdGet32 (PcdCpuMaxLogicalProcessorNumber));
179 ASSERT (mSmrrEnabled != NULL);
180
181 return EFI_SUCCESS;
182 }
183
184 /**
185 Called during the very first SMI into System Management Mode to initialize
186 CPU features, including SMBASE, for the currently executing CPU. Since this
187 is the first SMI, the SMRAM Save State Map is at the default address of
188 SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing
189 CPU is specified by CpuIndex and CpuIndex can be used to access information
190 about the currently executing CPU in the ProcessorInfo array and the
191 HotPlugCpuData data structure.
192
193 @param[in] CpuIndex The index of the CPU to initialize. The value
194 must be between 0 and the NumberOfCpus field in
195 the System Management System Table (SMST).
196 @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that
197 was elected as monarch during System Management
198 Mode initialization.
199 FALSE if the CpuIndex is not the index of the CPU
200 that was elected as monarch during System
201 Management Mode initialization.
202 @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION
203 structures. ProcessorInfo[CpuIndex] contains the
204 information for the currently executing CPU.
205 @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that
206 contains the ApidId and SmBase arrays.
207 **/
208 VOID
209 EFIAPI
210 SmmCpuFeaturesInitializeProcessor (
211 IN UINTN CpuIndex,
212 IN BOOLEAN IsMonarch,
213 IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,
214 IN CPU_HOT_PLUG_DATA *CpuHotPlugData
215 )
216 {
217 SMRAM_SAVE_STATE_MAP *CpuState;
218 UINT64 FeatureControl;
219 UINT32 RegEax;
220 UINT32 RegEdx;
221 UINTN FamilyId;
222 UINTN ModelId;
223
224 //
225 // Configure SMBASE.
226 //
227 CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
228 CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
229
230 //
231 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
232 // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family
233 //
234 // If Intel(R) Core(TM) Core(TM) 2 Processor Family MSRs are being used, then
235 // make sure SMRR Enable(BIT3) of MSR_FEATURE_CONTROL MSR(0x3A) is set before
236 // accessing SMRR base/mask MSRs. If Lock(BIT0) of MSR_FEATURE_CONTROL MSR(0x3A)
237 // is set, then the MSR is locked and can not be modified.
238 //
239 if (mSmrrSupported && mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE) {
240 FeatureControl = AsmReadMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL);
241 if ((FeatureControl & BIT3) == 0) {
242 if ((FeatureControl & BIT0) == 0) {
243 AsmWriteMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL, FeatureControl | BIT3);
244 } else {
245 mSmrrSupported = FALSE;
246 }
247 }
248 }
249
250 //
251 // If SMRR is supported, then program SMRR base/mask MSRs.
252 // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first normal SMI.
253 // The code that initializes SMM environment is running in normal mode
254 // from SMRAM region. If SMRR is enabled here, then the SMRAM region
255 // is protected and the normal mode code execution will fail.
256 //
257 if (mSmrrSupported) {
258 //
259 // SMRR size cannot be less than 4-KBytes
260 // SMRR size must be of length 2^n
261 // SMRR base alignment cannot be less than SMRR length
262 //
263 if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||
264 (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||
265 ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase)) {
266 //
267 // Print message and halt if CPU is Monarch
268 //
269 if (IsMonarch) {
270 DEBUG ((DEBUG_ERROR, "SMM Base/Size does not meet alignment/size requirement!\n"));
271 CpuDeadLoop ();
272 }
273 } else {
274 AsmWriteMsr64 (mSmrrPhysBaseMsr, CpuHotPlugData->SmrrBase | MTRR_CACHE_WRITE_BACK);
275 AsmWriteMsr64 (mSmrrPhysMaskMsr, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK));
276 mSmrrEnabled[CpuIndex] = FALSE;
277 }
278 }
279
280 //
281 // Retrieve CPU Family and Model
282 //
283 AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);
284 FamilyId = (RegEax >> 8) & 0xf;
285 ModelId = (RegEax >> 4) & 0xf;
286 if (FamilyId == 0x06 || FamilyId == 0x0f) {
287 ModelId = ModelId | ((RegEax >> 12) & 0xf0);
288 }
289
290 //
291 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
292 // Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM)
293 // Processor Family.
294 //
295 // If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generation
296 // Intel(R) Core(TM) Processor Family MSRs.
297 //
298 if (FamilyId == 0x06) {
299 if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46 ||
300 ModelId == 0x3D || ModelId == 0x47 || ModelId == 0x4E || ModelId == 0x4F ||
301 ModelId == 0x3F || ModelId == 0x56 || ModelId == 0x57 || ModelId == 0x5C) {
302 //
303 // Check to see if the CPU supports the SMM Code Access Check feature
304 // Do not access this MSR unless the CPU supports the SmmRegFeatureControl
305 //
306 if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) != 0) {
307 mSmmFeatureControlSupported = TRUE;
308 }
309 }
310 }
311
312 //
313 // Call internal worker function that completes the CPU initialization
314 //
315 FinishSmmCpuFeaturesInitializeProcessor ();
316 }
317
318 /**
319 This function updates the SMRAM save state on the currently executing CPU
320 to resume execution at a specific address after an RSM instruction. This
321 function must evaluate the SMRAM save state to determine the execution mode
322 the RSM instruction resumes and update the resume execution address with
323 either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart
324 flag in the SMRAM save state must always be cleared. This function returns
325 the value of the instruction pointer from the SMRAM save state that was
326 replaced. If this function returns 0, then the SMRAM save state was not
327 modified.
328
329 This function is called during the very first SMI on each CPU after
330 SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
331 to signal that the SMBASE of each CPU has been updated before the default
332 SMBASE address is used for the first SMI to the next CPU.
333
334 @param[in] CpuIndex The index of the CPU to hook. The value
335 must be between 0 and the NumberOfCpus
336 field in the System Management System Table
337 (SMST).
338 @param[in] CpuState Pointer to SMRAM Save State Map for the
339 currently executing CPU.
340 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
341 32-bit execution mode from 64-bit SMM.
342 @param[in] NewInstructionPointer Instruction pointer to use if resuming to
343 same execution mode as SMM.
344
345 @retval 0 This function did modify the SMRAM save state.
346 @retval > 0 The original instruction pointer value from the SMRAM save state
347 before it was replaced.
348 **/
349 UINT64
350 EFIAPI
351 SmmCpuFeaturesHookReturnFromSmm (
352 IN UINTN CpuIndex,
353 IN SMRAM_SAVE_STATE_MAP *CpuState,
354 IN UINT64 NewInstructionPointer32,
355 IN UINT64 NewInstructionPointer
356 )
357 {
358 return 0;
359 }
360
361 /**
362 Hook point in normal execution mode that allows the one CPU that was elected
363 as monarch during System Management Mode initialization to perform additional
364 initialization actions immediately after all of the CPUs have processed their
365 first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE
366 into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().
367 **/
368 VOID
369 EFIAPI
370 SmmCpuFeaturesSmmRelocationComplete (
371 VOID
372 )
373 {
374 }
375
376 /**
377 Determines if MTRR registers must be configured to set SMRAM cache-ability
378 when executing in System Management Mode.
379
380 @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.
381 @retval FALSE MTRR registers do not need to be configured to set SMRAM
382 cache-ability.
383 **/
384 BOOLEAN
385 EFIAPI
386 SmmCpuFeaturesNeedConfigureMtrrs (
387 VOID
388 )
389 {
390 return mNeedConfigureMtrrs;
391 }
392
393 /**
394 Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
395 returns TRUE.
396 **/
397 VOID
398 EFIAPI
399 SmmCpuFeaturesDisableSmrr (
400 VOID
401 )
402 {
403 if (mSmrrSupported && mNeedConfigureMtrrs) {
404 AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64(mSmrrPhysMaskMsr) & ~EFI_MSR_SMRR_PHYS_MASK_VALID);
405 }
406 }
407
408 /**
409 Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
410 returns TRUE.
411 **/
412 VOID
413 EFIAPI
414 SmmCpuFeaturesReenableSmrr (
415 VOID
416 )
417 {
418 if (mSmrrSupported && mNeedConfigureMtrrs) {
419 AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64(mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);
420 }
421 }
422
423 /**
424 Processor specific hook point each time a CPU enters System Management Mode.
425
426 @param[in] CpuIndex The index of the CPU that has entered SMM. The value
427 must be between 0 and the NumberOfCpus field in the
428 System Management System Table (SMST).
429 **/
430 VOID
431 EFIAPI
432 SmmCpuFeaturesRendezvousEntry (
433 IN UINTN CpuIndex
434 )
435 {
436 //
437 // If SMRR is supported and this is the first normal SMI, then enable SMRR
438 //
439 if (mSmrrSupported && !mSmrrEnabled[CpuIndex]) {
440 AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);
441 mSmrrEnabled[CpuIndex] = TRUE;
442 }
443 }
444
445 /**
446 Processor specific hook point each time a CPU exits System Management Mode.
447
448 @param[in] CpuIndex The index of the CPU that is exiting SMM. The value must
449 be between 0 and the NumberOfCpus field in the System
450 Management System Table (SMST).
451 **/
452 VOID
453 EFIAPI
454 SmmCpuFeaturesRendezvousExit (
455 IN UINTN CpuIndex
456 )
457 {
458 }
459
460 /**
461 Check to see if an SMM register is supported by a specified CPU.
462
463 @param[in] CpuIndex The index of the CPU to check for SMM register support.
464 The value must be between 0 and the NumberOfCpus field
465 in the System Management System Table (SMST).
466 @param[in] RegName Identifies the SMM register to check for support.
467
468 @retval TRUE The SMM register specified by RegName is supported by the CPU
469 specified by CpuIndex.
470 @retval FALSE The SMM register specified by RegName is not supported by the
471 CPU specified by CpuIndex.
472 **/
473 BOOLEAN
474 EFIAPI
475 SmmCpuFeaturesIsSmmRegisterSupported (
476 IN UINTN CpuIndex,
477 IN SMM_REG_NAME RegName
478 )
479 {
480 if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
481 return TRUE;
482 }
483 return FALSE;
484 }
485
486 /**
487 Returns the current value of the SMM register for the specified CPU.
488 If the SMM register is not supported, then 0 is returned.
489
490 @param[in] CpuIndex The index of the CPU to read the SMM register. The
491 value must be between 0 and the NumberOfCpus field in
492 the System Management System Table (SMST).
493 @param[in] RegName Identifies the SMM register to read.
494
495 @return The value of the SMM register specified by RegName from the CPU
496 specified by CpuIndex.
497 **/
498 UINT64
499 EFIAPI
500 SmmCpuFeaturesGetSmmRegister (
501 IN UINTN CpuIndex,
502 IN SMM_REG_NAME RegName
503 )
504 {
505 if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
506 return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL);
507 }
508 return 0;
509 }
510
511 /**
512 Sets the value of an SMM register on a specified CPU.
513 If the SMM register is not supported, then no action is performed.
514
515 @param[in] CpuIndex The index of the CPU to write the SMM register. The
516 value must be between 0 and the NumberOfCpus field in
517 the System Management System Table (SMST).
518 @param[in] RegName Identifies the SMM register to write.
519 registers are read-only.
520 @param[in] Value The value to write to the SMM register.
521 **/
522 VOID
523 EFIAPI
524 SmmCpuFeaturesSetSmmRegister (
525 IN UINTN CpuIndex,
526 IN SMM_REG_NAME RegName,
527 IN UINT64 Value
528 )
529 {
530 if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
531 AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value);
532 }
533 }
534
535 /**
536 Read an SMM Save State register on the target processor. If this function
537 returns EFI_UNSUPPORTED, then the caller is responsible for reading the
538 SMM Save Sate register.
539
540 @param[in] CpuIndex The index of the CPU to read the SMM Save State. The
541 value must be between 0 and the NumberOfCpus field in
542 the System Management System Table (SMST).
543 @param[in] Register The SMM Save State register to read.
544 @param[in] Width The number of bytes to read from the CPU save state.
545 @param[out] Buffer Upon return, this holds the CPU register value read
546 from the save state.
547
548 @retval EFI_SUCCESS The register was read from Save State.
549 @retval EFI_INVALID_PARAMTER Buffer is NULL.
550 @retval EFI_UNSUPPORTED This function does not support reading Register.
551
552 **/
553 EFI_STATUS
554 EFIAPI
555 SmmCpuFeaturesReadSaveStateRegister (
556 IN UINTN CpuIndex,
557 IN EFI_SMM_SAVE_STATE_REGISTER Register,
558 IN UINTN Width,
559 OUT VOID *Buffer
560 )
561 {
562 return EFI_UNSUPPORTED;
563 }
564
565 /**
566 Writes an SMM Save State register on the target processor. If this function
567 returns EFI_UNSUPPORTED, then the caller is responsible for writing the
568 SMM Save Sate register.
569
570 @param[in] CpuIndex The index of the CPU to write the SMM Save State. The
571 value must be between 0 and the NumberOfCpus field in
572 the System Management System Table (SMST).
573 @param[in] Register The SMM Save State register to write.
574 @param[in] Width The number of bytes to write to the CPU save state.
575 @param[in] Buffer Upon entry, this holds the new CPU register value.
576
577 @retval EFI_SUCCESS The register was written to Save State.
578 @retval EFI_INVALID_PARAMTER Buffer is NULL.
579 @retval EFI_UNSUPPORTED This function does not support writing Register.
580 **/
581 EFI_STATUS
582 EFIAPI
583 SmmCpuFeaturesWriteSaveStateRegister (
584 IN UINTN CpuIndex,
585 IN EFI_SMM_SAVE_STATE_REGISTER Register,
586 IN UINTN Width,
587 IN CONST VOID *Buffer
588 )
589 {
590 return EFI_UNSUPPORTED;
591 }
592
593 /**
594 This function is hook point called after the gEfiSmmReadyToLockProtocolGuid
595 notification is completely processed.
596 **/
597 VOID
598 EFIAPI
599 SmmCpuFeaturesCompleteSmmReadyToLock (
600 VOID
601 )
602 {
603 }
604
605 /**
606 This API provides a method for a CPU to allocate a specific region for storing page tables.
607
608 This API can be called more once to allocate memory for page tables.
609
610 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
611 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
612 is returned. If there is not enough memory remaining to satisfy the request, then NULL is
613 returned.
614
615 This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.
616
617 @param Pages The number of 4 KB pages to allocate.
618
619 @return A pointer to the allocated buffer for page tables.
620 @retval NULL Fail to allocate a specific region for storing page tables,
621 Or there is no preference on where the page tables are allocated in SMRAM.
622
623 **/
624 VOID *
625 EFIAPI
626 SmmCpuFeaturesAllocatePageTableMemory (
627 IN UINTN Pages
628 )
629 {
630 return NULL;
631 }
632