2 The CPU specific programming for PiSmmCpuDxeSmm module.
4 Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include <Library/SmmCpuFeaturesLib.h>
17 #include <Library/BaseLib.h>
18 #include <Library/MtrrLib.h>
19 #include <Library/PcdLib.h>
20 #include <Library/MemoryAllocationLib.h>
21 #include <Library/DebugLib.h>
22 #include <Register/Cpuid.h>
23 #include <Register/SmramSaveStateMap.h>
26 // Machine Specific Registers (MSRs)
28 #define SMM_FEATURES_LIB_IA32_MTRR_CAP 0x0FE
29 #define SMM_FEATURES_LIB_IA32_FEATURE_CONTROL 0x03A
30 #define SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE 0x1F2
31 #define SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK 0x1F3
32 #define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE 0x0A0
33 #define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK 0x0A1
34 #define EFI_MSR_SMRR_MASK 0xFFFFF000
35 #define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11
38 // Set default value to assume SMRR is not supported
40 BOOLEAN mSmrrSupported
= FALSE
;
43 // Set default value to assume IA-32 Architectural MSRs are used
45 UINT32 mSmrrPhysBaseMsr
= SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE
;
46 UINT32 mSmrrPhysMaskMsr
= SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK
;
49 // Set default value to assume MTRRs need to be configured on each SMI
51 BOOLEAN mNeedConfigureMtrrs
= TRUE
;
54 // Array for state of SMRR enable on all CPUs
56 BOOLEAN
*mSmrrEnabled
;
59 The constructor function
61 @param[in] ImageHandle The firmware allocated handle for the EFI image.
62 @param[in] SystemTable A pointer to the EFI System Table.
64 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
69 SmmCpuFeaturesLibConstructor (
70 IN EFI_HANDLE ImageHandle
,
71 IN EFI_SYSTEM_TABLE
*SystemTable
80 // Retrieve CPU Family and Model
82 AsmCpuid (CPUID_VERSION_INFO
, &RegEax
, NULL
, NULL
, &RegEdx
);
83 FamilyId
= (RegEax
>> 8) & 0xf;
84 ModelId
= (RegEax
>> 4) & 0xf;
85 if (FamilyId
== 0x06 || FamilyId
== 0x0f) {
86 ModelId
= ModelId
| ((RegEax
>> 12) & 0xf0);
90 // Check CPUID(CPUID_VERSION_INFO).EDX[12] for MTRR capability
92 if ((RegEdx
& BIT12
) != 0) {
94 // Check MTRR_CAP MSR bit 11 for SMRR support
96 if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MTRR_CAP
) & BIT11
) != 0) {
97 mSmrrSupported
= TRUE
;
102 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
103 // Volume 3C, Section 35.3 MSRs in the Intel(R) Atom(TM) Processor Family
105 // If CPU Family/Model is 06_1CH, 06_26H, 06_27H, 06_35H or 06_36H, then
106 // SMRR Physical Base and SMM Physical Mask MSRs are not available.
108 if (FamilyId
== 0x06) {
109 if (ModelId
== 0x1C || ModelId
== 0x26 || ModelId
== 0x27 || ModelId
== 0x35 || ModelId
== 0x36) {
110 mSmrrSupported
= FALSE
;
115 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
116 // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family
118 // If CPU Family/Model is 06_0F or 06_17, then use Intel(R) Core(TM) 2
119 // Processor Family MSRs
121 if (FamilyId
== 0x06) {
122 if (ModelId
== 0x17 || ModelId
== 0x0f) {
123 mSmrrPhysBaseMsr
= SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE
;
124 mSmrrPhysMaskMsr
= SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK
;
129 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
130 // Volume 3C, Section 34.4.2 SMRAM Caching
131 // An IA-32 processor does not automatically write back and invalidate its
132 // caches before entering SMM or before exiting SMM. Because of this behavior,
133 // care must be taken in the placement of the SMRAM in system memory and in
134 // the caching of the SMRAM to prevent cache incoherence when switching back
135 // and forth between SMM and protected mode operation.
137 // An IA-32 processor is a processor that does not support the Intel 64
138 // Architecture. Support for the Intel 64 Architecture can be detected from
139 // CPUID(CPUID_EXTENDED_CPU_SIG).EDX[29]
141 // If an IA-32 processor is detected, then set mNeedConfigureMtrrs to TRUE,
142 // so caches are flushed on SMI entry and SMI exit, the interrupted code
143 // MTRRs are saved/restored, and MTRRs for SMM are loaded.
145 AsmCpuid (CPUID_EXTENDED_FUNCTION
, &RegEax
, NULL
, NULL
, NULL
);
146 if (RegEax
>= CPUID_EXTENDED_CPU_SIG
) {
147 AsmCpuid (CPUID_EXTENDED_CPU_SIG
, NULL
, NULL
, NULL
, &RegEdx
);
148 if ((RegEdx
& BIT29
) != 0) {
149 mNeedConfigureMtrrs
= FALSE
;
154 // Allocate array for state of SMRR enable on all CPUs
156 mSmrrEnabled
= (BOOLEAN
*)AllocatePool (sizeof (BOOLEAN
) * PcdGet32 (PcdCpuMaxLogicalProcessorNumber
));
157 ASSERT (mSmrrEnabled
!= NULL
);
163 Called during the very first SMI into System Management Mode to initialize
164 CPU features, including SMBASE, for the currently executing CPU. Since this
165 is the first SMI, the SMRAM Save State Map is at the default address of
166 SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing
167 CPU is specified by CpuIndex and CpuIndex can be used to access information
168 about the currently executing CPU in the ProcessorInfo array and the
169 HotPlugCpuData data structure.
171 @param[in] CpuIndex The index of the CPU to initialize. The value
172 must be between 0 and the NumberOfCpus field in
173 the System Management System Table (SMST).
174 @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that
175 was elected as monarch during System Management
177 FALSE if the CpuIndex is not the index of the CPU
178 that was elected as monarch during System
179 Management Mode initialization.
180 @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION
181 structures. ProcessorInfo[CpuIndex] contains the
182 information for the currently executing CPU.
183 @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that
184 contains the ApidId and SmBase arrays.
188 SmmCpuFeaturesInitializeProcessor (
190 IN BOOLEAN IsMonarch
,
191 IN EFI_PROCESSOR_INFORMATION
*ProcessorInfo
,
192 IN CPU_HOT_PLUG_DATA
*CpuHotPlugData
195 SMRAM_SAVE_STATE_MAP
*CpuState
;
196 UINT64 FeatureControl
;
201 CpuState
= (SMRAM_SAVE_STATE_MAP
*)(UINTN
)(SMM_DEFAULT_SMBASE
+ SMRAM_SAVE_STATE_MAP_OFFSET
);
202 CpuState
->x86
.SMBASE
= (UINT32
)CpuHotPlugData
->SmBase
[CpuIndex
];
205 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
206 // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family
208 // If Intel(R) Core(TM) Core(TM) 2 Processor Family MSRs are being used, then
209 // make sure SMRR Enable(BIT3) of MSR_FEATURE_CONTROL MSR(0x3A) is set before
210 // accessing SMRR base/mask MSRs. If Lock(BIT0) of MSR_FEATURE_CONTROL MSR(0x3A)
211 // is set, then the MSR is locked and can not be modified.
213 if (mSmrrSupported
&& mSmrrPhysBaseMsr
== SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE
) {
214 FeatureControl
= AsmReadMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL
);
215 if ((FeatureControl
& BIT3
) == 0) {
216 if ((FeatureControl
& BIT0
) == 0) {
217 AsmWriteMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL
, FeatureControl
| BIT3
);
219 mSmrrSupported
= FALSE
;
225 // If SMRR is supported, then program SMRR base/mask MSRs.
226 // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first normal SMI.
227 // The code that initializes SMM environment is running in normal mode
228 // from SMRAM region. If SMRR is enabled here, then the SMRAM region
229 // is protected and the normal mode code execution will fail.
231 if (mSmrrSupported
) {
232 AsmWriteMsr64 (mSmrrPhysBaseMsr
, CpuHotPlugData
->SmrrBase
| MTRR_CACHE_WRITE_BACK
);
233 AsmWriteMsr64 (mSmrrPhysMaskMsr
, (~(CpuHotPlugData
->SmrrSize
- 1) & EFI_MSR_SMRR_MASK
));
234 mSmrrEnabled
[CpuIndex
] = FALSE
;
239 This function updates the SMRAM save state on the currently executing CPU
240 to resume execution at a specific address after an RSM instruction. This
241 function must evaluate the SMRAM save state to determine the execution mode
242 the RSM instruction resumes and update the resume execution address with
243 either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart
244 flag in the SMRAM save state must always be cleared. This function returns
245 the value of the instruction pointer from the SMRAM save state that was
246 replaced. If this function returns 0, then the SMRAM save state was not
249 This function is called during the very first SMI on each CPU after
250 SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
251 to signal that the SMBASE of each CPU has been updated before the default
252 SMBASE address is used for the first SMI to the next CPU.
254 @param[in] CpuIndex The index of the CPU to hook. The value
255 must be between 0 and the NumberOfCpus
256 field in the System Management System Table
258 @param[in] CpuState Pointer to SMRAM Save State Map for the
259 currently executing CPU.
260 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
261 32-bit execution mode from 64-bit SMM.
262 @param[in] NewInstructionPointer Instruction pointer to use if resuming to
263 same execution mode as SMM.
265 @retval 0 This function did modify the SMRAM save state.
266 @retval > 0 The original instruction pointer value from the SMRAM save state
267 before it was replaced.
271 SmmCpuFeaturesHookReturnFromSmm (
273 IN SMRAM_SAVE_STATE_MAP
*CpuState
,
274 IN UINT64 NewInstructionPointer32
,
275 IN UINT64 NewInstructionPointer
282 Hook point in normal execution mode that allows the one CPU that was elected
283 as monarch during System Management Mode initialization to perform additional
284 initialization actions immediately after all of the CPUs have processed their
285 first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE
286 into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().
290 SmmCpuFeaturesSmmRelocationComplete (
297 Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is
298 returned, then a custom SMI handler is not provided by this library,
299 and the default SMI handler must be used.
301 @retval 0 Use the default SMI handler.
302 @retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()
303 The caller is required to allocate enough SMRAM for each CPU to
304 support the size of the custom SMI handler.
308 SmmCpuFeaturesGetSmiHandlerSize (
316 Install a custom SMI handler for the CPU specified by CpuIndex. This function
317 is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater
318 than zero and is called by the CPU that was elected as monarch during System
319 Management Mode initialization.
321 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.
322 The value must be between 0 and the NumberOfCpus field
323 in the System Management System Table (SMST).
324 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
325 @param[in] SmiStack The stack to use when an SMI is processed by the
326 the CPU specified by CpuIndex.
327 @param[in] StackSize The size, in bytes, if the stack used when an SMI is
328 processed by the CPU specified by CpuIndex.
329 @param[in] GdtBase The base address of the GDT to use when an SMI is
330 processed by the CPU specified by CpuIndex.
331 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
332 processed by the CPU specified by CpuIndex.
333 @param[in] IdtBase The base address of the IDT to use when an SMI is
334 processed by the CPU specified by CpuIndex.
335 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
336 processed by the CPU specified by CpuIndex.
337 @param[in] Cr3 The base address of the page tables to use when an SMI
338 is processed by the CPU specified by CpuIndex.
342 SmmCpuFeaturesInstallSmiHandler (
357 Determines if MTRR registers must be configured to set SMRAM cache-ability
358 when executing in System Management Mode.
360 @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.
361 @retval FALSE MTRR registers do not need to be configured to set SMRAM
366 SmmCpuFeaturesNeedConfigureMtrrs (
370 return mNeedConfigureMtrrs
;
374 Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
379 SmmCpuFeaturesDisableSmrr (
383 if (mSmrrSupported
&& mNeedConfigureMtrrs
) {
384 AsmWriteMsr64 (mSmrrPhysMaskMsr
, AsmReadMsr64(mSmrrPhysMaskMsr
) & ~EFI_MSR_SMRR_PHYS_MASK_VALID
);
389 Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
394 SmmCpuFeaturesReenableSmrr (
398 if (mSmrrSupported
&& mNeedConfigureMtrrs
) {
399 AsmWriteMsr64 (mSmrrPhysMaskMsr
, AsmReadMsr64(mSmrrPhysMaskMsr
) | EFI_MSR_SMRR_PHYS_MASK_VALID
);
404 Processor specific hook point each time a CPU enters System Management Mode.
406 @param[in] CpuIndex The index of the CPU that has entered SMM. The value
407 must be between 0 and the NumberOfCpus field in the
408 System Management System Table (SMST).
412 SmmCpuFeaturesRendezvousEntry (
417 // If SMRR is supported and this is the first normal SMI, then enable SMRR
419 if (mSmrrSupported
&& !mSmrrEnabled
[CpuIndex
]) {
420 AsmWriteMsr64 (mSmrrPhysMaskMsr
, AsmReadMsr64 (mSmrrPhysMaskMsr
) | EFI_MSR_SMRR_PHYS_MASK_VALID
);
421 mSmrrEnabled
[CpuIndex
] = TRUE
;
426 Processor specific hook point each time a CPU exits System Management Mode.
428 @param[in] CpuIndex The index of the CPU that is exiting SMM. The value must
429 be between 0 and the NumberOfCpus field in the System
430 Management System Table (SMST).
434 SmmCpuFeaturesRendezvousExit (
441 Check to see if an SMM register is supported by a specified CPU.
443 @param[in] CpuIndex The index of the CPU to check for SMM register support.
444 The value must be between 0 and the NumberOfCpus field
445 in the System Management System Table (SMST).
446 @param[in] RegName Identifies the SMM register to check for support.
448 @retval TRUE The SMM register specified by RegName is supported by the CPU
449 specified by CpuIndex.
450 @retval FALSE The SMM register specified by RegName is not supported by the
451 CPU specified by CpuIndex.
455 SmmCpuFeaturesIsSmmRegisterSupported (
457 IN SMM_REG_NAME RegName
464 Returns the current value of the SMM register for the specified CPU.
465 If the SMM register is not supported, then 0 is returned.
467 @param[in] CpuIndex The index of the CPU to read the SMM register. The
468 value must be between 0 and the NumberOfCpus field in
469 the System Management System Table (SMST).
470 @param[in] RegName Identifies the SMM register to read.
472 @return The value of the SMM register specified by RegName from the CPU
473 specified by CpuIndex.
477 SmmCpuFeaturesGetSmmRegister (
479 IN SMM_REG_NAME RegName
486 Sets the value of an SMM register on a specified CPU.
487 If the SMM register is not supported, then no action is performed.
489 @param[in] CpuIndex The index of the CPU to write the SMM register. The
490 value must be between 0 and the NumberOfCpus field in
491 the System Management System Table (SMST).
492 @param[in] RegName Identifies the SMM register to write.
493 registers are read-only.
494 @param[in] Value The value to write to the SMM register.
498 SmmCpuFeaturesSetSmmRegister (
500 IN SMM_REG_NAME RegName
,
507 Read an SMM Save State register on the target processor. If this function
508 returns EFI_UNSUPPORTED, then the caller is responsible for reading the
509 SMM Save Sate register.
511 @param[in] CpuIndex The index of the CPU to read the SMM Save State. The
512 value must be between 0 and the NumberOfCpus field in
513 the System Management System Table (SMST).
514 @param[in] Register The SMM Save State register to read.
515 @param[in] Width The number of bytes to read from the CPU save state.
516 @param[out] Buffer Upon return, this holds the CPU register value read
519 @retval EFI_SUCCESS The register was read from Save State.
520 @retval EFI_INVALID_PARAMTER Buffer is NULL.
521 @retval EFI_UNSUPPORTED This function does not support reading Register.
526 SmmCpuFeaturesReadSaveStateRegister (
528 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
533 return EFI_UNSUPPORTED
;
537 Writes an SMM Save State register on the target processor. If this function
538 returns EFI_UNSUPPORTED, then the caller is responsible for writing the
539 SMM Save Sate register.
541 @param[in] CpuIndex The index of the CPU to write the SMM Save State. The
542 value must be between 0 and the NumberOfCpus field in
543 the System Management System Table (SMST).
544 @param[in] Register The SMM Save State register to write.
545 @param[in] Width The number of bytes to write to the CPU save state.
546 @param[in] Buffer Upon entry, this holds the new CPU register value.
548 @retval EFI_SUCCESS The register was written to Save State.
549 @retval EFI_INVALID_PARAMTER Buffer is NULL.
550 @retval EFI_UNSUPPORTED This function does not support writing Register.
554 SmmCpuFeaturesWriteSaveStateRegister (
556 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
558 IN CONST VOID
*Buffer
561 return EFI_UNSUPPORTED
;