UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm

   1 ;------------------------------------------------------------------------------ ;
   2 ; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
   3 ; This program and the accompanying materials
   4 ; are licensed and made available under the terms and conditions of the BSD License
   5 ; which accompanies this distribution.  The full text of the license may be found at
   6 ; http://opensource.org/licenses/bsd-license.php.
   7 ;
   8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
   9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  10 ;
  11 ; Module Name:
  12 ;
  13 ;   SmiException.nasm
  14 ;
  15 ; Abstract:
  16 ;
  17 ;   Exception handlers used in SM mode
  18 ;
  19 ;-------------------------------------------------------------------------------
  20
  21 %include "StuffRsbNasm.inc"
  22
  23 global  ASM_PFX(gcStmPsd)
  24
  25 extern  ASM_PFX(SmmStmExceptionHandler)
  26 extern  ASM_PFX(SmmStmSetup)
  27 extern  ASM_PFX(SmmStmTeardown)
  28 extern  ASM_PFX(gStmXdSupported)
  29 extern  ASM_PFX(gStmSmiHandlerIdtr)
  30
  31 %define MSR_IA32_MISC_ENABLE 0x1A0
  32 %define MSR_EFER      0xc0000080
  33 %define MSR_EFER_XD   0x800
  34
  35 CODE_SEL          equ 0x38
  36 DATA_SEL          equ 0x20
  37 TR_SEL            equ 0x40
  38
  39     SECTION .data
  40
  41 ;
  42 ; This structure serves as a template for all processors.
  43 ;
  44 ASM_PFX(gcStmPsd):
  45             DB      'TXTPSSIG'
  46             DW      PSD_SIZE
  47             DW      1              ; Version
  48             DD      0              ; LocalApicId
  49             DB      0x0F           ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr
  50             DB      0              ; BIOS to STM
  51             DB      0              ; STM to BIOS
  52             DB      0
  53             DW      CODE_SEL
  54             DW      DATA_SEL
  55             DW      DATA_SEL
  56             DW      DATA_SEL
  57             DW      TR_SEL
  58             DW      0
  59             DQ      0              ; SmmCr3
  60             DQ      ASM_PFX(OnStmSetup)
  61             DQ      ASM_PFX(OnStmTeardown)
  62             DQ      0              ; SmmSmiHandlerRip - SMM guest entrypoint
  63             DQ      0              ; SmmSmiHandlerRsp
  64             DQ      0
  65             DD      0
  66             DD      0x80010100     ; RequiredStmSmmRevId
  67             DQ      ASM_PFX(OnException)
  68             DQ      0              ; ExceptionStack
  69             DW      DATA_SEL
  70             DW      0x01F          ; ExceptionFilter
  71             DD      0
  72             DQ      0
  73             DQ      0              ; BiosHwResourceRequirementsPtr
  74             DQ      0              ; AcpiRsdp
  75             DB      0              ; PhysicalAddressBits
  76 PSD_SIZE  equ $ -   ASM_PFX(gcStmPsd)
  77
  78     DEFAULT REL
  79     SECTION .text
  80 ;------------------------------------------------------------------------------
  81 ; SMM Exception handlers
  82 ;------------------------------------------------------------------------------
  83 global ASM_PFX(OnException)
  84 ASM_PFX(OnException):
  85     mov  rcx, rsp
  86     add  rsp, -0x28
  87     call ASM_PFX(SmmStmExceptionHandler)
  88     add  rsp, 0x28
  89     mov  ebx, eax
  90     mov  eax, 4
  91     vmcall
  92     jmp $
  93
  94 global ASM_PFX(OnStmSetup)
  95 ASM_PFX(OnStmSetup):
  96 ;
  97 ; Check XD disable bit
  98 ;
  99     xor     r8, r8
 100     lea     rax, [ASM_PFX(gStmXdSupported)]
 101     mov     al, [rax]
 102     cmp     al, 0
 103     jz      @StmXdDone1
 104     mov     ecx, MSR_IA32_MISC_ENABLE
 105     rdmsr
 106     mov     r8, rdx                    ; save MSR_IA32_MISC_ENABLE[63-32]
 107     test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]
 108     jz      .01
 109     and     dx, 0xFFFB                 ; clear XD Disable bit if it is set
 110     wrmsr
 111 .01:
 112     mov     ecx, MSR_EFER
 113     rdmsr
 114     or      ax, MSR_EFER_XD            ; enable NXE
 115     wrmsr
 116 @StmXdDone1:
 117     push    r8
 118
 119   add  rsp, -0x20
 120   call ASM_PFX(SmmStmSetup)
 121   add  rsp, 0x20
 122
 123     lea     rax, [ASM_PFX(gStmXdSupported)]
 124     mov     al, [rax]
 125     cmp     al, 0
 126     jz      .11
 127     pop     rdx                       ; get saved MSR_IA32_MISC_ENABLE[63-32]
 128     test    edx, BIT2
 129     jz      .11
 130     mov     ecx, MSR_IA32_MISC_ENABLE
 131     rdmsr
 132     or      dx, BIT2                  ; set XD Disable bit if it was set before entering into SMM
 133     wrmsr
 134
 135 .11:
 136     StuffRsb64
 137     rsm
 138
 139 global ASM_PFX(OnStmTeardown)
 140 ASM_PFX(OnStmTeardown):
 141 ;
 142 ; Check XD disable bit
 143 ;
 144     xor     r8, r8
 145     lea     rax, [ASM_PFX(gStmXdSupported)]
 146     mov     al, [rax]
 147     cmp     al, 0
 148     jz      @StmXdDone2
 149     mov     ecx, MSR_IA32_MISC_ENABLE
 150     rdmsr
 151     mov     r8, rdx                    ; save MSR_IA32_MISC_ENABLE[63-32]
 152     test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]
 153     jz      .02
 154     and     dx, 0xFFFB                 ; clear XD Disable bit if it is set
 155     wrmsr
 156 .02:
 157     mov     ecx, MSR_EFER
 158     rdmsr
 159     or      ax, MSR_EFER_XD            ; enable NXE
 160     wrmsr
 161 @StmXdDone2:
 162     push    r8
 163
 164   add  rsp, -0x20
 165   call ASM_PFX(SmmStmTeardown)
 166   add  rsp, 0x20
 167
 168     lea     rax, [ASM_PFX(gStmXdSupported)]
 169     mov     al, [rax]
 170     cmp     al, 0
 171     jz      .12
 172     pop     rdx                       ; get saved MSR_IA32_MISC_ENABLE[63-32]
 173     test    edx, BIT2
 174     jz      .12
 175     mov     ecx, MSR_IA32_MISC_ENABLE
 176     rdmsr
 177     or      dx, BIT2                  ; set XD Disable bit if it was set before entering into SMM
 178     wrmsr
 179
 180 .12:
 181     StuffRsb64
 182     rsm