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UefiCpuPkg/PiSmmCpuDxeSmm: Combine CR read/write action.
[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / CpuS3.c
1 /** @file
2 Code for Processor S3 restoration
3
4 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
6
7 **/
8
9 #include "PiSmmCpuDxeSmm.h"
10
11 #pragma pack(1)
12 typedef struct {
13 UINTN Lock;
14 VOID *StackStart;
15 UINTN StackSize;
16 VOID *ApFunction;
17 IA32_DESCRIPTOR GdtrProfile;
18 IA32_DESCRIPTOR IdtrProfile;
19 UINT32 BufferStart;
20 UINT32 Cr3;
21 UINTN InitializeFloatingPointUnitsAddress;
22 } MP_CPU_EXCHANGE_INFO;
23 #pragma pack()
24
25 typedef struct {
26 UINT8 *RendezvousFunnelAddress;
27 UINTN PModeEntryOffset;
28 UINTN FlatJumpOffset;
29 UINTN Size;
30 UINTN LModeEntryOffset;
31 UINTN LongJumpOffset;
32 } MP_ASSEMBLY_ADDRESS_MAP;
33
34 //
35 // Flags used when program the register.
36 //
37 typedef struct {
38 volatile UINTN MemoryMappedLock; // Spinlock used to program mmio
39 volatile UINT32 *CoreSemaphoreCount; // Semaphore container used to program
40 // core level semaphore.
41 volatile UINT32 *PackageSemaphoreCount; // Semaphore container used to program
42 // package level semaphore.
43 } PROGRAM_CPU_REGISTER_FLAGS;
44
45 //
46 // Signal that SMM BASE relocation is complete.
47 //
48 volatile BOOLEAN mInitApsAfterSmmBaseReloc;
49
50 /**
51 Get starting address and size of the rendezvous entry for APs.
52 Information for fixing a jump instruction in the code is also returned.
53
54 @param AddressMap Output buffer for address map information.
55 **/
56 VOID *
57 EFIAPI
58 AsmGetAddressMap (
59 MP_ASSEMBLY_ADDRESS_MAP *AddressMap
60 );
61
62 #define LEGACY_REGION_SIZE (2 * 0x1000)
63 #define LEGACY_REGION_BASE (0xA0000 - LEGACY_REGION_SIZE)
64
65 PROGRAM_CPU_REGISTER_FLAGS mCpuFlags;
66 ACPI_CPU_DATA mAcpiCpuData;
67 volatile UINT32 mNumberToFinish;
68 MP_CPU_EXCHANGE_INFO *mExchangeInfo;
69 BOOLEAN mRestoreSmmConfigurationInS3 = FALSE;
70
71 //
72 // S3 boot flag
73 //
74 BOOLEAN mSmmS3Flag = FALSE;
75
76 //
77 // Pointer to structure used during S3 Resume
78 //
79 SMM_S3_RESUME_STATE *mSmmS3ResumeState = NULL;
80
81 BOOLEAN mAcpiS3Enable = TRUE;
82
83 UINT8 *mApHltLoopCode = NULL;
84 UINT8 mApHltLoopCodeTemplate[] = {
85 0x8B, 0x44, 0x24, 0x04, // mov eax, dword ptr [esp+4]
86 0xF0, 0xFF, 0x08, // lock dec dword ptr [eax]
87 0xFA, // cli
88 0xF4, // hlt
89 0xEB, 0xFC // jmp $-2
90 };
91
92 /**
93 Sync up the MTRR values for all processors.
94
95 @param MtrrTable Table holding fixed/variable MTRR values to be loaded.
96 **/
97 VOID
98 EFIAPI
99 LoadMtrrData (
100 EFI_PHYSICAL_ADDRESS MtrrTable
101 )
102 /*++
103
104 Routine Description:
105
106 Sync up the MTRR values for all processors.
107
108 Arguments:
109
110 Returns:
111 None
112
113 --*/
114 {
115 MTRR_SETTINGS *MtrrSettings;
116
117 MtrrSettings = (MTRR_SETTINGS *) (UINTN) MtrrTable;
118 MtrrSetAllMtrrs (MtrrSettings);
119 }
120
121 /**
122 Increment semaphore by 1.
123
124 @param Sem IN: 32-bit unsigned integer
125
126 **/
127 VOID
128 S3ReleaseSemaphore (
129 IN OUT volatile UINT32 *Sem
130 )
131 {
132 InterlockedIncrement (Sem);
133 }
134
135 /**
136 Decrement the semaphore by 1 if it is not zero.
137
138 Performs an atomic decrement operation for semaphore.
139 The compare exchange operation must be performed using
140 MP safe mechanisms.
141
142 @param Sem IN: 32-bit unsigned integer
143
144 **/
145 VOID
146 S3WaitForSemaphore (
147 IN OUT volatile UINT32 *Sem
148 )
149 {
150 UINT32 Value;
151
152 do {
153 Value = *Sem;
154 } while (Value == 0 ||
155 InterlockedCompareExchange32 (
156 Sem,
157 Value,
158 Value - 1
159 ) != Value);
160 }
161
162 /**
163 Read / write CR value.
164
165 @param[in] CrIndex The CR index which need to read/write.
166 @param[in] Read Read or write. TRUE is read.
167 @param[in,out] CrValue CR value.
168
169 @retval EFI_SUCCESS means read/write success, else return EFI_UNSUPPORTED.
170 **/
171 UINTN
172 ReadWriteCr (
173 IN UINT32 CrIndex,
174 IN BOOLEAN Read,
175 IN OUT UINTN *CrValue
176 )
177 {
178 switch (CrIndex) {
179 case 0:
180 if (Read) {
181 *CrValue = AsmReadCr0 ();
182 } else {
183 AsmWriteCr0 (*CrValue);
184 }
185 break;
186 case 2:
187 if (Read) {
188 *CrValue = AsmReadCr2 ();
189 } else {
190 AsmWriteCr2 (*CrValue);
191 }
192 break;
193 case 3:
194 if (Read) {
195 *CrValue = AsmReadCr3 ();
196 } else {
197 AsmWriteCr3 (*CrValue);
198 }
199 break;
200 case 4:
201 if (Read) {
202 *CrValue = AsmReadCr4 ();
203 } else {
204 AsmWriteCr4 (*CrValue);
205 }
206 break;
207 default:
208 return EFI_UNSUPPORTED;;
209 }
210
211 return EFI_SUCCESS;
212 }
213
214 /**
215 Initialize the CPU registers from a register table.
216
217 @param[in] RegisterTable The register table for this AP.
218 @param[in] ApLocation AP location info for this ap.
219 @param[in] CpuStatus CPU status info for this CPU.
220 @param[in] CpuFlags Flags data structure used when program the register.
221
222 @note This service could be called by BSP/APs.
223 **/
224 VOID
225 ProgramProcessorRegister (
226 IN CPU_REGISTER_TABLE *RegisterTable,
227 IN EFI_CPU_PHYSICAL_LOCATION *ApLocation,
228 IN CPU_STATUS_INFORMATION *CpuStatus,
229 IN PROGRAM_CPU_REGISTER_FLAGS *CpuFlags
230 )
231 {
232 CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;
233 UINTN Index;
234 UINTN Value;
235 CPU_REGISTER_TABLE_ENTRY *RegisterTableEntryHead;
236 volatile UINT32 *SemaphorePtr;
237 UINT32 FirstThread;
238 UINT32 PackageThreadsCount;
239 UINT32 CurrentThread;
240 UINTN ProcessorIndex;
241 UINTN ValidThreadCount;
242 UINT32 *ValidCoreCountPerPackage;
243 EFI_STATUS Status;
244
245 //
246 // Traverse Register Table of this logical processor
247 //
248 RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry;
249
250 for (Index = 0; Index < RegisterTable->TableLength; Index++) {
251
252 RegisterTableEntry = &RegisterTableEntryHead[Index];
253
254 //
255 // Check the type of specified register
256 //
257 switch (RegisterTableEntry->RegisterType) {
258 //
259 // The specified register is Control Register
260 //
261 case ControlRegister:
262 Status = ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value);
263 if (EFI_ERROR (Status)) {
264 break;
265 }
266 Value = (UINTN) BitFieldWrite64 (
267 Value,
268 RegisterTableEntry->ValidBitStart,
269 RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
270 RegisterTableEntry->Value
271 );
272 ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value);
273 break;
274 //
275 // The specified register is Model Specific Register
276 //
277 case Msr:
278 //
279 // If this function is called to restore register setting after INIT signal,
280 // there is no need to restore MSRs in register table.
281 //
282 if (RegisterTableEntry->ValidBitLength >= 64) {
283 //
284 // If length is not less than 64 bits, then directly write without reading
285 //
286 AsmWriteMsr64 (
287 RegisterTableEntry->Index,
288 RegisterTableEntry->Value
289 );
290 } else {
291 //
292 // Set the bit section according to bit start and length
293 //
294 AsmMsrBitFieldWrite64 (
295 RegisterTableEntry->Index,
296 RegisterTableEntry->ValidBitStart,
297 RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
298 RegisterTableEntry->Value
299 );
300 }
301 break;
302 //
303 // MemoryMapped operations
304 //
305 case MemoryMapped:
306 AcquireSpinLock (&CpuFlags->MemoryMappedLock);
307 MmioBitFieldWrite32 (
308 (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)),
309 RegisterTableEntry->ValidBitStart,
310 RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
311 (UINT32)RegisterTableEntry->Value
312 );
313 ReleaseSpinLock (&CpuFlags->MemoryMappedLock);
314 break;
315 //
316 // Enable or disable cache
317 //
318 case CacheControl:
319 //
320 // If value of the entry is 0, then disable cache. Otherwise, enable cache.
321 //
322 if (RegisterTableEntry->Value == 0) {
323 AsmDisableCache ();
324 } else {
325 AsmEnableCache ();
326 }
327 break;
328
329 case Semaphore:
330 // Semaphore works logic like below:
331 //
332 // V(x) = LibReleaseSemaphore (Semaphore[FirstThread + x]);
333 // P(x) = LibWaitForSemaphore (Semaphore[FirstThread + x]);
334 //
335 // All threads (T0...Tn) waits in P() line and continues running
336 // together.
337 //
338 //
339 // T0 T1 ... Tn
340 //
341 // V(0...n) V(0...n) ... V(0...n)
342 // n * P(0) n * P(1) ... n * P(n)
343 //
344 ASSERT (
345 (ApLocation != NULL) &&
346 (CpuStatus->ValidCoreCountPerPackage != 0) &&
347 (CpuFlags->CoreSemaphoreCount != NULL) &&
348 (CpuFlags->PackageSemaphoreCount != NULL)
349 );
350 switch (RegisterTableEntry->Value) {
351 case CoreDepType:
352 SemaphorePtr = CpuFlags->CoreSemaphoreCount;
353 //
354 // Get Offset info for the first thread in the core which current thread belongs to.
355 //
356 FirstThread = (ApLocation->Package * CpuStatus->MaxCoreCount + ApLocation->Core) * CpuStatus->MaxThreadCount;
357 CurrentThread = FirstThread + ApLocation->Thread;
358 //
359 // First Notify all threads in current Core that this thread has ready.
360 //
361 for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex ++) {
362 S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
363 }
364 //
365 // Second, check whether all valid threads in current core have ready.
366 //
367 for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex ++) {
368 S3WaitForSemaphore (&SemaphorePtr[CurrentThread]);
369 }
370 break;
371
372 case PackageDepType:
373 SemaphorePtr = CpuFlags->PackageSemaphoreCount;
374 ValidCoreCountPerPackage = (UINT32 *)(UINTN)CpuStatus->ValidCoreCountPerPackage;
375 //
376 // Get Offset info for the first thread in the package which current thread belongs to.
377 //
378 FirstThread = ApLocation->Package * CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount;
379 //
380 // Get the possible threads count for current package.
381 //
382 PackageThreadsCount = CpuStatus->MaxThreadCount * CpuStatus->MaxCoreCount;
383 CurrentThread = FirstThread + CpuStatus->MaxThreadCount * ApLocation->Core + ApLocation->Thread;
384 //
385 // Get the valid thread count for current package.
386 //
387 ValidThreadCount = CpuStatus->MaxThreadCount * ValidCoreCountPerPackage[ApLocation->Package];
388
389 //
390 // Different packages may have different valid cores in them. If driver maintail clearly
391 // cores number in different packages, the logic will be much complicated.
392 // Here driver just simply records the max core number in all packages and use it as expect
393 // core number for all packages.
394 // In below two steps logic, first current thread will Release semaphore for each thread
395 // in current package. Maybe some threads are not valid in this package, but driver don't
396 // care. Second, driver will let current thread wait semaphore for all valid threads in
397 // current package. Because only the valid threads will do release semaphore for this
398 // thread, driver here only need to wait the valid thread count.
399 //
400
401 //
402 // First Notify all threads in current package that this thread has ready.
403 //
404 for (ProcessorIndex = 0; ProcessorIndex < PackageThreadsCount ; ProcessorIndex ++) {
405 S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
406 }
407 //
408 // Second, check whether all valid threads in current package have ready.
409 //
410 for (ProcessorIndex = 0; ProcessorIndex < ValidThreadCount; ProcessorIndex ++) {
411 S3WaitForSemaphore (&SemaphorePtr[CurrentThread]);
412 }
413 break;
414
415 default:
416 break;
417 }
418 break;
419
420 default:
421 break;
422 }
423 }
424 }
425
426 /**
427
428 Set Processor register for one AP.
429
430 @param PreSmmRegisterTable Use pre Smm register table or register table.
431
432 **/
433 VOID
434 SetRegister (
435 IN BOOLEAN PreSmmRegisterTable
436 )
437 {
438 CPU_REGISTER_TABLE *RegisterTable;
439 CPU_REGISTER_TABLE *RegisterTables;
440 UINT32 InitApicId;
441 UINTN ProcIndex;
442 UINTN Index;
443
444 if (PreSmmRegisterTable) {
445 RegisterTables = (CPU_REGISTER_TABLE *)(UINTN)mAcpiCpuData.PreSmmInitRegisterTable;
446 } else {
447 RegisterTables = (CPU_REGISTER_TABLE *)(UINTN)mAcpiCpuData.RegisterTable;
448 }
449
450 InitApicId = GetInitialApicId ();
451 RegisterTable = NULL;
452 ProcIndex = (UINTN)-1;
453 for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) {
454 if (RegisterTables[Index].InitialApicId == InitApicId) {
455 RegisterTable = &RegisterTables[Index];
456 ProcIndex = Index;
457 break;
458 }
459 }
460 ASSERT (RegisterTable != NULL);
461
462 if (mAcpiCpuData.ApLocation != 0) {
463 ProgramProcessorRegister (
464 RegisterTable,
465 (EFI_CPU_PHYSICAL_LOCATION *)(UINTN)mAcpiCpuData.ApLocation + ProcIndex,
466 &mAcpiCpuData.CpuStatus,
467 &mCpuFlags
468 );
469 } else {
470 ProgramProcessorRegister (
471 RegisterTable,
472 NULL,
473 &mAcpiCpuData.CpuStatus,
474 &mCpuFlags
475 );
476 }
477 }
478
479 /**
480 AP initialization before then after SMBASE relocation in the S3 boot path.
481 **/
482 VOID
483 InitializeAp (
484 VOID
485 )
486 {
487 UINTN TopOfStack;
488 UINT8 Stack[128];
489
490 LoadMtrrData (mAcpiCpuData.MtrrTable);
491
492 SetRegister (TRUE);
493
494 //
495 // Count down the number with lock mechanism.
496 //
497 InterlockedDecrement (&mNumberToFinish);
498
499 //
500 // Wait for BSP to signal SMM Base relocation done.
501 //
502 while (!mInitApsAfterSmmBaseReloc) {
503 CpuPause ();
504 }
505
506 ProgramVirtualWireMode ();
507 DisableLvtInterrupts ();
508
509 SetRegister (FALSE);
510
511 //
512 // Place AP into the safe code, count down the number with lock mechanism in the safe code.
513 //
514 TopOfStack = (UINTN) Stack + sizeof (Stack);
515 TopOfStack &= ~(UINTN) (CPU_STACK_ALIGNMENT - 1);
516 CopyMem ((VOID *) (UINTN) mApHltLoopCode, mApHltLoopCodeTemplate, sizeof (mApHltLoopCodeTemplate));
517 TransferApToSafeState ((UINTN)mApHltLoopCode, TopOfStack, (UINTN)&mNumberToFinish);
518 }
519
520 /**
521 Prepares startup vector for APs.
522
523 This function prepares startup vector for APs.
524
525 @param WorkingBuffer The address of the work buffer.
526 **/
527 VOID
528 PrepareApStartupVector (
529 EFI_PHYSICAL_ADDRESS WorkingBuffer
530 )
531 {
532 EFI_PHYSICAL_ADDRESS StartupVector;
533 MP_ASSEMBLY_ADDRESS_MAP AddressMap;
534
535 //
536 // Get the address map of startup code for AP,
537 // including code size, and offset of long jump instructions to redirect.
538 //
539 ZeroMem (&AddressMap, sizeof (AddressMap));
540 AsmGetAddressMap (&AddressMap);
541
542 StartupVector = WorkingBuffer;
543
544 //
545 // Copy AP startup code to startup vector, and then redirect the long jump
546 // instructions for mode switching.
547 //
548 CopyMem ((VOID *) (UINTN) StartupVector, AddressMap.RendezvousFunnelAddress, AddressMap.Size);
549 *(UINT32 *) (UINTN) (StartupVector + AddressMap.FlatJumpOffset + 3) = (UINT32) (StartupVector + AddressMap.PModeEntryOffset);
550 if (AddressMap.LongJumpOffset != 0) {
551 *(UINT32 *) (UINTN) (StartupVector + AddressMap.LongJumpOffset + 2) = (UINT32) (StartupVector + AddressMap.LModeEntryOffset);
552 }
553
554 //
555 // Get the start address of exchange data between BSP and AP.
556 //
557 mExchangeInfo = (MP_CPU_EXCHANGE_INFO *) (UINTN) (StartupVector + AddressMap.Size);
558 ZeroMem ((VOID *) mExchangeInfo, sizeof (MP_CPU_EXCHANGE_INFO));
559
560 CopyMem ((VOID *) (UINTN) &mExchangeInfo->GdtrProfile, (VOID *) (UINTN) mAcpiCpuData.GdtrProfile, sizeof (IA32_DESCRIPTOR));
561 CopyMem ((VOID *) (UINTN) &mExchangeInfo->IdtrProfile, (VOID *) (UINTN) mAcpiCpuData.IdtrProfile, sizeof (IA32_DESCRIPTOR));
562
563 mExchangeInfo->StackStart = (VOID *) (UINTN) mAcpiCpuData.StackAddress;
564 mExchangeInfo->StackSize = mAcpiCpuData.StackSize;
565 mExchangeInfo->BufferStart = (UINT32) StartupVector;
566 mExchangeInfo->Cr3 = (UINT32) (AsmReadCr3 ());
567 mExchangeInfo->InitializeFloatingPointUnitsAddress = (UINTN)InitializeFloatingPointUnits;
568 }
569
570 /**
571 The function is invoked before SMBASE relocation in S3 path to restores CPU status.
572
573 The function is invoked before SMBASE relocation in S3 path. It does first time microcode load
574 and restores MTRRs for both BSP and APs.
575
576 **/
577 VOID
578 InitializeCpuBeforeRebase (
579 VOID
580 )
581 {
582 LoadMtrrData (mAcpiCpuData.MtrrTable);
583
584 SetRegister (TRUE);
585
586 ProgramVirtualWireMode ();
587
588 PrepareApStartupVector (mAcpiCpuData.StartupVector);
589
590 mNumberToFinish = mAcpiCpuData.NumberOfCpus - 1;
591 mExchangeInfo->ApFunction = (VOID *) (UINTN) InitializeAp;
592
593 //
594 // Execute code for before SmmBaseReloc. Note: This flag is maintained across S3 boots.
595 //
596 mInitApsAfterSmmBaseReloc = FALSE;
597
598 //
599 // Send INIT IPI - SIPI to all APs
600 //
601 SendInitSipiSipiAllExcludingSelf ((UINT32)mAcpiCpuData.StartupVector);
602
603 while (mNumberToFinish > 0) {
604 CpuPause ();
605 }
606 }
607
608 /**
609 The function is invoked after SMBASE relocation in S3 path to restores CPU status.
610
611 The function is invoked after SMBASE relocation in S3 path. It restores configuration according to
612 data saved by normal boot path for both BSP and APs.
613
614 **/
615 VOID
616 InitializeCpuAfterRebase (
617 VOID
618 )
619 {
620 mNumberToFinish = mAcpiCpuData.NumberOfCpus - 1;
621
622 //
623 // Signal that SMM base relocation is complete and to continue initialization for all APs.
624 //
625 mInitApsAfterSmmBaseReloc = TRUE;
626
627 //
628 // Must begin set register after all APs have continue their initialization.
629 // This is a requirement to support semaphore mechanism in register table.
630 // Because if semaphore's dependence type is package type, semaphore will wait
631 // for all Aps in one package finishing their tasks before set next register
632 // for all APs. If the Aps not begin its task during BSP doing its task, the
633 // BSP thread will hang because it is waiting for other Aps in the same
634 // package finishing their task.
635 //
636 SetRegister (FALSE);
637
638 while (mNumberToFinish > 0) {
639 CpuPause ();
640 }
641 }
642
643 /**
644 Restore SMM Configuration in S3 boot path.
645
646 **/
647 VOID
648 RestoreSmmConfigurationInS3 (
649 VOID
650 )
651 {
652 if (!mAcpiS3Enable) {
653 return;
654 }
655
656 //
657 // Restore SMM Configuration in S3 boot path.
658 //
659 if (mRestoreSmmConfigurationInS3) {
660 //
661 // Need make sure gSmst is correct because below function may use them.
662 //
663 gSmst->SmmStartupThisAp = gSmmCpuPrivate->SmmCoreEntryContext.SmmStartupThisAp;
664 gSmst->CurrentlyExecutingCpu = gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu;
665 gSmst->NumberOfCpus = gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
666 gSmst->CpuSaveStateSize = gSmmCpuPrivate->SmmCoreEntryContext.CpuSaveStateSize;
667 gSmst->CpuSaveState = gSmmCpuPrivate->SmmCoreEntryContext.CpuSaveState;
668
669 //
670 // Configure SMM Code Access Check feature if available.
671 //
672 ConfigSmmCodeAccessCheck ();
673
674 SmmCpuFeaturesCompleteSmmReadyToLock ();
675
676 mRestoreSmmConfigurationInS3 = FALSE;
677 }
678 }
679
680 /**
681 Perform SMM initialization for all processors in the S3 boot path.
682
683 For a native platform, MP initialization in the S3 boot path is also performed in this function.
684 **/
685 VOID
686 EFIAPI
687 SmmRestoreCpu (
688 VOID
689 )
690 {
691 SMM_S3_RESUME_STATE *SmmS3ResumeState;
692 IA32_DESCRIPTOR Ia32Idtr;
693 IA32_DESCRIPTOR X64Idtr;
694 IA32_IDT_GATE_DESCRIPTOR IdtEntryTable[EXCEPTION_VECTOR_NUMBER];
695 EFI_STATUS Status;
696
697 DEBUG ((EFI_D_INFO, "SmmRestoreCpu()\n"));
698
699 mSmmS3Flag = TRUE;
700
701 //
702 // See if there is enough context to resume PEI Phase
703 //
704 if (mSmmS3ResumeState == NULL) {
705 DEBUG ((EFI_D_ERROR, "No context to return to PEI Phase\n"));
706 CpuDeadLoop ();
707 }
708
709 SmmS3ResumeState = mSmmS3ResumeState;
710 ASSERT (SmmS3ResumeState != NULL);
711
712 if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {
713 //
714 // Save the IA32 IDT Descriptor
715 //
716 AsmReadIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);
717
718 //
719 // Setup X64 IDT table
720 //
721 ZeroMem (IdtEntryTable, sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32);
722 X64Idtr.Base = (UINTN) IdtEntryTable;
723 X64Idtr.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32 - 1);
724 AsmWriteIdtr ((IA32_DESCRIPTOR *) &X64Idtr);
725
726 //
727 // Setup the default exception handler
728 //
729 Status = InitializeCpuExceptionHandlers (NULL);
730 ASSERT_EFI_ERROR (Status);
731
732 //
733 // Initialize Debug Agent to support source level debug
734 //
735 InitializeDebugAgent (DEBUG_AGENT_INIT_THUNK_PEI_IA32TOX64, (VOID *)&Ia32Idtr, NULL);
736 }
737
738 //
739 // Skip initialization if mAcpiCpuData is not valid
740 //
741 if (mAcpiCpuData.NumberOfCpus > 0) {
742 //
743 // First time microcode load and restore MTRRs
744 //
745 InitializeCpuBeforeRebase ();
746 }
747
748 //
749 // Restore SMBASE for BSP and all APs
750 //
751 SmmRelocateBases ();
752
753 //
754 // Skip initialization if mAcpiCpuData is not valid
755 //
756 if (mAcpiCpuData.NumberOfCpus > 0) {
757 //
758 // Restore MSRs for BSP and all APs
759 //
760 InitializeCpuAfterRebase ();
761 }
762
763 //
764 // Set a flag to restore SMM configuration in S3 path.
765 //
766 mRestoreSmmConfigurationInS3 = TRUE;
767
768 DEBUG (( EFI_D_INFO, "SMM S3 Return CS = %x\n", SmmS3ResumeState->ReturnCs));
769 DEBUG (( EFI_D_INFO, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState->ReturnEntryPoint));
770 DEBUG (( EFI_D_INFO, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState->ReturnContext1));
771 DEBUG (( EFI_D_INFO, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState->ReturnContext2));
772 DEBUG (( EFI_D_INFO, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState->ReturnStackPointer));
773
774 //
775 // If SMM is in 32-bit mode, then use SwitchStack() to resume PEI Phase
776 //
777 if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_32) {
778 DEBUG ((EFI_D_INFO, "Call SwitchStack() to return to S3 Resume in PEI Phase\n"));
779
780 SwitchStack (
781 (SWITCH_STACK_ENTRY_POINT)(UINTN)SmmS3ResumeState->ReturnEntryPoint,
782 (VOID *)(UINTN)SmmS3ResumeState->ReturnContext1,
783 (VOID *)(UINTN)SmmS3ResumeState->ReturnContext2,
784 (VOID *)(UINTN)SmmS3ResumeState->ReturnStackPointer
785 );
786 }
787
788 //
789 // If SMM is in 64-bit mode, then use AsmDisablePaging64() to resume PEI Phase
790 //
791 if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {
792 DEBUG ((EFI_D_INFO, "Call AsmDisablePaging64() to return to S3 Resume in PEI Phase\n"));
793 //
794 // Disable interrupt of Debug timer, since new IDT table is for IA32 and will not work in long mode.
795 //
796 SaveAndSetDebugTimerInterrupt (FALSE);
797 //
798 // Restore IA32 IDT table
799 //
800 AsmWriteIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);
801 AsmDisablePaging64 (
802 SmmS3ResumeState->ReturnCs,
803 (UINT32)SmmS3ResumeState->ReturnEntryPoint,
804 (UINT32)SmmS3ResumeState->ReturnContext1,
805 (UINT32)SmmS3ResumeState->ReturnContext2,
806 (UINT32)SmmS3ResumeState->ReturnStackPointer
807 );
808 }
809
810 //
811 // Can not resume PEI Phase
812 //
813 DEBUG ((EFI_D_ERROR, "No context to return to PEI Phase\n"));
814 CpuDeadLoop ();
815 }
816
817 /**
818 Initialize SMM S3 resume state structure used during S3 Resume.
819
820 @param[in] Cr3 The base address of the page tables to use in SMM.
821
822 **/
823 VOID
824 InitSmmS3ResumeState (
825 IN UINT32 Cr3
826 )
827 {
828 VOID *GuidHob;
829 EFI_SMRAM_DESCRIPTOR *SmramDescriptor;
830 SMM_S3_RESUME_STATE *SmmS3ResumeState;
831 EFI_PHYSICAL_ADDRESS Address;
832 EFI_STATUS Status;
833
834 if (!mAcpiS3Enable) {
835 return;
836 }
837
838 GuidHob = GetFirstGuidHob (&gEfiAcpiVariableGuid);
839 if (GuidHob == NULL) {
840 DEBUG ((
841 DEBUG_ERROR,
842 "ERROR:%a(): HOB(gEfiAcpiVariableGuid=%g) needed by S3 resume doesn't exist!\n",
843 __FUNCTION__,
844 &gEfiAcpiVariableGuid
845 ));
846 CpuDeadLoop ();
847 } else {
848 SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *) GET_GUID_HOB_DATA (GuidHob);
849
850 DEBUG ((EFI_D_INFO, "SMM S3 SMRAM Structure = %x\n", SmramDescriptor));
851 DEBUG ((EFI_D_INFO, "SMM S3 Structure = %x\n", SmramDescriptor->CpuStart));
852
853 SmmS3ResumeState = (SMM_S3_RESUME_STATE *)(UINTN)SmramDescriptor->CpuStart;
854 ZeroMem (SmmS3ResumeState, sizeof (SMM_S3_RESUME_STATE));
855
856 mSmmS3ResumeState = SmmS3ResumeState;
857 SmmS3ResumeState->Smst = (EFI_PHYSICAL_ADDRESS)(UINTN)gSmst;
858
859 SmmS3ResumeState->SmmS3ResumeEntryPoint = (EFI_PHYSICAL_ADDRESS)(UINTN)SmmRestoreCpu;
860
861 SmmS3ResumeState->SmmS3StackSize = SIZE_32KB;
862 SmmS3ResumeState->SmmS3StackBase = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)SmmS3ResumeState->SmmS3StackSize));
863 if (SmmS3ResumeState->SmmS3StackBase == 0) {
864 SmmS3ResumeState->SmmS3StackSize = 0;
865 }
866
867 SmmS3ResumeState->SmmS3Cr0 = mSmmCr0;
868 SmmS3ResumeState->SmmS3Cr3 = Cr3;
869 SmmS3ResumeState->SmmS3Cr4 = mSmmCr4;
870
871 if (sizeof (UINTN) == sizeof (UINT64)) {
872 SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_64;
873 }
874 if (sizeof (UINTN) == sizeof (UINT32)) {
875 SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_32;
876 }
877
878 //
879 // Patch SmmS3ResumeState->SmmS3Cr3
880 //
881 InitSmmS3Cr3 ();
882 }
883
884 //
885 // Allocate safe memory in ACPI NVS for AP to execute hlt loop in
886 // protected mode on S3 path
887 //
888 Address = BASE_4GB - 1;
889 Status = gBS->AllocatePages (
890 AllocateMaxAddress,
891 EfiACPIMemoryNVS,
892 EFI_SIZE_TO_PAGES (sizeof (mApHltLoopCodeTemplate)),
893 &Address
894 );
895 ASSERT_EFI_ERROR (Status);
896 mApHltLoopCode = (UINT8 *) (UINTN) Address;
897 }
898
899 /**
900 Copy register table from ACPI NVS memory into SMRAM.
901
902 @param[in] DestinationRegisterTableList Points to destination register table.
903 @param[in] SourceRegisterTableList Points to source register table.
904 @param[in] NumberOfCpus Number of CPUs.
905
906 **/
907 VOID
908 CopyRegisterTable (
909 IN CPU_REGISTER_TABLE *DestinationRegisterTableList,
910 IN CPU_REGISTER_TABLE *SourceRegisterTableList,
911 IN UINT32 NumberOfCpus
912 )
913 {
914 UINTN Index;
915 CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;
916
917 CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
918 for (Index = 0; Index < NumberOfCpus; Index++) {
919 if (DestinationRegisterTableList[Index].AllocatedSize != 0) {
920 RegisterTableEntry = AllocateCopyPool (
921 DestinationRegisterTableList[Index].AllocatedSize,
922 (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry
923 );
924 ASSERT (RegisterTableEntry != NULL);
925 DestinationRegisterTableList[Index].RegisterTableEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;
926 }
927 }
928 }
929
930 /**
931 Get ACPI CPU data.
932
933 **/
934 VOID
935 GetAcpiCpuData (
936 VOID
937 )
938 {
939 ACPI_CPU_DATA *AcpiCpuData;
940 IA32_DESCRIPTOR *Gdtr;
941 IA32_DESCRIPTOR *Idtr;
942 VOID *GdtForAp;
943 VOID *IdtForAp;
944 VOID *MachineCheckHandlerForAp;
945 CPU_STATUS_INFORMATION *CpuStatus;
946
947 if (!mAcpiS3Enable) {
948 return;
949 }
950
951 //
952 // Prevent use of mAcpiCpuData by initialize NumberOfCpus to 0
953 //
954 mAcpiCpuData.NumberOfCpus = 0;
955
956 //
957 // If PcdCpuS3DataAddress was never set, then do not copy CPU S3 Data into SMRAM
958 //
959 AcpiCpuData = (ACPI_CPU_DATA *)(UINTN)PcdGet64 (PcdCpuS3DataAddress);
960 if (AcpiCpuData == 0) {
961 return;
962 }
963
964 //
965 // For a native platform, copy the CPU S3 data into SMRAM for use on CPU S3 Resume.
966 //
967 CopyMem (&mAcpiCpuData, AcpiCpuData, sizeof (mAcpiCpuData));
968
969 mAcpiCpuData.MtrrTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (MTRR_SETTINGS));
970 ASSERT (mAcpiCpuData.MtrrTable != 0);
971
972 CopyMem ((VOID *)(UINTN)mAcpiCpuData.MtrrTable, (VOID *)(UINTN)AcpiCpuData->MtrrTable, sizeof (MTRR_SETTINGS));
973
974 mAcpiCpuData.GdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (IA32_DESCRIPTOR));
975 ASSERT (mAcpiCpuData.GdtrProfile != 0);
976
977 CopyMem ((VOID *)(UINTN)mAcpiCpuData.GdtrProfile, (VOID *)(UINTN)AcpiCpuData->GdtrProfile, sizeof (IA32_DESCRIPTOR));
978
979 mAcpiCpuData.IdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (IA32_DESCRIPTOR));
980 ASSERT (mAcpiCpuData.IdtrProfile != 0);
981
982 CopyMem ((VOID *)(UINTN)mAcpiCpuData.IdtrProfile, (VOID *)(UINTN)AcpiCpuData->IdtrProfile, sizeof (IA32_DESCRIPTOR));
983
984 mAcpiCpuData.PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
985 ASSERT (mAcpiCpuData.PreSmmInitRegisterTable != 0);
986
987 CopyRegisterTable (
988 (CPU_REGISTER_TABLE *)(UINTN)mAcpiCpuData.PreSmmInitRegisterTable,
989 (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->PreSmmInitRegisterTable,
990 mAcpiCpuData.NumberOfCpus
991 );
992
993 mAcpiCpuData.RegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
994 ASSERT (mAcpiCpuData.RegisterTable != 0);
995
996 CopyRegisterTable (
997 (CPU_REGISTER_TABLE *)(UINTN)mAcpiCpuData.RegisterTable,
998 (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->RegisterTable,
999 mAcpiCpuData.NumberOfCpus
1000 );
1001
1002 //
1003 // Copy AP's GDT, IDT and Machine Check handler into SMRAM.
1004 //
1005 Gdtr = (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.GdtrProfile;
1006 Idtr = (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.IdtrProfile;
1007
1008 GdtForAp = AllocatePool ((Gdtr->Limit + 1) + (Idtr->Limit + 1) + mAcpiCpuData.ApMachineCheckHandlerSize);
1009 ASSERT (GdtForAp != NULL);
1010 IdtForAp = (VOID *) ((UINTN)GdtForAp + (Gdtr->Limit + 1));
1011 MachineCheckHandlerForAp = (VOID *) ((UINTN)IdtForAp + (Idtr->Limit + 1));
1012
1013 CopyMem (GdtForAp, (VOID *)Gdtr->Base, Gdtr->Limit + 1);
1014 CopyMem (IdtForAp, (VOID *)Idtr->Base, Idtr->Limit + 1);
1015 CopyMem (MachineCheckHandlerForAp, (VOID *)(UINTN)mAcpiCpuData.ApMachineCheckHandlerBase, mAcpiCpuData.ApMachineCheckHandlerSize);
1016
1017 Gdtr->Base = (UINTN)GdtForAp;
1018 Idtr->Base = (UINTN)IdtForAp;
1019 mAcpiCpuData.ApMachineCheckHandlerBase = (EFI_PHYSICAL_ADDRESS)(UINTN)MachineCheckHandlerForAp;
1020
1021 CpuStatus = &mAcpiCpuData.CpuStatus;
1022 CopyMem (CpuStatus, &AcpiCpuData->CpuStatus, sizeof (CPU_STATUS_INFORMATION));
1023 if (AcpiCpuData->CpuStatus.ValidCoreCountPerPackage != 0) {
1024 CpuStatus->ValidCoreCountPerPackage = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateCopyPool (
1025 sizeof (UINT32) * CpuStatus->PackageCount,
1026 (UINT32 *)(UINTN)AcpiCpuData->CpuStatus.ValidCoreCountPerPackage
1027 );
1028 ASSERT (CpuStatus->ValidCoreCountPerPackage != 0);
1029 }
1030 if (AcpiCpuData->ApLocation != 0) {
1031 mAcpiCpuData.ApLocation = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateCopyPool (
1032 mAcpiCpuData.NumberOfCpus * sizeof (EFI_CPU_PHYSICAL_LOCATION),
1033 (EFI_CPU_PHYSICAL_LOCATION *)(UINTN)AcpiCpuData->ApLocation
1034 );
1035 ASSERT (mAcpiCpuData.ApLocation != 0);
1036 }
1037 if (CpuStatus->PackageCount != 0) {
1038 mCpuFlags.CoreSemaphoreCount = AllocateZeroPool (
1039 sizeof (UINT32) * CpuStatus->PackageCount *
1040 CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount
1041 );
1042 ASSERT (mCpuFlags.CoreSemaphoreCount != NULL);
1043 mCpuFlags.PackageSemaphoreCount = AllocateZeroPool (
1044 sizeof (UINT32) * CpuStatus->PackageCount *
1045 CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount
1046 );
1047 ASSERT (mCpuFlags.PackageSemaphoreCount != NULL);
1048 }
1049 InitializeSpinLock((SPIN_LOCK*) &mCpuFlags.MemoryMappedLock);
1050 }
1051
1052 /**
1053 Get ACPI S3 enable flag.
1054
1055 **/
1056 VOID
1057 GetAcpiS3EnableFlag (
1058 VOID
1059 )
1060 {
1061 mAcpiS3Enable = PcdGetBool (PcdAcpiS3Enable);
1062 }
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