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UefiCpuPkg/PiSmmCpuDxeSmm: Remove debug message.
[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / CpuS3.c
1 /** @file
2 Code for Processor S3 restoration
3
4 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
6
7 **/
8
9 #include "PiSmmCpuDxeSmm.h"
10
11 #pragma pack(1)
12 typedef struct {
13 UINTN Lock;
14 VOID *StackStart;
15 UINTN StackSize;
16 VOID *ApFunction;
17 IA32_DESCRIPTOR GdtrProfile;
18 IA32_DESCRIPTOR IdtrProfile;
19 UINT32 BufferStart;
20 UINT32 Cr3;
21 UINTN InitializeFloatingPointUnitsAddress;
22 } MP_CPU_EXCHANGE_INFO;
23 #pragma pack()
24
25 typedef struct {
26 UINT8 *RendezvousFunnelAddress;
27 UINTN PModeEntryOffset;
28 UINTN FlatJumpOffset;
29 UINTN Size;
30 UINTN LModeEntryOffset;
31 UINTN LongJumpOffset;
32 } MP_ASSEMBLY_ADDRESS_MAP;
33
34 //
35 // Flags used when program the register.
36 //
37 typedef struct {
38 volatile UINTN ConsoleLogLock; // Spinlock used to control console.
39 volatile UINTN MemoryMappedLock; // Spinlock used to program mmio
40 volatile UINT32 *CoreSemaphoreCount; // Semaphore container used to program
41 // core level semaphore.
42 volatile UINT32 *PackageSemaphoreCount; // Semaphore container used to program
43 // package level semaphore.
44 } PROGRAM_CPU_REGISTER_FLAGS;
45
46 //
47 // Signal that SMM BASE relocation is complete.
48 //
49 volatile BOOLEAN mInitApsAfterSmmBaseReloc;
50
51 /**
52 Get starting address and size of the rendezvous entry for APs.
53 Information for fixing a jump instruction in the code is also returned.
54
55 @param AddressMap Output buffer for address map information.
56 **/
57 VOID *
58 EFIAPI
59 AsmGetAddressMap (
60 MP_ASSEMBLY_ADDRESS_MAP *AddressMap
61 );
62
63 #define LEGACY_REGION_SIZE (2 * 0x1000)
64 #define LEGACY_REGION_BASE (0xA0000 - LEGACY_REGION_SIZE)
65
66 PROGRAM_CPU_REGISTER_FLAGS mCpuFlags;
67 ACPI_CPU_DATA mAcpiCpuData;
68 volatile UINT32 mNumberToFinish;
69 MP_CPU_EXCHANGE_INFO *mExchangeInfo;
70 BOOLEAN mRestoreSmmConfigurationInS3 = FALSE;
71
72 //
73 // S3 boot flag
74 //
75 BOOLEAN mSmmS3Flag = FALSE;
76
77 //
78 // Pointer to structure used during S3 Resume
79 //
80 SMM_S3_RESUME_STATE *mSmmS3ResumeState = NULL;
81
82 BOOLEAN mAcpiS3Enable = TRUE;
83
84 UINT8 *mApHltLoopCode = NULL;
85 UINT8 mApHltLoopCodeTemplate[] = {
86 0x8B, 0x44, 0x24, 0x04, // mov eax, dword ptr [esp+4]
87 0xF0, 0xFF, 0x08, // lock dec dword ptr [eax]
88 0xFA, // cli
89 0xF4, // hlt
90 0xEB, 0xFC // jmp $-2
91 };
92
93 /**
94 Sync up the MTRR values for all processors.
95
96 @param MtrrTable Table holding fixed/variable MTRR values to be loaded.
97 **/
98 VOID
99 EFIAPI
100 LoadMtrrData (
101 EFI_PHYSICAL_ADDRESS MtrrTable
102 )
103 /*++
104
105 Routine Description:
106
107 Sync up the MTRR values for all processors.
108
109 Arguments:
110
111 Returns:
112 None
113
114 --*/
115 {
116 MTRR_SETTINGS *MtrrSettings;
117
118 MtrrSettings = (MTRR_SETTINGS *) (UINTN) MtrrTable;
119 MtrrSetAllMtrrs (MtrrSettings);
120 }
121
122 /**
123 Increment semaphore by 1.
124
125 @param Sem IN: 32-bit unsigned integer
126
127 **/
128 VOID
129 S3ReleaseSemaphore (
130 IN OUT volatile UINT32 *Sem
131 )
132 {
133 InterlockedIncrement (Sem);
134 }
135
136 /**
137 Decrement the semaphore by 1 if it is not zero.
138
139 Performs an atomic decrement operation for semaphore.
140 The compare exchange operation must be performed using
141 MP safe mechanisms.
142
143 @param Sem IN: 32-bit unsigned integer
144
145 **/
146 VOID
147 S3WaitForSemaphore (
148 IN OUT volatile UINT32 *Sem
149 )
150 {
151 UINT32 Value;
152
153 do {
154 Value = *Sem;
155 } while (Value == 0 ||
156 InterlockedCompareExchange32 (
157 Sem,
158 Value,
159 Value - 1
160 ) != Value);
161 }
162
163 /**
164 Initialize the CPU registers from a register table.
165
166 @param[in] RegisterTable The register table for this AP.
167 @param[in] ApLocation AP location info for this ap.
168 @param[in] CpuStatus CPU status info for this CPU.
169 @param[in] CpuFlags Flags data structure used when program the register.
170
171 @note This service could be called by BSP/APs.
172 **/
173 VOID
174 ProgramProcessorRegister (
175 IN CPU_REGISTER_TABLE *RegisterTable,
176 IN EFI_CPU_PHYSICAL_LOCATION *ApLocation,
177 IN CPU_STATUS_INFORMATION *CpuStatus,
178 IN PROGRAM_CPU_REGISTER_FLAGS *CpuFlags
179 )
180 {
181 CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;
182 UINTN Index;
183 UINTN Value;
184 CPU_REGISTER_TABLE_ENTRY *RegisterTableEntryHead;
185 volatile UINT32 *SemaphorePtr;
186 UINT32 FirstThread;
187 UINT32 PackageThreadsCount;
188 UINT32 CurrentThread;
189 UINTN ProcessorIndex;
190 UINTN ValidThreadCount;
191 UINT32 *ValidCoreCountPerPackage;
192
193 //
194 // Traverse Register Table of this logical processor
195 //
196 RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry;
197
198 for (Index = 0; Index < RegisterTable->TableLength; Index++) {
199
200 RegisterTableEntry = &RegisterTableEntryHead[Index];
201
202 //
203 // Check the type of specified register
204 //
205 switch (RegisterTableEntry->RegisterType) {
206 //
207 // The specified register is Control Register
208 //
209 case ControlRegister:
210 switch (RegisterTableEntry->Index) {
211 case 0:
212 Value = AsmReadCr0 ();
213 Value = (UINTN) BitFieldWrite64 (
214 Value,
215 RegisterTableEntry->ValidBitStart,
216 RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
217 (UINTN) RegisterTableEntry->Value
218 );
219 AsmWriteCr0 (Value);
220 break;
221 case 2:
222 Value = AsmReadCr2 ();
223 Value = (UINTN) BitFieldWrite64 (
224 Value,
225 RegisterTableEntry->ValidBitStart,
226 RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
227 (UINTN) RegisterTableEntry->Value
228 );
229 AsmWriteCr2 (Value);
230 break;
231 case 3:
232 Value = AsmReadCr3 ();
233 Value = (UINTN) BitFieldWrite64 (
234 Value,
235 RegisterTableEntry->ValidBitStart,
236 RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
237 (UINTN) RegisterTableEntry->Value
238 );
239 AsmWriteCr3 (Value);
240 break;
241 case 4:
242 Value = AsmReadCr4 ();
243 Value = (UINTN) BitFieldWrite64 (
244 Value,
245 RegisterTableEntry->ValidBitStart,
246 RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
247 (UINTN) RegisterTableEntry->Value
248 );
249 AsmWriteCr4 (Value);
250 break;
251 default:
252 break;
253 }
254 break;
255 //
256 // The specified register is Model Specific Register
257 //
258 case Msr:
259 //
260 // If this function is called to restore register setting after INIT signal,
261 // there is no need to restore MSRs in register table.
262 //
263 if (RegisterTableEntry->ValidBitLength >= 64) {
264 //
265 // If length is not less than 64 bits, then directly write without reading
266 //
267 AsmWriteMsr64 (
268 RegisterTableEntry->Index,
269 RegisterTableEntry->Value
270 );
271 } else {
272 //
273 // Set the bit section according to bit start and length
274 //
275 AsmMsrBitFieldWrite64 (
276 RegisterTableEntry->Index,
277 RegisterTableEntry->ValidBitStart,
278 RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
279 RegisterTableEntry->Value
280 );
281 }
282 break;
283 //
284 // MemoryMapped operations
285 //
286 case MemoryMapped:
287 AcquireSpinLock (&CpuFlags->MemoryMappedLock);
288 MmioBitFieldWrite32 (
289 (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)),
290 RegisterTableEntry->ValidBitStart,
291 RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
292 (UINT32)RegisterTableEntry->Value
293 );
294 ReleaseSpinLock (&CpuFlags->MemoryMappedLock);
295 break;
296 //
297 // Enable or disable cache
298 //
299 case CacheControl:
300 //
301 // If value of the entry is 0, then disable cache. Otherwise, enable cache.
302 //
303 if (RegisterTableEntry->Value == 0) {
304 AsmDisableCache ();
305 } else {
306 AsmEnableCache ();
307 }
308 break;
309
310 case Semaphore:
311 // Semaphore works logic like below:
312 //
313 // V(x) = LibReleaseSemaphore (Semaphore[FirstThread + x]);
314 // P(x) = LibWaitForSemaphore (Semaphore[FirstThread + x]);
315 //
316 // All threads (T0...Tn) waits in P() line and continues running
317 // together.
318 //
319 //
320 // T0 T1 ... Tn
321 //
322 // V(0...n) V(0...n) ... V(0...n)
323 // n * P(0) n * P(1) ... n * P(n)
324 //
325 ASSERT (
326 (ApLocation != NULL) &&
327 (CpuStatus->ValidCoreCountPerPackage != 0) &&
328 (CpuFlags->CoreSemaphoreCount != NULL) &&
329 (CpuFlags->PackageSemaphoreCount != NULL)
330 );
331 switch (RegisterTableEntry->Value) {
332 case CoreDepType:
333 SemaphorePtr = CpuFlags->CoreSemaphoreCount;
334 //
335 // Get Offset info for the first thread in the core which current thread belongs to.
336 //
337 FirstThread = (ApLocation->Package * CpuStatus->MaxCoreCount + ApLocation->Core) * CpuStatus->MaxThreadCount;
338 CurrentThread = FirstThread + ApLocation->Thread;
339 //
340 // First Notify all threads in current Core that this thread has ready.
341 //
342 for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex ++) {
343 S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
344 }
345 //
346 // Second, check whether all valid threads in current core have ready.
347 //
348 for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex ++) {
349 S3WaitForSemaphore (&SemaphorePtr[CurrentThread]);
350 }
351 break;
352
353 case PackageDepType:
354 SemaphorePtr = CpuFlags->PackageSemaphoreCount;
355 ValidCoreCountPerPackage = (UINT32 *)(UINTN)CpuStatus->ValidCoreCountPerPackage;
356 //
357 // Get Offset info for the first thread in the package which current thread belongs to.
358 //
359 FirstThread = ApLocation->Package * CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount;
360 //
361 // Get the possible threads count for current package.
362 //
363 PackageThreadsCount = CpuStatus->MaxThreadCount * CpuStatus->MaxCoreCount;
364 CurrentThread = FirstThread + CpuStatus->MaxThreadCount * ApLocation->Core + ApLocation->Thread;
365 //
366 // Get the valid thread count for current package.
367 //
368 ValidThreadCount = CpuStatus->MaxThreadCount * ValidCoreCountPerPackage[ApLocation->Package];
369
370 //
371 // Different packages may have different valid cores in them. If driver maintail clearly
372 // cores number in different packages, the logic will be much complicated.
373 // Here driver just simply records the max core number in all packages and use it as expect
374 // core number for all packages.
375 // In below two steps logic, first current thread will Release semaphore for each thread
376 // in current package. Maybe some threads are not valid in this package, but driver don't
377 // care. Second, driver will let current thread wait semaphore for all valid threads in
378 // current package. Because only the valid threads will do release semaphore for this
379 // thread, driver here only need to wait the valid thread count.
380 //
381
382 //
383 // First Notify all threads in current package that this thread has ready.
384 //
385 for (ProcessorIndex = 0; ProcessorIndex < PackageThreadsCount ; ProcessorIndex ++) {
386 S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
387 }
388 //
389 // Second, check whether all valid threads in current package have ready.
390 //
391 for (ProcessorIndex = 0; ProcessorIndex < ValidThreadCount; ProcessorIndex ++) {
392 S3WaitForSemaphore (&SemaphorePtr[CurrentThread]);
393 }
394 break;
395
396 default:
397 break;
398 }
399 break;
400
401 default:
402 break;
403 }
404 }
405 }
406
407 /**
408
409 Set Processor register for one AP.
410
411 @param PreSmmRegisterTable Use pre Smm register table or register table.
412
413 **/
414 VOID
415 SetRegister (
416 IN BOOLEAN PreSmmRegisterTable
417 )
418 {
419 CPU_REGISTER_TABLE *RegisterTable;
420 CPU_REGISTER_TABLE *RegisterTables;
421 UINT32 InitApicId;
422 UINTN ProcIndex;
423 UINTN Index;
424
425 if (PreSmmRegisterTable) {
426 RegisterTables = (CPU_REGISTER_TABLE *)(UINTN)mAcpiCpuData.PreSmmInitRegisterTable;
427 } else {
428 RegisterTables = (CPU_REGISTER_TABLE *)(UINTN)mAcpiCpuData.RegisterTable;
429 }
430
431 InitApicId = GetInitialApicId ();
432 RegisterTable = NULL;
433 ProcIndex = (UINTN)-1;
434 for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) {
435 if (RegisterTables[Index].InitialApicId == InitApicId) {
436 RegisterTable = &RegisterTables[Index];
437 ProcIndex = Index;
438 break;
439 }
440 }
441 ASSERT (RegisterTable != NULL);
442
443 if (mAcpiCpuData.ApLocation != 0) {
444 ProgramProcessorRegister (
445 RegisterTable,
446 (EFI_CPU_PHYSICAL_LOCATION *)(UINTN)mAcpiCpuData.ApLocation + ProcIndex,
447 &mAcpiCpuData.CpuStatus,
448 &mCpuFlags
449 );
450 } else {
451 ProgramProcessorRegister (
452 RegisterTable,
453 NULL,
454 &mAcpiCpuData.CpuStatus,
455 &mCpuFlags
456 );
457 }
458 }
459
460 /**
461 AP initialization before then after SMBASE relocation in the S3 boot path.
462 **/
463 VOID
464 InitializeAp (
465 VOID
466 )
467 {
468 UINTN TopOfStack;
469 UINT8 Stack[128];
470
471 LoadMtrrData (mAcpiCpuData.MtrrTable);
472
473 SetRegister (TRUE);
474
475 //
476 // Count down the number with lock mechanism.
477 //
478 InterlockedDecrement (&mNumberToFinish);
479
480 //
481 // Wait for BSP to signal SMM Base relocation done.
482 //
483 while (!mInitApsAfterSmmBaseReloc) {
484 CpuPause ();
485 }
486
487 ProgramVirtualWireMode ();
488 DisableLvtInterrupts ();
489
490 SetRegister (FALSE);
491
492 //
493 // Place AP into the safe code, count down the number with lock mechanism in the safe code.
494 //
495 TopOfStack = (UINTN) Stack + sizeof (Stack);
496 TopOfStack &= ~(UINTN) (CPU_STACK_ALIGNMENT - 1);
497 CopyMem ((VOID *) (UINTN) mApHltLoopCode, mApHltLoopCodeTemplate, sizeof (mApHltLoopCodeTemplate));
498 TransferApToSafeState ((UINTN)mApHltLoopCode, TopOfStack, (UINTN)&mNumberToFinish);
499 }
500
501 /**
502 Prepares startup vector for APs.
503
504 This function prepares startup vector for APs.
505
506 @param WorkingBuffer The address of the work buffer.
507 **/
508 VOID
509 PrepareApStartupVector (
510 EFI_PHYSICAL_ADDRESS WorkingBuffer
511 )
512 {
513 EFI_PHYSICAL_ADDRESS StartupVector;
514 MP_ASSEMBLY_ADDRESS_MAP AddressMap;
515
516 //
517 // Get the address map of startup code for AP,
518 // including code size, and offset of long jump instructions to redirect.
519 //
520 ZeroMem (&AddressMap, sizeof (AddressMap));
521 AsmGetAddressMap (&AddressMap);
522
523 StartupVector = WorkingBuffer;
524
525 //
526 // Copy AP startup code to startup vector, and then redirect the long jump
527 // instructions for mode switching.
528 //
529 CopyMem ((VOID *) (UINTN) StartupVector, AddressMap.RendezvousFunnelAddress, AddressMap.Size);
530 *(UINT32 *) (UINTN) (StartupVector + AddressMap.FlatJumpOffset + 3) = (UINT32) (StartupVector + AddressMap.PModeEntryOffset);
531 if (AddressMap.LongJumpOffset != 0) {
532 *(UINT32 *) (UINTN) (StartupVector + AddressMap.LongJumpOffset + 2) = (UINT32) (StartupVector + AddressMap.LModeEntryOffset);
533 }
534
535 //
536 // Get the start address of exchange data between BSP and AP.
537 //
538 mExchangeInfo = (MP_CPU_EXCHANGE_INFO *) (UINTN) (StartupVector + AddressMap.Size);
539 ZeroMem ((VOID *) mExchangeInfo, sizeof (MP_CPU_EXCHANGE_INFO));
540
541 CopyMem ((VOID *) (UINTN) &mExchangeInfo->GdtrProfile, (VOID *) (UINTN) mAcpiCpuData.GdtrProfile, sizeof (IA32_DESCRIPTOR));
542 CopyMem ((VOID *) (UINTN) &mExchangeInfo->IdtrProfile, (VOID *) (UINTN) mAcpiCpuData.IdtrProfile, sizeof (IA32_DESCRIPTOR));
543
544 mExchangeInfo->StackStart = (VOID *) (UINTN) mAcpiCpuData.StackAddress;
545 mExchangeInfo->StackSize = mAcpiCpuData.StackSize;
546 mExchangeInfo->BufferStart = (UINT32) StartupVector;
547 mExchangeInfo->Cr3 = (UINT32) (AsmReadCr3 ());
548 mExchangeInfo->InitializeFloatingPointUnitsAddress = (UINTN)InitializeFloatingPointUnits;
549 }
550
551 /**
552 The function is invoked before SMBASE relocation in S3 path to restores CPU status.
553
554 The function is invoked before SMBASE relocation in S3 path. It does first time microcode load
555 and restores MTRRs for both BSP and APs.
556
557 **/
558 VOID
559 InitializeCpuBeforeRebase (
560 VOID
561 )
562 {
563 LoadMtrrData (mAcpiCpuData.MtrrTable);
564
565 SetRegister (TRUE);
566
567 ProgramVirtualWireMode ();
568
569 PrepareApStartupVector (mAcpiCpuData.StartupVector);
570
571 mNumberToFinish = mAcpiCpuData.NumberOfCpus - 1;
572 mExchangeInfo->ApFunction = (VOID *) (UINTN) InitializeAp;
573
574 //
575 // Execute code for before SmmBaseReloc. Note: This flag is maintained across S3 boots.
576 //
577 mInitApsAfterSmmBaseReloc = FALSE;
578
579 //
580 // Send INIT IPI - SIPI to all APs
581 //
582 SendInitSipiSipiAllExcludingSelf ((UINT32)mAcpiCpuData.StartupVector);
583
584 while (mNumberToFinish > 0) {
585 CpuPause ();
586 }
587 }
588
589 /**
590 The function is invoked after SMBASE relocation in S3 path to restores CPU status.
591
592 The function is invoked after SMBASE relocation in S3 path. It restores configuration according to
593 data saved by normal boot path for both BSP and APs.
594
595 **/
596 VOID
597 InitializeCpuAfterRebase (
598 VOID
599 )
600 {
601 mNumberToFinish = mAcpiCpuData.NumberOfCpus - 1;
602
603 //
604 // Signal that SMM base relocation is complete and to continue initialization for all APs.
605 //
606 mInitApsAfterSmmBaseReloc = TRUE;
607
608 //
609 // Must begin set register after all APs have continue their initialization.
610 // This is a requirement to support semaphore mechanism in register table.
611 // Because if semaphore's dependence type is package type, semaphore will wait
612 // for all Aps in one package finishing their tasks before set next register
613 // for all APs. If the Aps not begin its task during BSP doing its task, the
614 // BSP thread will hang because it is waiting for other Aps in the same
615 // package finishing their task.
616 //
617 SetRegister (FALSE);
618
619 while (mNumberToFinish > 0) {
620 CpuPause ();
621 }
622 }
623
624 /**
625 Restore SMM Configuration in S3 boot path.
626
627 **/
628 VOID
629 RestoreSmmConfigurationInS3 (
630 VOID
631 )
632 {
633 if (!mAcpiS3Enable) {
634 return;
635 }
636
637 //
638 // Restore SMM Configuration in S3 boot path.
639 //
640 if (mRestoreSmmConfigurationInS3) {
641 //
642 // Need make sure gSmst is correct because below function may use them.
643 //
644 gSmst->SmmStartupThisAp = gSmmCpuPrivate->SmmCoreEntryContext.SmmStartupThisAp;
645 gSmst->CurrentlyExecutingCpu = gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu;
646 gSmst->NumberOfCpus = gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
647 gSmst->CpuSaveStateSize = gSmmCpuPrivate->SmmCoreEntryContext.CpuSaveStateSize;
648 gSmst->CpuSaveState = gSmmCpuPrivate->SmmCoreEntryContext.CpuSaveState;
649
650 //
651 // Configure SMM Code Access Check feature if available.
652 //
653 ConfigSmmCodeAccessCheck ();
654
655 SmmCpuFeaturesCompleteSmmReadyToLock ();
656
657 mRestoreSmmConfigurationInS3 = FALSE;
658 }
659 }
660
661 /**
662 Perform SMM initialization for all processors in the S3 boot path.
663
664 For a native platform, MP initialization in the S3 boot path is also performed in this function.
665 **/
666 VOID
667 EFIAPI
668 SmmRestoreCpu (
669 VOID
670 )
671 {
672 SMM_S3_RESUME_STATE *SmmS3ResumeState;
673 IA32_DESCRIPTOR Ia32Idtr;
674 IA32_DESCRIPTOR X64Idtr;
675 IA32_IDT_GATE_DESCRIPTOR IdtEntryTable[EXCEPTION_VECTOR_NUMBER];
676 EFI_STATUS Status;
677
678 DEBUG ((EFI_D_INFO, "SmmRestoreCpu()\n"));
679
680 mSmmS3Flag = TRUE;
681
682 //
683 // See if there is enough context to resume PEI Phase
684 //
685 if (mSmmS3ResumeState == NULL) {
686 DEBUG ((EFI_D_ERROR, "No context to return to PEI Phase\n"));
687 CpuDeadLoop ();
688 }
689
690 SmmS3ResumeState = mSmmS3ResumeState;
691 ASSERT (SmmS3ResumeState != NULL);
692
693 if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {
694 //
695 // Save the IA32 IDT Descriptor
696 //
697 AsmReadIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);
698
699 //
700 // Setup X64 IDT table
701 //
702 ZeroMem (IdtEntryTable, sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32);
703 X64Idtr.Base = (UINTN) IdtEntryTable;
704 X64Idtr.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32 - 1);
705 AsmWriteIdtr ((IA32_DESCRIPTOR *) &X64Idtr);
706
707 //
708 // Setup the default exception handler
709 //
710 Status = InitializeCpuExceptionHandlers (NULL);
711 ASSERT_EFI_ERROR (Status);
712
713 //
714 // Initialize Debug Agent to support source level debug
715 //
716 InitializeDebugAgent (DEBUG_AGENT_INIT_THUNK_PEI_IA32TOX64, (VOID *)&Ia32Idtr, NULL);
717 }
718
719 //
720 // Skip initialization if mAcpiCpuData is not valid
721 //
722 if (mAcpiCpuData.NumberOfCpus > 0) {
723 //
724 // First time microcode load and restore MTRRs
725 //
726 InitializeCpuBeforeRebase ();
727 }
728
729 //
730 // Restore SMBASE for BSP and all APs
731 //
732 SmmRelocateBases ();
733
734 //
735 // Skip initialization if mAcpiCpuData is not valid
736 //
737 if (mAcpiCpuData.NumberOfCpus > 0) {
738 //
739 // Restore MSRs for BSP and all APs
740 //
741 InitializeCpuAfterRebase ();
742 }
743
744 //
745 // Set a flag to restore SMM configuration in S3 path.
746 //
747 mRestoreSmmConfigurationInS3 = TRUE;
748
749 DEBUG (( EFI_D_INFO, "SMM S3 Return CS = %x\n", SmmS3ResumeState->ReturnCs));
750 DEBUG (( EFI_D_INFO, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState->ReturnEntryPoint));
751 DEBUG (( EFI_D_INFO, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState->ReturnContext1));
752 DEBUG (( EFI_D_INFO, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState->ReturnContext2));
753 DEBUG (( EFI_D_INFO, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState->ReturnStackPointer));
754
755 //
756 // If SMM is in 32-bit mode, then use SwitchStack() to resume PEI Phase
757 //
758 if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_32) {
759 DEBUG ((EFI_D_INFO, "Call SwitchStack() to return to S3 Resume in PEI Phase\n"));
760
761 SwitchStack (
762 (SWITCH_STACK_ENTRY_POINT)(UINTN)SmmS3ResumeState->ReturnEntryPoint,
763 (VOID *)(UINTN)SmmS3ResumeState->ReturnContext1,
764 (VOID *)(UINTN)SmmS3ResumeState->ReturnContext2,
765 (VOID *)(UINTN)SmmS3ResumeState->ReturnStackPointer
766 );
767 }
768
769 //
770 // If SMM is in 64-bit mode, then use AsmDisablePaging64() to resume PEI Phase
771 //
772 if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {
773 DEBUG ((EFI_D_INFO, "Call AsmDisablePaging64() to return to S3 Resume in PEI Phase\n"));
774 //
775 // Disable interrupt of Debug timer, since new IDT table is for IA32 and will not work in long mode.
776 //
777 SaveAndSetDebugTimerInterrupt (FALSE);
778 //
779 // Restore IA32 IDT table
780 //
781 AsmWriteIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);
782 AsmDisablePaging64 (
783 SmmS3ResumeState->ReturnCs,
784 (UINT32)SmmS3ResumeState->ReturnEntryPoint,
785 (UINT32)SmmS3ResumeState->ReturnContext1,
786 (UINT32)SmmS3ResumeState->ReturnContext2,
787 (UINT32)SmmS3ResumeState->ReturnStackPointer
788 );
789 }
790
791 //
792 // Can not resume PEI Phase
793 //
794 DEBUG ((EFI_D_ERROR, "No context to return to PEI Phase\n"));
795 CpuDeadLoop ();
796 }
797
798 /**
799 Initialize SMM S3 resume state structure used during S3 Resume.
800
801 @param[in] Cr3 The base address of the page tables to use in SMM.
802
803 **/
804 VOID
805 InitSmmS3ResumeState (
806 IN UINT32 Cr3
807 )
808 {
809 VOID *GuidHob;
810 EFI_SMRAM_DESCRIPTOR *SmramDescriptor;
811 SMM_S3_RESUME_STATE *SmmS3ResumeState;
812 EFI_PHYSICAL_ADDRESS Address;
813 EFI_STATUS Status;
814
815 if (!mAcpiS3Enable) {
816 return;
817 }
818
819 GuidHob = GetFirstGuidHob (&gEfiAcpiVariableGuid);
820 if (GuidHob == NULL) {
821 DEBUG ((
822 DEBUG_ERROR,
823 "ERROR:%a(): HOB(gEfiAcpiVariableGuid=%g) needed by S3 resume doesn't exist!\n",
824 __FUNCTION__,
825 &gEfiAcpiVariableGuid
826 ));
827 CpuDeadLoop ();
828 } else {
829 SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *) GET_GUID_HOB_DATA (GuidHob);
830
831 DEBUG ((EFI_D_INFO, "SMM S3 SMRAM Structure = %x\n", SmramDescriptor));
832 DEBUG ((EFI_D_INFO, "SMM S3 Structure = %x\n", SmramDescriptor->CpuStart));
833
834 SmmS3ResumeState = (SMM_S3_RESUME_STATE *)(UINTN)SmramDescriptor->CpuStart;
835 ZeroMem (SmmS3ResumeState, sizeof (SMM_S3_RESUME_STATE));
836
837 mSmmS3ResumeState = SmmS3ResumeState;
838 SmmS3ResumeState->Smst = (EFI_PHYSICAL_ADDRESS)(UINTN)gSmst;
839
840 SmmS3ResumeState->SmmS3ResumeEntryPoint = (EFI_PHYSICAL_ADDRESS)(UINTN)SmmRestoreCpu;
841
842 SmmS3ResumeState->SmmS3StackSize = SIZE_32KB;
843 SmmS3ResumeState->SmmS3StackBase = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)SmmS3ResumeState->SmmS3StackSize));
844 if (SmmS3ResumeState->SmmS3StackBase == 0) {
845 SmmS3ResumeState->SmmS3StackSize = 0;
846 }
847
848 SmmS3ResumeState->SmmS3Cr0 = mSmmCr0;
849 SmmS3ResumeState->SmmS3Cr3 = Cr3;
850 SmmS3ResumeState->SmmS3Cr4 = mSmmCr4;
851
852 if (sizeof (UINTN) == sizeof (UINT64)) {
853 SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_64;
854 }
855 if (sizeof (UINTN) == sizeof (UINT32)) {
856 SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_32;
857 }
858
859 //
860 // Patch SmmS3ResumeState->SmmS3Cr3
861 //
862 InitSmmS3Cr3 ();
863 }
864
865 //
866 // Allocate safe memory in ACPI NVS for AP to execute hlt loop in
867 // protected mode on S3 path
868 //
869 Address = BASE_4GB - 1;
870 Status = gBS->AllocatePages (
871 AllocateMaxAddress,
872 EfiACPIMemoryNVS,
873 EFI_SIZE_TO_PAGES (sizeof (mApHltLoopCodeTemplate)),
874 &Address
875 );
876 ASSERT_EFI_ERROR (Status);
877 mApHltLoopCode = (UINT8 *) (UINTN) Address;
878 }
879
880 /**
881 Copy register table from ACPI NVS memory into SMRAM.
882
883 @param[in] DestinationRegisterTableList Points to destination register table.
884 @param[in] SourceRegisterTableList Points to source register table.
885 @param[in] NumberOfCpus Number of CPUs.
886
887 **/
888 VOID
889 CopyRegisterTable (
890 IN CPU_REGISTER_TABLE *DestinationRegisterTableList,
891 IN CPU_REGISTER_TABLE *SourceRegisterTableList,
892 IN UINT32 NumberOfCpus
893 )
894 {
895 UINTN Index;
896 CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;
897
898 CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
899 for (Index = 0; Index < NumberOfCpus; Index++) {
900 if (DestinationRegisterTableList[Index].AllocatedSize != 0) {
901 RegisterTableEntry = AllocateCopyPool (
902 DestinationRegisterTableList[Index].AllocatedSize,
903 (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry
904 );
905 ASSERT (RegisterTableEntry != NULL);
906 DestinationRegisterTableList[Index].RegisterTableEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;
907 }
908 }
909 }
910
911 /**
912 Get ACPI CPU data.
913
914 **/
915 VOID
916 GetAcpiCpuData (
917 VOID
918 )
919 {
920 ACPI_CPU_DATA *AcpiCpuData;
921 IA32_DESCRIPTOR *Gdtr;
922 IA32_DESCRIPTOR *Idtr;
923 VOID *GdtForAp;
924 VOID *IdtForAp;
925 VOID *MachineCheckHandlerForAp;
926 CPU_STATUS_INFORMATION *CpuStatus;
927
928 if (!mAcpiS3Enable) {
929 return;
930 }
931
932 //
933 // Prevent use of mAcpiCpuData by initialize NumberOfCpus to 0
934 //
935 mAcpiCpuData.NumberOfCpus = 0;
936
937 //
938 // If PcdCpuS3DataAddress was never set, then do not copy CPU S3 Data into SMRAM
939 //
940 AcpiCpuData = (ACPI_CPU_DATA *)(UINTN)PcdGet64 (PcdCpuS3DataAddress);
941 if (AcpiCpuData == 0) {
942 return;
943 }
944
945 //
946 // For a native platform, copy the CPU S3 data into SMRAM for use on CPU S3 Resume.
947 //
948 CopyMem (&mAcpiCpuData, AcpiCpuData, sizeof (mAcpiCpuData));
949
950 mAcpiCpuData.MtrrTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (MTRR_SETTINGS));
951 ASSERT (mAcpiCpuData.MtrrTable != 0);
952
953 CopyMem ((VOID *)(UINTN)mAcpiCpuData.MtrrTable, (VOID *)(UINTN)AcpiCpuData->MtrrTable, sizeof (MTRR_SETTINGS));
954
955 mAcpiCpuData.GdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (IA32_DESCRIPTOR));
956 ASSERT (mAcpiCpuData.GdtrProfile != 0);
957
958 CopyMem ((VOID *)(UINTN)mAcpiCpuData.GdtrProfile, (VOID *)(UINTN)AcpiCpuData->GdtrProfile, sizeof (IA32_DESCRIPTOR));
959
960 mAcpiCpuData.IdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (IA32_DESCRIPTOR));
961 ASSERT (mAcpiCpuData.IdtrProfile != 0);
962
963 CopyMem ((VOID *)(UINTN)mAcpiCpuData.IdtrProfile, (VOID *)(UINTN)AcpiCpuData->IdtrProfile, sizeof (IA32_DESCRIPTOR));
964
965 mAcpiCpuData.PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
966 ASSERT (mAcpiCpuData.PreSmmInitRegisterTable != 0);
967
968 CopyRegisterTable (
969 (CPU_REGISTER_TABLE *)(UINTN)mAcpiCpuData.PreSmmInitRegisterTable,
970 (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->PreSmmInitRegisterTable,
971 mAcpiCpuData.NumberOfCpus
972 );
973
974 mAcpiCpuData.RegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
975 ASSERT (mAcpiCpuData.RegisterTable != 0);
976
977 CopyRegisterTable (
978 (CPU_REGISTER_TABLE *)(UINTN)mAcpiCpuData.RegisterTable,
979 (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->RegisterTable,
980 mAcpiCpuData.NumberOfCpus
981 );
982
983 //
984 // Copy AP's GDT, IDT and Machine Check handler into SMRAM.
985 //
986 Gdtr = (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.GdtrProfile;
987 Idtr = (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.IdtrProfile;
988
989 GdtForAp = AllocatePool ((Gdtr->Limit + 1) + (Idtr->Limit + 1) + mAcpiCpuData.ApMachineCheckHandlerSize);
990 ASSERT (GdtForAp != NULL);
991 IdtForAp = (VOID *) ((UINTN)GdtForAp + (Gdtr->Limit + 1));
992 MachineCheckHandlerForAp = (VOID *) ((UINTN)IdtForAp + (Idtr->Limit + 1));
993
994 CopyMem (GdtForAp, (VOID *)Gdtr->Base, Gdtr->Limit + 1);
995 CopyMem (IdtForAp, (VOID *)Idtr->Base, Idtr->Limit + 1);
996 CopyMem (MachineCheckHandlerForAp, (VOID *)(UINTN)mAcpiCpuData.ApMachineCheckHandlerBase, mAcpiCpuData.ApMachineCheckHandlerSize);
997
998 Gdtr->Base = (UINTN)GdtForAp;
999 Idtr->Base = (UINTN)IdtForAp;
1000 mAcpiCpuData.ApMachineCheckHandlerBase = (EFI_PHYSICAL_ADDRESS)(UINTN)MachineCheckHandlerForAp;
1001
1002 CpuStatus = &mAcpiCpuData.CpuStatus;
1003 CopyMem (CpuStatus, &AcpiCpuData->CpuStatus, sizeof (CPU_STATUS_INFORMATION));
1004 if (AcpiCpuData->CpuStatus.ValidCoreCountPerPackage != 0) {
1005 CpuStatus->ValidCoreCountPerPackage = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateCopyPool (
1006 sizeof (UINT32) * CpuStatus->PackageCount,
1007 (UINT32 *)(UINTN)AcpiCpuData->CpuStatus.ValidCoreCountPerPackage
1008 );
1009 ASSERT (CpuStatus->ValidCoreCountPerPackage != 0);
1010 }
1011 if (AcpiCpuData->ApLocation != 0) {
1012 mAcpiCpuData.ApLocation = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateCopyPool (
1013 mAcpiCpuData.NumberOfCpus * sizeof (EFI_CPU_PHYSICAL_LOCATION),
1014 (EFI_CPU_PHYSICAL_LOCATION *)(UINTN)AcpiCpuData->ApLocation
1015 );
1016 ASSERT (mAcpiCpuData.ApLocation != 0);
1017 }
1018 if (CpuStatus->PackageCount != 0) {
1019 mCpuFlags.CoreSemaphoreCount = AllocateZeroPool (
1020 sizeof (UINT32) * CpuStatus->PackageCount *
1021 CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount
1022 );
1023 ASSERT (mCpuFlags.CoreSemaphoreCount != NULL);
1024 mCpuFlags.PackageSemaphoreCount = AllocateZeroPool (
1025 sizeof (UINT32) * CpuStatus->PackageCount *
1026 CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount
1027 );
1028 ASSERT (mCpuFlags.PackageSemaphoreCount != NULL);
1029 }
1030 InitializeSpinLock((SPIN_LOCK*) &mCpuFlags.MemoryMappedLock);
1031 InitializeSpinLock((SPIN_LOCK*) &mCpuFlags.ConsoleLogLock);
1032 }
1033
1034 /**
1035 Get ACPI S3 enable flag.
1036
1037 **/
1038 VOID
1039 GetAcpiS3EnableFlag (
1040 VOID
1041 )
1042 {
1043 mAcpiS3Enable = PcdGetBool (PcdAcpiS3Enable);
1044 }
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