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[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / CpuS3.c
1 /** @file
2 Code for Processor S3 restoration
3
4 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
6
7 **/
8
9 #include "PiSmmCpuDxeSmm.h"
10
11 #pragma pack(1)
12 typedef struct {
13 UINTN Lock;
14 VOID *StackStart;
15 UINTN StackSize;
16 VOID *ApFunction;
17 IA32_DESCRIPTOR GdtrProfile;
18 IA32_DESCRIPTOR IdtrProfile;
19 UINT32 BufferStart;
20 UINT32 Cr3;
21 UINTN InitializeFloatingPointUnitsAddress;
22 } MP_CPU_EXCHANGE_INFO;
23 #pragma pack()
24
25 typedef struct {
26 UINT8 *RendezvousFunnelAddress;
27 UINTN PModeEntryOffset;
28 UINTN FlatJumpOffset;
29 UINTN Size;
30 UINTN LModeEntryOffset;
31 UINTN LongJumpOffset;
32 } MP_ASSEMBLY_ADDRESS_MAP;
33
34 //
35 // Flags used when program the register.
36 //
37 typedef struct {
38 volatile UINTN MemoryMappedLock; // Spinlock used to program mmio
39 volatile UINT32 *CoreSemaphoreCount; // Semaphore container used to program
40 // core level semaphore.
41 volatile UINT32 *PackageSemaphoreCount; // Semaphore container used to program
42 // package level semaphore.
43 } PROGRAM_CPU_REGISTER_FLAGS;
44
45 //
46 // Signal that SMM BASE relocation is complete.
47 //
48 volatile BOOLEAN mInitApsAfterSmmBaseReloc;
49
50 /**
51 Get starting address and size of the rendezvous entry for APs.
52 Information for fixing a jump instruction in the code is also returned.
53
54 @param AddressMap Output buffer for address map information.
55 **/
56 VOID *
57 EFIAPI
58 AsmGetAddressMap (
59 MP_ASSEMBLY_ADDRESS_MAP *AddressMap
60 );
61
62 #define LEGACY_REGION_SIZE (2 * 0x1000)
63 #define LEGACY_REGION_BASE (0xA0000 - LEGACY_REGION_SIZE)
64
65 PROGRAM_CPU_REGISTER_FLAGS mCpuFlags;
66 ACPI_CPU_DATA mAcpiCpuData;
67 volatile UINT32 mNumberToFinish;
68 MP_CPU_EXCHANGE_INFO *mExchangeInfo;
69 BOOLEAN mRestoreSmmConfigurationInS3 = FALSE;
70
71 //
72 // S3 boot flag
73 //
74 BOOLEAN mSmmS3Flag = FALSE;
75
76 //
77 // Pointer to structure used during S3 Resume
78 //
79 SMM_S3_RESUME_STATE *mSmmS3ResumeState = NULL;
80
81 BOOLEAN mAcpiS3Enable = TRUE;
82
83 UINT8 *mApHltLoopCode = NULL;
84 UINT8 mApHltLoopCodeTemplate[] = {
85 0x8B, 0x44, 0x24, 0x04, // mov eax, dword ptr [esp+4]
86 0xF0, 0xFF, 0x08, // lock dec dword ptr [eax]
87 0xFA, // cli
88 0xF4, // hlt
89 0xEB, 0xFC // jmp $-2
90 };
91
92 /**
93 Sync up the MTRR values for all processors.
94
95 @param MtrrTable Table holding fixed/variable MTRR values to be loaded.
96 **/
97 VOID
98 EFIAPI
99 LoadMtrrData (
100 EFI_PHYSICAL_ADDRESS MtrrTable
101 )
102 /*++
103
104 Routine Description:
105
106 Sync up the MTRR values for all processors.
107
108 Arguments:
109
110 Returns:
111 None
112
113 --*/
114 {
115 MTRR_SETTINGS *MtrrSettings;
116
117 MtrrSettings = (MTRR_SETTINGS *) (UINTN) MtrrTable;
118 MtrrSetAllMtrrs (MtrrSettings);
119 }
120
121 /**
122 Increment semaphore by 1.
123
124 @param Sem IN: 32-bit unsigned integer
125
126 **/
127 VOID
128 S3ReleaseSemaphore (
129 IN OUT volatile UINT32 *Sem
130 )
131 {
132 InterlockedIncrement (Sem);
133 }
134
135 /**
136 Decrement the semaphore by 1 if it is not zero.
137
138 Performs an atomic decrement operation for semaphore.
139 The compare exchange operation must be performed using
140 MP safe mechanisms.
141
142 @param Sem IN: 32-bit unsigned integer
143
144 **/
145 VOID
146 S3WaitForSemaphore (
147 IN OUT volatile UINT32 *Sem
148 )
149 {
150 UINT32 Value;
151
152 do {
153 Value = *Sem;
154 } while (Value == 0 ||
155 InterlockedCompareExchange32 (
156 Sem,
157 Value,
158 Value - 1
159 ) != Value);
160 }
161
162 /**
163 Initialize the CPU registers from a register table.
164
165 @param[in] RegisterTable The register table for this AP.
166 @param[in] ApLocation AP location info for this ap.
167 @param[in] CpuStatus CPU status info for this CPU.
168 @param[in] CpuFlags Flags data structure used when program the register.
169
170 @note This service could be called by BSP/APs.
171 **/
172 VOID
173 ProgramProcessorRegister (
174 IN CPU_REGISTER_TABLE *RegisterTable,
175 IN EFI_CPU_PHYSICAL_LOCATION *ApLocation,
176 IN CPU_STATUS_INFORMATION *CpuStatus,
177 IN PROGRAM_CPU_REGISTER_FLAGS *CpuFlags
178 )
179 {
180 CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;
181 UINTN Index;
182 UINTN Value;
183 CPU_REGISTER_TABLE_ENTRY *RegisterTableEntryHead;
184 volatile UINT32 *SemaphorePtr;
185 UINT32 FirstThread;
186 UINT32 PackageThreadsCount;
187 UINT32 CurrentThread;
188 UINTN ProcessorIndex;
189 UINTN ValidThreadCount;
190 UINT32 *ValidCoreCountPerPackage;
191
192 //
193 // Traverse Register Table of this logical processor
194 //
195 RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry;
196
197 for (Index = 0; Index < RegisterTable->TableLength; Index++) {
198
199 RegisterTableEntry = &RegisterTableEntryHead[Index];
200
201 //
202 // Check the type of specified register
203 //
204 switch (RegisterTableEntry->RegisterType) {
205 //
206 // The specified register is Control Register
207 //
208 case ControlRegister:
209 switch (RegisterTableEntry->Index) {
210 case 0:
211 Value = AsmReadCr0 ();
212 Value = (UINTN) BitFieldWrite64 (
213 Value,
214 RegisterTableEntry->ValidBitStart,
215 RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
216 (UINTN) RegisterTableEntry->Value
217 );
218 AsmWriteCr0 (Value);
219 break;
220 case 2:
221 Value = AsmReadCr2 ();
222 Value = (UINTN) BitFieldWrite64 (
223 Value,
224 RegisterTableEntry->ValidBitStart,
225 RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
226 (UINTN) RegisterTableEntry->Value
227 );
228 AsmWriteCr2 (Value);
229 break;
230 case 3:
231 Value = AsmReadCr3 ();
232 Value = (UINTN) BitFieldWrite64 (
233 Value,
234 RegisterTableEntry->ValidBitStart,
235 RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
236 (UINTN) RegisterTableEntry->Value
237 );
238 AsmWriteCr3 (Value);
239 break;
240 case 4:
241 Value = AsmReadCr4 ();
242 Value = (UINTN) BitFieldWrite64 (
243 Value,
244 RegisterTableEntry->ValidBitStart,
245 RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
246 (UINTN) RegisterTableEntry->Value
247 );
248 AsmWriteCr4 (Value);
249 break;
250 default:
251 break;
252 }
253 break;
254 //
255 // The specified register is Model Specific Register
256 //
257 case Msr:
258 //
259 // If this function is called to restore register setting after INIT signal,
260 // there is no need to restore MSRs in register table.
261 //
262 if (RegisterTableEntry->ValidBitLength >= 64) {
263 //
264 // If length is not less than 64 bits, then directly write without reading
265 //
266 AsmWriteMsr64 (
267 RegisterTableEntry->Index,
268 RegisterTableEntry->Value
269 );
270 } else {
271 //
272 // Set the bit section according to bit start and length
273 //
274 AsmMsrBitFieldWrite64 (
275 RegisterTableEntry->Index,
276 RegisterTableEntry->ValidBitStart,
277 RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
278 RegisterTableEntry->Value
279 );
280 }
281 break;
282 //
283 // MemoryMapped operations
284 //
285 case MemoryMapped:
286 AcquireSpinLock (&CpuFlags->MemoryMappedLock);
287 MmioBitFieldWrite32 (
288 (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)),
289 RegisterTableEntry->ValidBitStart,
290 RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
291 (UINT32)RegisterTableEntry->Value
292 );
293 ReleaseSpinLock (&CpuFlags->MemoryMappedLock);
294 break;
295 //
296 // Enable or disable cache
297 //
298 case CacheControl:
299 //
300 // If value of the entry is 0, then disable cache. Otherwise, enable cache.
301 //
302 if (RegisterTableEntry->Value == 0) {
303 AsmDisableCache ();
304 } else {
305 AsmEnableCache ();
306 }
307 break;
308
309 case Semaphore:
310 // Semaphore works logic like below:
311 //
312 // V(x) = LibReleaseSemaphore (Semaphore[FirstThread + x]);
313 // P(x) = LibWaitForSemaphore (Semaphore[FirstThread + x]);
314 //
315 // All threads (T0...Tn) waits in P() line and continues running
316 // together.
317 //
318 //
319 // T0 T1 ... Tn
320 //
321 // V(0...n) V(0...n) ... V(0...n)
322 // n * P(0) n * P(1) ... n * P(n)
323 //
324 ASSERT (
325 (ApLocation != NULL) &&
326 (CpuStatus->ValidCoreCountPerPackage != 0) &&
327 (CpuFlags->CoreSemaphoreCount != NULL) &&
328 (CpuFlags->PackageSemaphoreCount != NULL)
329 );
330 switch (RegisterTableEntry->Value) {
331 case CoreDepType:
332 SemaphorePtr = CpuFlags->CoreSemaphoreCount;
333 //
334 // Get Offset info for the first thread in the core which current thread belongs to.
335 //
336 FirstThread = (ApLocation->Package * CpuStatus->MaxCoreCount + ApLocation->Core) * CpuStatus->MaxThreadCount;
337 CurrentThread = FirstThread + ApLocation->Thread;
338 //
339 // First Notify all threads in current Core that this thread has ready.
340 //
341 for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex ++) {
342 S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
343 }
344 //
345 // Second, check whether all valid threads in current core have ready.
346 //
347 for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex ++) {
348 S3WaitForSemaphore (&SemaphorePtr[CurrentThread]);
349 }
350 break;
351
352 case PackageDepType:
353 SemaphorePtr = CpuFlags->PackageSemaphoreCount;
354 ValidCoreCountPerPackage = (UINT32 *)(UINTN)CpuStatus->ValidCoreCountPerPackage;
355 //
356 // Get Offset info for the first thread in the package which current thread belongs to.
357 //
358 FirstThread = ApLocation->Package * CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount;
359 //
360 // Get the possible threads count for current package.
361 //
362 PackageThreadsCount = CpuStatus->MaxThreadCount * CpuStatus->MaxCoreCount;
363 CurrentThread = FirstThread + CpuStatus->MaxThreadCount * ApLocation->Core + ApLocation->Thread;
364 //
365 // Get the valid thread count for current package.
366 //
367 ValidThreadCount = CpuStatus->MaxThreadCount * ValidCoreCountPerPackage[ApLocation->Package];
368
369 //
370 // Different packages may have different valid cores in them. If driver maintail clearly
371 // cores number in different packages, the logic will be much complicated.
372 // Here driver just simply records the max core number in all packages and use it as expect
373 // core number for all packages.
374 // In below two steps logic, first current thread will Release semaphore for each thread
375 // in current package. Maybe some threads are not valid in this package, but driver don't
376 // care. Second, driver will let current thread wait semaphore for all valid threads in
377 // current package. Because only the valid threads will do release semaphore for this
378 // thread, driver here only need to wait the valid thread count.
379 //
380
381 //
382 // First Notify all threads in current package that this thread has ready.
383 //
384 for (ProcessorIndex = 0; ProcessorIndex < PackageThreadsCount ; ProcessorIndex ++) {
385 S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
386 }
387 //
388 // Second, check whether all valid threads in current package have ready.
389 //
390 for (ProcessorIndex = 0; ProcessorIndex < ValidThreadCount; ProcessorIndex ++) {
391 S3WaitForSemaphore (&SemaphorePtr[CurrentThread]);
392 }
393 break;
394
395 default:
396 break;
397 }
398 break;
399
400 default:
401 break;
402 }
403 }
404 }
405
406 /**
407
408 Set Processor register for one AP.
409
410 @param PreSmmRegisterTable Use pre Smm register table or register table.
411
412 **/
413 VOID
414 SetRegister (
415 IN BOOLEAN PreSmmRegisterTable
416 )
417 {
418 CPU_REGISTER_TABLE *RegisterTable;
419 CPU_REGISTER_TABLE *RegisterTables;
420 UINT32 InitApicId;
421 UINTN ProcIndex;
422 UINTN Index;
423
424 if (PreSmmRegisterTable) {
425 RegisterTables = (CPU_REGISTER_TABLE *)(UINTN)mAcpiCpuData.PreSmmInitRegisterTable;
426 } else {
427 RegisterTables = (CPU_REGISTER_TABLE *)(UINTN)mAcpiCpuData.RegisterTable;
428 }
429
430 InitApicId = GetInitialApicId ();
431 RegisterTable = NULL;
432 ProcIndex = (UINTN)-1;
433 for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) {
434 if (RegisterTables[Index].InitialApicId == InitApicId) {
435 RegisterTable = &RegisterTables[Index];
436 ProcIndex = Index;
437 break;
438 }
439 }
440 ASSERT (RegisterTable != NULL);
441
442 if (mAcpiCpuData.ApLocation != 0) {
443 ProgramProcessorRegister (
444 RegisterTable,
445 (EFI_CPU_PHYSICAL_LOCATION *)(UINTN)mAcpiCpuData.ApLocation + ProcIndex,
446 &mAcpiCpuData.CpuStatus,
447 &mCpuFlags
448 );
449 } else {
450 ProgramProcessorRegister (
451 RegisterTable,
452 NULL,
453 &mAcpiCpuData.CpuStatus,
454 &mCpuFlags
455 );
456 }
457 }
458
459 /**
460 AP initialization before then after SMBASE relocation in the S3 boot path.
461 **/
462 VOID
463 InitializeAp (
464 VOID
465 )
466 {
467 UINTN TopOfStack;
468 UINT8 Stack[128];
469
470 LoadMtrrData (mAcpiCpuData.MtrrTable);
471
472 SetRegister (TRUE);
473
474 //
475 // Count down the number with lock mechanism.
476 //
477 InterlockedDecrement (&mNumberToFinish);
478
479 //
480 // Wait for BSP to signal SMM Base relocation done.
481 //
482 while (!mInitApsAfterSmmBaseReloc) {
483 CpuPause ();
484 }
485
486 ProgramVirtualWireMode ();
487 DisableLvtInterrupts ();
488
489 SetRegister (FALSE);
490
491 //
492 // Place AP into the safe code, count down the number with lock mechanism in the safe code.
493 //
494 TopOfStack = (UINTN) Stack + sizeof (Stack);
495 TopOfStack &= ~(UINTN) (CPU_STACK_ALIGNMENT - 1);
496 CopyMem ((VOID *) (UINTN) mApHltLoopCode, mApHltLoopCodeTemplate, sizeof (mApHltLoopCodeTemplate));
497 TransferApToSafeState ((UINTN)mApHltLoopCode, TopOfStack, (UINTN)&mNumberToFinish);
498 }
499
500 /**
501 Prepares startup vector for APs.
502
503 This function prepares startup vector for APs.
504
505 @param WorkingBuffer The address of the work buffer.
506 **/
507 VOID
508 PrepareApStartupVector (
509 EFI_PHYSICAL_ADDRESS WorkingBuffer
510 )
511 {
512 EFI_PHYSICAL_ADDRESS StartupVector;
513 MP_ASSEMBLY_ADDRESS_MAP AddressMap;
514
515 //
516 // Get the address map of startup code for AP,
517 // including code size, and offset of long jump instructions to redirect.
518 //
519 ZeroMem (&AddressMap, sizeof (AddressMap));
520 AsmGetAddressMap (&AddressMap);
521
522 StartupVector = WorkingBuffer;
523
524 //
525 // Copy AP startup code to startup vector, and then redirect the long jump
526 // instructions for mode switching.
527 //
528 CopyMem ((VOID *) (UINTN) StartupVector, AddressMap.RendezvousFunnelAddress, AddressMap.Size);
529 *(UINT32 *) (UINTN) (StartupVector + AddressMap.FlatJumpOffset + 3) = (UINT32) (StartupVector + AddressMap.PModeEntryOffset);
530 if (AddressMap.LongJumpOffset != 0) {
531 *(UINT32 *) (UINTN) (StartupVector + AddressMap.LongJumpOffset + 2) = (UINT32) (StartupVector + AddressMap.LModeEntryOffset);
532 }
533
534 //
535 // Get the start address of exchange data between BSP and AP.
536 //
537 mExchangeInfo = (MP_CPU_EXCHANGE_INFO *) (UINTN) (StartupVector + AddressMap.Size);
538 ZeroMem ((VOID *) mExchangeInfo, sizeof (MP_CPU_EXCHANGE_INFO));
539
540 CopyMem ((VOID *) (UINTN) &mExchangeInfo->GdtrProfile, (VOID *) (UINTN) mAcpiCpuData.GdtrProfile, sizeof (IA32_DESCRIPTOR));
541 CopyMem ((VOID *) (UINTN) &mExchangeInfo->IdtrProfile, (VOID *) (UINTN) mAcpiCpuData.IdtrProfile, sizeof (IA32_DESCRIPTOR));
542
543 mExchangeInfo->StackStart = (VOID *) (UINTN) mAcpiCpuData.StackAddress;
544 mExchangeInfo->StackSize = mAcpiCpuData.StackSize;
545 mExchangeInfo->BufferStart = (UINT32) StartupVector;
546 mExchangeInfo->Cr3 = (UINT32) (AsmReadCr3 ());
547 mExchangeInfo->InitializeFloatingPointUnitsAddress = (UINTN)InitializeFloatingPointUnits;
548 }
549
550 /**
551 The function is invoked before SMBASE relocation in S3 path to restores CPU status.
552
553 The function is invoked before SMBASE relocation in S3 path. It does first time microcode load
554 and restores MTRRs for both BSP and APs.
555
556 **/
557 VOID
558 InitializeCpuBeforeRebase (
559 VOID
560 )
561 {
562 LoadMtrrData (mAcpiCpuData.MtrrTable);
563
564 SetRegister (TRUE);
565
566 ProgramVirtualWireMode ();
567
568 PrepareApStartupVector (mAcpiCpuData.StartupVector);
569
570 mNumberToFinish = mAcpiCpuData.NumberOfCpus - 1;
571 mExchangeInfo->ApFunction = (VOID *) (UINTN) InitializeAp;
572
573 //
574 // Execute code for before SmmBaseReloc. Note: This flag is maintained across S3 boots.
575 //
576 mInitApsAfterSmmBaseReloc = FALSE;
577
578 //
579 // Send INIT IPI - SIPI to all APs
580 //
581 SendInitSipiSipiAllExcludingSelf ((UINT32)mAcpiCpuData.StartupVector);
582
583 while (mNumberToFinish > 0) {
584 CpuPause ();
585 }
586 }
587
588 /**
589 The function is invoked after SMBASE relocation in S3 path to restores CPU status.
590
591 The function is invoked after SMBASE relocation in S3 path. It restores configuration according to
592 data saved by normal boot path for both BSP and APs.
593
594 **/
595 VOID
596 InitializeCpuAfterRebase (
597 VOID
598 )
599 {
600 mNumberToFinish = mAcpiCpuData.NumberOfCpus - 1;
601
602 //
603 // Signal that SMM base relocation is complete and to continue initialization for all APs.
604 //
605 mInitApsAfterSmmBaseReloc = TRUE;
606
607 //
608 // Must begin set register after all APs have continue their initialization.
609 // This is a requirement to support semaphore mechanism in register table.
610 // Because if semaphore's dependence type is package type, semaphore will wait
611 // for all Aps in one package finishing their tasks before set next register
612 // for all APs. If the Aps not begin its task during BSP doing its task, the
613 // BSP thread will hang because it is waiting for other Aps in the same
614 // package finishing their task.
615 //
616 SetRegister (FALSE);
617
618 while (mNumberToFinish > 0) {
619 CpuPause ();
620 }
621 }
622
623 /**
624 Restore SMM Configuration in S3 boot path.
625
626 **/
627 VOID
628 RestoreSmmConfigurationInS3 (
629 VOID
630 )
631 {
632 if (!mAcpiS3Enable) {
633 return;
634 }
635
636 //
637 // Restore SMM Configuration in S3 boot path.
638 //
639 if (mRestoreSmmConfigurationInS3) {
640 //
641 // Need make sure gSmst is correct because below function may use them.
642 //
643 gSmst->SmmStartupThisAp = gSmmCpuPrivate->SmmCoreEntryContext.SmmStartupThisAp;
644 gSmst->CurrentlyExecutingCpu = gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu;
645 gSmst->NumberOfCpus = gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
646 gSmst->CpuSaveStateSize = gSmmCpuPrivate->SmmCoreEntryContext.CpuSaveStateSize;
647 gSmst->CpuSaveState = gSmmCpuPrivate->SmmCoreEntryContext.CpuSaveState;
648
649 //
650 // Configure SMM Code Access Check feature if available.
651 //
652 ConfigSmmCodeAccessCheck ();
653
654 SmmCpuFeaturesCompleteSmmReadyToLock ();
655
656 mRestoreSmmConfigurationInS3 = FALSE;
657 }
658 }
659
660 /**
661 Perform SMM initialization for all processors in the S3 boot path.
662
663 For a native platform, MP initialization in the S3 boot path is also performed in this function.
664 **/
665 VOID
666 EFIAPI
667 SmmRestoreCpu (
668 VOID
669 )
670 {
671 SMM_S3_RESUME_STATE *SmmS3ResumeState;
672 IA32_DESCRIPTOR Ia32Idtr;
673 IA32_DESCRIPTOR X64Idtr;
674 IA32_IDT_GATE_DESCRIPTOR IdtEntryTable[EXCEPTION_VECTOR_NUMBER];
675 EFI_STATUS Status;
676
677 DEBUG ((EFI_D_INFO, "SmmRestoreCpu()\n"));
678
679 mSmmS3Flag = TRUE;
680
681 //
682 // See if there is enough context to resume PEI Phase
683 //
684 if (mSmmS3ResumeState == NULL) {
685 DEBUG ((EFI_D_ERROR, "No context to return to PEI Phase\n"));
686 CpuDeadLoop ();
687 }
688
689 SmmS3ResumeState = mSmmS3ResumeState;
690 ASSERT (SmmS3ResumeState != NULL);
691
692 if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {
693 //
694 // Save the IA32 IDT Descriptor
695 //
696 AsmReadIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);
697
698 //
699 // Setup X64 IDT table
700 //
701 ZeroMem (IdtEntryTable, sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32);
702 X64Idtr.Base = (UINTN) IdtEntryTable;
703 X64Idtr.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32 - 1);
704 AsmWriteIdtr ((IA32_DESCRIPTOR *) &X64Idtr);
705
706 //
707 // Setup the default exception handler
708 //
709 Status = InitializeCpuExceptionHandlers (NULL);
710 ASSERT_EFI_ERROR (Status);
711
712 //
713 // Initialize Debug Agent to support source level debug
714 //
715 InitializeDebugAgent (DEBUG_AGENT_INIT_THUNK_PEI_IA32TOX64, (VOID *)&Ia32Idtr, NULL);
716 }
717
718 //
719 // Skip initialization if mAcpiCpuData is not valid
720 //
721 if (mAcpiCpuData.NumberOfCpus > 0) {
722 //
723 // First time microcode load and restore MTRRs
724 //
725 InitializeCpuBeforeRebase ();
726 }
727
728 //
729 // Restore SMBASE for BSP and all APs
730 //
731 SmmRelocateBases ();
732
733 //
734 // Skip initialization if mAcpiCpuData is not valid
735 //
736 if (mAcpiCpuData.NumberOfCpus > 0) {
737 //
738 // Restore MSRs for BSP and all APs
739 //
740 InitializeCpuAfterRebase ();
741 }
742
743 //
744 // Set a flag to restore SMM configuration in S3 path.
745 //
746 mRestoreSmmConfigurationInS3 = TRUE;
747
748 DEBUG (( EFI_D_INFO, "SMM S3 Return CS = %x\n", SmmS3ResumeState->ReturnCs));
749 DEBUG (( EFI_D_INFO, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState->ReturnEntryPoint));
750 DEBUG (( EFI_D_INFO, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState->ReturnContext1));
751 DEBUG (( EFI_D_INFO, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState->ReturnContext2));
752 DEBUG (( EFI_D_INFO, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState->ReturnStackPointer));
753
754 //
755 // If SMM is in 32-bit mode, then use SwitchStack() to resume PEI Phase
756 //
757 if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_32) {
758 DEBUG ((EFI_D_INFO, "Call SwitchStack() to return to S3 Resume in PEI Phase\n"));
759
760 SwitchStack (
761 (SWITCH_STACK_ENTRY_POINT)(UINTN)SmmS3ResumeState->ReturnEntryPoint,
762 (VOID *)(UINTN)SmmS3ResumeState->ReturnContext1,
763 (VOID *)(UINTN)SmmS3ResumeState->ReturnContext2,
764 (VOID *)(UINTN)SmmS3ResumeState->ReturnStackPointer
765 );
766 }
767
768 //
769 // If SMM is in 64-bit mode, then use AsmDisablePaging64() to resume PEI Phase
770 //
771 if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {
772 DEBUG ((EFI_D_INFO, "Call AsmDisablePaging64() to return to S3 Resume in PEI Phase\n"));
773 //
774 // Disable interrupt of Debug timer, since new IDT table is for IA32 and will not work in long mode.
775 //
776 SaveAndSetDebugTimerInterrupt (FALSE);
777 //
778 // Restore IA32 IDT table
779 //
780 AsmWriteIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);
781 AsmDisablePaging64 (
782 SmmS3ResumeState->ReturnCs,
783 (UINT32)SmmS3ResumeState->ReturnEntryPoint,
784 (UINT32)SmmS3ResumeState->ReturnContext1,
785 (UINT32)SmmS3ResumeState->ReturnContext2,
786 (UINT32)SmmS3ResumeState->ReturnStackPointer
787 );
788 }
789
790 //
791 // Can not resume PEI Phase
792 //
793 DEBUG ((EFI_D_ERROR, "No context to return to PEI Phase\n"));
794 CpuDeadLoop ();
795 }
796
797 /**
798 Initialize SMM S3 resume state structure used during S3 Resume.
799
800 @param[in] Cr3 The base address of the page tables to use in SMM.
801
802 **/
803 VOID
804 InitSmmS3ResumeState (
805 IN UINT32 Cr3
806 )
807 {
808 VOID *GuidHob;
809 EFI_SMRAM_DESCRIPTOR *SmramDescriptor;
810 SMM_S3_RESUME_STATE *SmmS3ResumeState;
811 EFI_PHYSICAL_ADDRESS Address;
812 EFI_STATUS Status;
813
814 if (!mAcpiS3Enable) {
815 return;
816 }
817
818 GuidHob = GetFirstGuidHob (&gEfiAcpiVariableGuid);
819 if (GuidHob == NULL) {
820 DEBUG ((
821 DEBUG_ERROR,
822 "ERROR:%a(): HOB(gEfiAcpiVariableGuid=%g) needed by S3 resume doesn't exist!\n",
823 __FUNCTION__,
824 &gEfiAcpiVariableGuid
825 ));
826 CpuDeadLoop ();
827 } else {
828 SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *) GET_GUID_HOB_DATA (GuidHob);
829
830 DEBUG ((EFI_D_INFO, "SMM S3 SMRAM Structure = %x\n", SmramDescriptor));
831 DEBUG ((EFI_D_INFO, "SMM S3 Structure = %x\n", SmramDescriptor->CpuStart));
832
833 SmmS3ResumeState = (SMM_S3_RESUME_STATE *)(UINTN)SmramDescriptor->CpuStart;
834 ZeroMem (SmmS3ResumeState, sizeof (SMM_S3_RESUME_STATE));
835
836 mSmmS3ResumeState = SmmS3ResumeState;
837 SmmS3ResumeState->Smst = (EFI_PHYSICAL_ADDRESS)(UINTN)gSmst;
838
839 SmmS3ResumeState->SmmS3ResumeEntryPoint = (EFI_PHYSICAL_ADDRESS)(UINTN)SmmRestoreCpu;
840
841 SmmS3ResumeState->SmmS3StackSize = SIZE_32KB;
842 SmmS3ResumeState->SmmS3StackBase = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)SmmS3ResumeState->SmmS3StackSize));
843 if (SmmS3ResumeState->SmmS3StackBase == 0) {
844 SmmS3ResumeState->SmmS3StackSize = 0;
845 }
846
847 SmmS3ResumeState->SmmS3Cr0 = mSmmCr0;
848 SmmS3ResumeState->SmmS3Cr3 = Cr3;
849 SmmS3ResumeState->SmmS3Cr4 = mSmmCr4;
850
851 if (sizeof (UINTN) == sizeof (UINT64)) {
852 SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_64;
853 }
854 if (sizeof (UINTN) == sizeof (UINT32)) {
855 SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_32;
856 }
857
858 //
859 // Patch SmmS3ResumeState->SmmS3Cr3
860 //
861 InitSmmS3Cr3 ();
862 }
863
864 //
865 // Allocate safe memory in ACPI NVS for AP to execute hlt loop in
866 // protected mode on S3 path
867 //
868 Address = BASE_4GB - 1;
869 Status = gBS->AllocatePages (
870 AllocateMaxAddress,
871 EfiACPIMemoryNVS,
872 EFI_SIZE_TO_PAGES (sizeof (mApHltLoopCodeTemplate)),
873 &Address
874 );
875 ASSERT_EFI_ERROR (Status);
876 mApHltLoopCode = (UINT8 *) (UINTN) Address;
877 }
878
879 /**
880 Copy register table from ACPI NVS memory into SMRAM.
881
882 @param[in] DestinationRegisterTableList Points to destination register table.
883 @param[in] SourceRegisterTableList Points to source register table.
884 @param[in] NumberOfCpus Number of CPUs.
885
886 **/
887 VOID
888 CopyRegisterTable (
889 IN CPU_REGISTER_TABLE *DestinationRegisterTableList,
890 IN CPU_REGISTER_TABLE *SourceRegisterTableList,
891 IN UINT32 NumberOfCpus
892 )
893 {
894 UINTN Index;
895 CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;
896
897 CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
898 for (Index = 0; Index < NumberOfCpus; Index++) {
899 if (DestinationRegisterTableList[Index].AllocatedSize != 0) {
900 RegisterTableEntry = AllocateCopyPool (
901 DestinationRegisterTableList[Index].AllocatedSize,
902 (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry
903 );
904 ASSERT (RegisterTableEntry != NULL);
905 DestinationRegisterTableList[Index].RegisterTableEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;
906 }
907 }
908 }
909
910 /**
911 Get ACPI CPU data.
912
913 **/
914 VOID
915 GetAcpiCpuData (
916 VOID
917 )
918 {
919 ACPI_CPU_DATA *AcpiCpuData;
920 IA32_DESCRIPTOR *Gdtr;
921 IA32_DESCRIPTOR *Idtr;
922 VOID *GdtForAp;
923 VOID *IdtForAp;
924 VOID *MachineCheckHandlerForAp;
925 CPU_STATUS_INFORMATION *CpuStatus;
926
927 if (!mAcpiS3Enable) {
928 return;
929 }
930
931 //
932 // Prevent use of mAcpiCpuData by initialize NumberOfCpus to 0
933 //
934 mAcpiCpuData.NumberOfCpus = 0;
935
936 //
937 // If PcdCpuS3DataAddress was never set, then do not copy CPU S3 Data into SMRAM
938 //
939 AcpiCpuData = (ACPI_CPU_DATA *)(UINTN)PcdGet64 (PcdCpuS3DataAddress);
940 if (AcpiCpuData == 0) {
941 return;
942 }
943
944 //
945 // For a native platform, copy the CPU S3 data into SMRAM for use on CPU S3 Resume.
946 //
947 CopyMem (&mAcpiCpuData, AcpiCpuData, sizeof (mAcpiCpuData));
948
949 mAcpiCpuData.MtrrTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (MTRR_SETTINGS));
950 ASSERT (mAcpiCpuData.MtrrTable != 0);
951
952 CopyMem ((VOID *)(UINTN)mAcpiCpuData.MtrrTable, (VOID *)(UINTN)AcpiCpuData->MtrrTable, sizeof (MTRR_SETTINGS));
953
954 mAcpiCpuData.GdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (IA32_DESCRIPTOR));
955 ASSERT (mAcpiCpuData.GdtrProfile != 0);
956
957 CopyMem ((VOID *)(UINTN)mAcpiCpuData.GdtrProfile, (VOID *)(UINTN)AcpiCpuData->GdtrProfile, sizeof (IA32_DESCRIPTOR));
958
959 mAcpiCpuData.IdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (IA32_DESCRIPTOR));
960 ASSERT (mAcpiCpuData.IdtrProfile != 0);
961
962 CopyMem ((VOID *)(UINTN)mAcpiCpuData.IdtrProfile, (VOID *)(UINTN)AcpiCpuData->IdtrProfile, sizeof (IA32_DESCRIPTOR));
963
964 mAcpiCpuData.PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
965 ASSERT (mAcpiCpuData.PreSmmInitRegisterTable != 0);
966
967 CopyRegisterTable (
968 (CPU_REGISTER_TABLE *)(UINTN)mAcpiCpuData.PreSmmInitRegisterTable,
969 (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->PreSmmInitRegisterTable,
970 mAcpiCpuData.NumberOfCpus
971 );
972
973 mAcpiCpuData.RegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
974 ASSERT (mAcpiCpuData.RegisterTable != 0);
975
976 CopyRegisterTable (
977 (CPU_REGISTER_TABLE *)(UINTN)mAcpiCpuData.RegisterTable,
978 (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->RegisterTable,
979 mAcpiCpuData.NumberOfCpus
980 );
981
982 //
983 // Copy AP's GDT, IDT and Machine Check handler into SMRAM.
984 //
985 Gdtr = (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.GdtrProfile;
986 Idtr = (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.IdtrProfile;
987
988 GdtForAp = AllocatePool ((Gdtr->Limit + 1) + (Idtr->Limit + 1) + mAcpiCpuData.ApMachineCheckHandlerSize);
989 ASSERT (GdtForAp != NULL);
990 IdtForAp = (VOID *) ((UINTN)GdtForAp + (Gdtr->Limit + 1));
991 MachineCheckHandlerForAp = (VOID *) ((UINTN)IdtForAp + (Idtr->Limit + 1));
992
993 CopyMem (GdtForAp, (VOID *)Gdtr->Base, Gdtr->Limit + 1);
994 CopyMem (IdtForAp, (VOID *)Idtr->Base, Idtr->Limit + 1);
995 CopyMem (MachineCheckHandlerForAp, (VOID *)(UINTN)mAcpiCpuData.ApMachineCheckHandlerBase, mAcpiCpuData.ApMachineCheckHandlerSize);
996
997 Gdtr->Base = (UINTN)GdtForAp;
998 Idtr->Base = (UINTN)IdtForAp;
999 mAcpiCpuData.ApMachineCheckHandlerBase = (EFI_PHYSICAL_ADDRESS)(UINTN)MachineCheckHandlerForAp;
1000
1001 CpuStatus = &mAcpiCpuData.CpuStatus;
1002 CopyMem (CpuStatus, &AcpiCpuData->CpuStatus, sizeof (CPU_STATUS_INFORMATION));
1003 if (AcpiCpuData->CpuStatus.ValidCoreCountPerPackage != 0) {
1004 CpuStatus->ValidCoreCountPerPackage = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateCopyPool (
1005 sizeof (UINT32) * CpuStatus->PackageCount,
1006 (UINT32 *)(UINTN)AcpiCpuData->CpuStatus.ValidCoreCountPerPackage
1007 );
1008 ASSERT (CpuStatus->ValidCoreCountPerPackage != 0);
1009 }
1010 if (AcpiCpuData->ApLocation != 0) {
1011 mAcpiCpuData.ApLocation = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateCopyPool (
1012 mAcpiCpuData.NumberOfCpus * sizeof (EFI_CPU_PHYSICAL_LOCATION),
1013 (EFI_CPU_PHYSICAL_LOCATION *)(UINTN)AcpiCpuData->ApLocation
1014 );
1015 ASSERT (mAcpiCpuData.ApLocation != 0);
1016 }
1017 if (CpuStatus->PackageCount != 0) {
1018 mCpuFlags.CoreSemaphoreCount = AllocateZeroPool (
1019 sizeof (UINT32) * CpuStatus->PackageCount *
1020 CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount
1021 );
1022 ASSERT (mCpuFlags.CoreSemaphoreCount != NULL);
1023 mCpuFlags.PackageSemaphoreCount = AllocateZeroPool (
1024 sizeof (UINT32) * CpuStatus->PackageCount *
1025 CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount
1026 );
1027 ASSERT (mCpuFlags.PackageSemaphoreCount != NULL);
1028 }
1029 InitializeSpinLock((SPIN_LOCK*) &mCpuFlags.MemoryMappedLock);
1030 }
1031
1032 /**
1033 Get ACPI S3 enable flag.
1034
1035 **/
1036 VOID
1037 GetAcpiS3EnableFlag (
1038 VOID
1039 )
1040 {
1041 mAcpiS3Enable = PcdGetBool (PcdAcpiS3Enable);
1042 }
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