1 #------------------------------------------------------------------------------
3 # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
4 # This program and the accompanying materials
5 # are licensed and made available under the terms and conditions of the BSD License
6 # which accompanies this distribution. The full text of the license may be found at
7 # http://opensource.org/licenses/bsd-license.php.
9 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 # Code template of the SMI handler for a particular processor
20 #------------------------------------------------------------------------------
22 ASM_GLOBAL ASM_PFX(gcSmiHandlerTemplate)
23 ASM_GLOBAL ASM_PFX(gcSmiHandlerSize)
24 ASM_GLOBAL ASM_PFX(gSmiCr3)
25 ASM_GLOBAL ASM_PFX(gSmiStack)
26 ASM_GLOBAL ASM_PFX(gSmbase)
27 ASM_GLOBAL ASM_PFX(mXdSupported)
28 ASM_GLOBAL ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
29 ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr)
31 .equ MSR_EFER, 0xc0000080
32 .equ MSR_EFER_XD, 0x800
34 .equ DSC_OFFSET, 0xfb00
42 .equ PROTECT_MODE_CS, 0x08
43 .equ PROTECT_MODE_DS, 0x20
44 .equ TSS_SEGMENT, 0x40
48 ASM_PFX(gcSmiHandlerTemplate):
51 .byte 0xbb # mov bx, imm16
52 .word _GdtDesc - _SmiEntryPoint + 0x8000
53 .byte 0x2e,0xa1 # mov ax, cs:[offset16]
54 .word DSC_OFFSET + DSC_GDTSIZ
56 movl %eax, %cs:(%edi) # mov cs:[bx], ax
57 .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
58 .word DSC_OFFSET + DSC_GDTPTR
60 movw %ax, %bp # ebp = GDT base
63 # Patch ProtectedMode Segment
64 .byte 0xb8 # mov ax, imm16
65 .word PROTECT_MODE_CS # set AX for segment directly
66 movl %eax, %cs:-2(%edi) # mov cs:[bx - 2], ax
67 # Patch ProtectedMode entry
68 .byte 0x66, 0xbf # mov edi, SMBASE
69 ASM_PFX(gSmbase): .space 4
71 lea ((Start32bit - _SmiEntryPoint) + 0x8000)(%edi), %ax
72 movw %ax, %cs:-6(%edi)
75 andl $0x9ffafff3, %ebx
86 movw $PROTECT_MODE_DS, %ax
92 .byte 0xbc # mov esp, imm32
93 ASM_PFX(gSmiStack): .space 4
94 movl $ASM_PFX(gSmiHandlerIdtr), %eax
99 .byte 0xb8 # mov eax, imm32
100 ASM_PFX(gSmiCr3): .space 4
103 # Need to test for CR4 specific bit support
106 cpuid # use CPUID to determine if specific CR4 bits are supported
107 xorl %eax, %eax # Clear EAX
108 testl $BIT2, %edx # Check for DE capabilities
112 testl $BIT6, %edx # Check for PAE capabilities
116 testl $BIT7, %edx # Check for MCE capabilities
120 testl $BIT24, %edx # Check for FXSR capabilities
124 testl $BIT25, %edx # Check for SSE capabilities
127 L12: # as cr4.PGE is not set here, refresh cr3
128 movl %eax, %cr4 # in PreModifyMtrrs() to flush TLB.
130 cmpb $0, ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
133 movb $0x89, (TSS_SEGMENT + 5)(%ebp) # clear busy flag
134 movl $TSS_SEGMENT, %eax
138 # enable NXE if supported
139 .byte 0xb0 # mov al, imm8
140 ASM_PFX(mXdSupported): .byte 1
144 # Check XD disable bit
146 movl $MSR_IA32_MISC_ENABLE, %ecx
148 pushl %edx # save MSR_IA32_MISC_ENABLE[63-32]
149 testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
151 andw $0x0FFFB, %dx # clear XD Disable bit if it is set
156 orw $MSR_EFER_XD,%ax # enable NXE
163 orl $0x080010023, %ebx # enable paging + WP + NE + MP + PE
165 leal DSC_OFFSET(%edi),%ebx
166 movw DSC_DS(%ebx),%ax
168 movw DSC_OTHERSEG(%ebx),%ax
172 movw DSC_SS(%ebx),%ax
175 # jmp _SmiHandler # instruction is not needed
181 movl $ASM_PFX(CpuSmmDebugEntry), %eax
186 movl $ASM_PFX(SmiRendezvous), %eax
191 movl $ASM_PFX(CpuSmmDebugExit), %eax
195 movl $ASM_PFX(mXdSupported), %eax
199 popl %edx # get saved MSR_IA32_MISC_ENABLE[63-32]
202 movl $MSR_IA32_MISC_ENABLE, %ecx
204 orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM
210 ASM_PFX(gcSmiHandlerSize): .word . - _SmiEntryPoint