1 #------------------------------------------------------------------------------
3 # Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
4 # This program and the accompanying materials
5 # are licensed and made available under the terms and conditions of the BSD License
6 # which accompanies this distribution. The full text of the license may be found at
7 # http://opensource.org/licenses/bsd-license.php.
9 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 # Code template of the SMI handler for a particular processor
20 #------------------------------------------------------------------------------
22 ASM_GLOBAL ASM_PFX(gcSmiHandlerTemplate)
23 ASM_GLOBAL ASM_PFX(gcSmiHandlerSize)
24 ASM_GLOBAL ASM_PFX(gSmiCr3)
25 ASM_GLOBAL ASM_PFX(gSmiStack)
26 ASM_GLOBAL ASM_PFX(gSmbase)
27 ASM_GLOBAL ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
28 ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr)
30 .equ DSC_OFFSET, 0xfb00
38 .equ PROTECT_MODE_CS, 0x08
39 .equ PROTECT_MODE_DS, 0x20
40 .equ TSS_SEGMENT, 0x40
44 ASM_PFX(gcSmiHandlerTemplate):
47 .byte 0xbb # mov bx, imm16
48 .word _GdtDesc - _SmiEntryPoint + 0x8000
49 .byte 0x2e,0xa1 # mov ax, cs:[offset16]
50 .word DSC_OFFSET + DSC_GDTSIZ
52 movl %eax, %cs:(%edi) # mov cs:[bx], ax
53 .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
54 .word DSC_OFFSET + DSC_GDTPTR
56 movw %ax, %bp # ebp = GDT base
59 # Patch ProtectedMode Segment
60 .byte 0xb8 # mov ax, imm16
61 .word PROTECT_MODE_CS # set AX for segment directly
62 movl %eax, %cs:-2(%edi) # mov cs:[bx - 2], ax
63 # Patch ProtectedMode entry
64 .byte 0x66, 0xbf # mov edi, SMBASE
65 ASM_PFX(gSmbase): .space 4
67 lea ((Start32bit - _SmiEntryPoint) + 0x8000)(%edi), %ax
68 movw %ax, %cs:-6(%edi)
71 andl $0x9ffafff3, %ebx
82 movw $PROTECT_MODE_DS, %ax
88 .byte 0xbc # mov esp, imm32
89 ASM_PFX(gSmiStack): .space 4
90 movl $ASM_PFX(gSmiHandlerIdtr), %eax
95 .byte 0xb8 # mov eax, imm32
96 ASM_PFX(gSmiCr3): .space 4
99 # Need to test for CR4 specific bit support
102 cpuid # use CPUID to determine if specific CR4 bits are supported
103 xorl %eax, %eax # Clear EAX
104 testl $BIT2, %edx # Check for DE capabilities
108 testl $BIT6, %edx # Check for PAE capabilities
112 testl $BIT7, %edx # Check for MCE capabilities
116 testl $BIT24, %edx # Check for FXSR capabilities
120 testl $BIT25, %edx # Check for SSE capabilities
123 L12: # as cr4.PGE is not set here, refresh cr3
124 movl %eax, %cr4 # in PreModifyMtrrs() to flush TLB.
126 orl $0x080010000, %ebx # enable paging + WP
128 leal DSC_OFFSET(%edi),%ebx
129 movw DSC_DS(%ebx),%ax
131 movw DSC_OTHERSEG(%ebx),%ax
135 movw DSC_SS(%ebx),%ax
138 cmpb $0, ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
142 movb $0x89, (TSS_SEGMENT + 5)(%ebp) # clear busy flag
143 movl $TSS_SEGMENT, %eax
147 # jmp _SmiHandler # instruction is not needed
153 movl $ASM_PFX(CpuSmmDebugEntry), %eax
158 movl $ASM_PFX(SmiRendezvous), %eax
163 movl $ASM_PFX(CpuSmmDebugExit), %eax
169 ASM_PFX(gcSmiHandlerSize): .word . - _SmiEntryPoint